CN109818745A - Internet of Things information security chip - Google Patents
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- CN109818745A CN109818745A CN201711166972.8A CN201711166972A CN109818745A CN 109818745 A CN109818745 A CN 109818745A CN 201711166972 A CN201711166972 A CN 201711166972A CN 109818745 A CN109818745 A CN 109818745A
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/50—Reducing energy consumption in communication networks in wire-line communication networks, e.g. low power modes or reduced link rate
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Abstract
The invention discloses a kind of Internet of Things information security chip, including central processing unit, dynamic memory, flash memory, SM2 Encryption Algorithm unit, SM3 Encryption Algorithm unit, SM4 Encryption Algorithm unit, AES encryption algorithm unit, real random number generator, physics unclonable function circuit, I2C interface, UART interface, SPI interface, I/O mouthfuls, jtag interface and the timer interconnected by on-chip bus；Real random number generator is for generating true random number, physics unclonable function circuit is generated for chip authentication and key, when needing using key, the true random number that real random number generator generates is input to physics unclonable function circuit by on-chip bus, the unique response sequence of physics unclonable function circuit output, the response sequence are key.Encryption and decryption arithmetic speed of the present invention is very fast, it is not reproducible with less hardware resource consumption and lower power consumption, key and steal, safe-guarding and anti-counterfeiting it is higher ranked.
Description
Technical field
The present invention relates to information security field, in particular to a kind of Internet of Things information security chip.
Background technique
It is the epoch of Information technology high speed development now, internet is quickly becoming the carrier of all trades and professions, pushes row
The progress of industry, and Internet of Things greatly improves industry production and people as the basic medium and pioneer that improve Internet application
The efficiency lived.Its application is referred to as the third wave that world information industry develops after computer, internet.With
This simultaneously, the safety issue of Internet of Things is also paid close attention to by people.
In order to ensure information safety, Password Management office, country, China proposes SM2 curve public key in December, 2010
Cryptographic algorithm, SM3 cryptographic Hash algorithm and SM4 block cipher.Effective combination of three kinds of Encryption Algorithm can meet a variety of
The demand for security of data encrypting and deciphering, authentication and data integrity, authenticity in cipher application.To pacify for China's information
Effective guarantee is provided entirely.
Unclonable function based on moderator is a kind of way of realization of the physics unclonable function (PUF) on silicon,
The main manufacturing process deviation using device and the physical randomness generated extract and the unique relevant characteristic quantity of the object.
Can be with the corresponding object of unique identification by this feature amount, and this feature amount can not be replicated, because of the work in production process
Skill deviation can not be replicated.Therefore, the PUF based on semiconductor technology has non-reproduction, uniqueness, stability, exempts from
The property of epidemic disease intrusive mood attack.Popular symmetric encipherment algorithm AES, SM4 etc. is needed key storage to non-volatile at present
Property reservoir inside, this is easy to will receive intrusive attack, causes key to be replicated and steals.And the moderator PUF based on silicon
Intrusive attack can be then prevented, prevents key to be replicated and steals, can be applied to chip anti-counterfeit recognition field.
It is the reflection of nature random physical process using the real random number generator (TRNG) that physical method is realized, even if
All information such as TRNG algorithm are exposed, and can not also guess as a result, the random number that the TRNG of i.e. high quality is generated never has
It is standby periodical.Therefore in information safety system, TRNG plays important role, such as data encryption, key management, public key
With private key generation, digital signature, identity authentication etc..
With the rapid development of integrated circuit fabrication process, system on chip SoC comes into being.SoC is greatly reduced
System volume, improves the performance of system；SoC is high, small in size with its integrated level, power consumption is few, good reliability, product come out, and the period is short
The advantages that be more and more widely used.However software cryptography mode is used in some products of existing market, lead to data
Enciphering rate is slow, the period is long, while there are also the encryptions of some products to be completed completely by hardware, although fast speed, chip area
It is larger, power consumption is higher, be unable to satisfy the low-power consumption requirement of internet of things product.Meanwhile almost most products all will in the market
Key is saved in non-volatile memory, to be highly susceptible to intrusive attack, is caused key to be replicated and is stolen.These are asked
Topic seriously restricts the universal and development of Internet of Things, brings great security risk to internet of things product.
Summary of the invention
The technical problem to be solved in the present invention is that in view of the above drawbacks of the prior art, providing a kind of encryption and decryption operation
Fast speed, it is not reproducible with less hardware resource consumption and lower power consumption, key and steal, safe-guarding and anti-counterfeiting grade compared with
High Internet of Things information security chip.
The technical solution adopted by the present invention to solve the technical problems is: constructing a kind of Internet of Things information security chip, wraps
Include central processing unit, dynamic memory, flash memory, SM2 Encryption Algorithm unit, SM3 Encryption Algorithm unit, SM4 Encryption Algorithm unit,
AES encryption algorithm unit, real random number generator, physics unclonable function circuit, I2C interface, UART interface, SPI interface,
I/O mouthfuls, jtag interface and timer, are equipped with register in the SM4 Encryption Algorithm unit, in the central processing unit connection sheet
Bus realizes adding for data for controlling the SM2 Encryption Algorithm unit, SM3 Encryption Algorithm unit and SM4 Encryption Algorithm unit
Close, decryption and signature sign test, control the generation of the operating mode and true random number of the real random number generator, described in control
The operating mode of physics unclonable function circuit and the key for reading physics unclonable function circuit evolving, and will be described
Key sends the SM2 Encryption Algorithm unit, SM3 Encryption Algorithm unit, SM4 Encryption Algorithm unit or AES encryption algorithm list to
Member controls the communication of the I2C interface, UART interface and SPI interface realization and the equipment of chip exterior, controls I/O mouthfuls described
Realize the control to external equipment and the work of the control timer；
The dynamic memory connects the on-chip bus, for storing the ephemeral data being currently running, the flash memory with
The on-chip bus connection is used for store code and constant, and the SM2 Encryption Algorithm unit connect with the on-chip bus, uses
In the point processing and modular arithmetic of realizing elliptic curve, the SM3 Encryption Algorithm unit connect with the on-chip bus, for realizing
Extension of message and Iteration Contraction in SM3 cryptographic Hash algorithm, message filling and message are grouped and are realized by the central processing unit,
The central processing unit, which passes through key and the data for needing to encrypt or decrypt in described, to be always input in register, described
SM4 Encryption Algorithm unit completes encryption or decryption operation, is sent by the on-chip bus to the central processing unit and reads number
According to notice, the AES encryption algorithm unit connect with the on-chip bus, for real under the control of the central processing unit
The secret communication of existing data；
The real random number generator is connect, for generating true random number with the on-chip bus, and will be described truly random
Number is stored in the flash memory, and the true random number is for generating the key, when needing using the key, it is described very with
Machine number is input to the physics unclonable function circuit by the on-chip bus, and the physics unclonable function circuit is received
A unique response sequence is exported after to the true random number, the response sequence is used as the key, and the physics is not
Functional circuit can be cloned to connect with the on-chip bus, for the generation of chip authentication and the key, the I2C interface,
UART interface and SPI interface are connect, for realizing the communication of the equipment with the chip exterior with the on-chip bus, described
I/O mouthfuls connect, for interacting with the external equipment with the on-chip bus, the jtag interface and the on-chip bus
Connection is used for program on-line debugging, and the timer is connect, for realizing timing with the on-chip bus.
It further include phaselocked loop in Internet of Things information security chip of the present invention, in the phaselocked loop and described
Bus connection, the clock signal for locking clock phase and the required frequency of generation.
Further include Power Management Unit in Internet of Things information security chip of the present invention, further includes power management
Unit, the Power Management Unit connect external power supply, for being powered to the Internet of Things information security chip.
In Internet of Things information security chip of the present invention, the external equipment include peripheral control unit, sensor,
LED, buzzer and key.
In Internet of Things information security chip of the present invention, the point processing includes dot product, point adduction times point.
In Internet of Things information security chip of the present invention, the modular arithmetic includes that mould adds, mould subtracts, modular multiplication and mould
It is inverse.
Implement Internet of Things information security chip of the invention, has the advantages that due to being equipped with central processing unit, moving
State memory, flash memory, SM2 Encryption Algorithm unit, SM3 Encryption Algorithm unit, SM4 Encryption Algorithm unit, AES encryption algorithm list
Member, real random number generator, physics unclonable function circuit, I2C interface, UART interface, SPI interface, I/O mouthfuls, JTAG connects
Mouth and timer, data encrypting and deciphering part biggish for operand is completed by hardware during secret communication, and centre
Manage device and be then responsible for the lesser data processing of operand and operation control, which under the premise of effectively improving encryption/decryption speed,
Chip area can be reduced and reduce power consumption, while the key in encryption process is by physics unclonable function circuit evolving, object
Input data needed for reason unclonable function circuit evolving key is generated by real random number generator, this mode can be supported effectively
Anti-invasion formula attack, avoids key from being replicated and steal, while physics unclonable function circuit can also be used in chip uniqueness
Identification and certification, further increase the security level of system, thus encryption and decryption arithmetic speed it is very fast, with less hardware resource
Consumption and lower power consumption, key it is not reproducible and steal, safe-guarding and anti-counterfeiting it is higher ranked.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of invention for those of ordinary skill in the art without creative efforts, can be with
It obtains other drawings based on these drawings.
Fig. 1 is the schematic diagram of internal structure in Internet of Things information security chip one embodiment of the present invention.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
In Internet of Things information security chip embodiment of the present invention, the internal structure of the Internet of Things information security chip is illustrated
Figure is as shown in Figure 1.In Fig. 1, which includes the central processor CPU interconnected by on-chip bus, moves
State memory SRAM, flash memory Flash, SM2 Encryption Algorithm unit 1 (i.e. the close SM2 rivest, shamir, adelman unit of state), SM3 encryption
Algorithm unit 2 (i.e. the close SM3 hash algorithm unit of state), SM4 Encryption Algorithm unit 3 (i.e. AM4 symmetric encipherment algorithm unit), AES
Encryption Algorithm unit 4 (i.e. AES symmetric encipherment algorithm unit), real random number generator TRNG, physics unclonable function circuit
PUF, I2C interface 5, UART interface 6, SPI interface 7, I/O mouth 8, jtag interface 9 and timer 10.
Specifically, being equipped with register (not shown) in SM4 Encryption Algorithm unit 3, central processor CPU can be direct
Access and control modules.Central processor CPU is low-power-consumption embedded processor, can use in day CK802, ARM
Cortex-M0 etc..Central processor CPU connects on-chip bus, calculates for responsible control SM2 Encryption Algorithm unit 1, SM3 encryption
Method unit 2 and SM4 Encryption Algorithm unit 3 realize the encryption, decryption and signature sign test of data, control real random number generator TRNG
Operating mode and true random number generation, control physics unclonable function circuit PUF operating mode and read object
The key that unclonable function circuit PUF is generated is managed, and sends key to SM2 Encryption Algorithm unit 1, SM3 Encryption Algorithm list
Member 2, SM4 Encryption Algorithm unit 3 or AES encryption algorithm unit 4, control I2C interface 5, UART interface 6 and SPI interface 7 realize with
The communication of the equipment of chip exterior, the content of communication can be the data after original data, encrypted data, decryption and
Other data etc., control I/O mouth 8 is realized to the control of external equipment and the work of control timer, realizes accurate timing
Deng.
It is noted that in the present embodiment, external equipment include peripheral control unit, sensor, LED, buzzer and by
Key etc., certainly, in practical applications, the type of external equipment can carry out respective extension as the case may be.
In the present embodiment, dynamic memory SRAM connection on-chip bus, for storing the ephemeral data being currently running, flash memory
Flash is connect, for store code and constant with on-chip bus.SM2 Encryption Algorithm unit 1, SM3 Encryption Algorithm unit 2 and SM4
Encryption Algorithm unit 3 is core secret unit, and the secret communication of data is mainly realized under the control of central processor CPU.
Specifically, SM2 Encryption Algorithm unit 1 is connect with on-chip bus, the point processing for realizing elliptic curve and mould are transported
It calculates, wherein point processing includes dot product, point adduction times point；Modular arithmetic includes that mould adds, mould subtracts, modular multiplication and mould are inverse.Each operation is all
It can individually be called by central processor CPU, there is very strong flexibility.SM2 Encryption Algorithm unit 1 and SM3 Encryption Algorithm list
Member 2, which matches, can be achieved the functions such as encryption, decryption, key exchange and signature sign test.
SM3 Encryption Algorithm unit 2 connect with on-chip bus, for realizing in SM3 cryptographic Hash algorithm extension of message and
Iteration Contraction, message filling and message grouping are realized that Hardware/Software Collaborative Design can improve SM3 operation by central processor CPU
Speed, and chip area and power consumption can be reduced, to meet the application demand of Internet of Things.
SM4 Encryption Algorithm unit 3 and AES encryption algorithm unit 4 use symmetric cryptographic algorithm, have speed fastly and
The advantages of strong security.Central processor CPU adds key and the data for needing to encrypt or decrypt by being always input to SM4 in piece
In the register of close algorithm unit 3, SM4 Encryption Algorithm unit 3 completes encryption or decryption operation, by on-chip bus to centre
It manages device CPU and sends the notice for reading data, AES encryption algorithm unit 3 is connect, in central processor CPU with on-chip bus
Control under realize data secret communication.
Real random number generator TRNG is connect with on-chip bus, the Internet of Things information security chip when first used, very
Randomizer TRNG generates one for generating the true random number of key, and the true random number is stored in flash memory Flash
In, when needing using key, which can be used as the input of physics unclonable function circuit PUF, physics can not gram
Grand functional circuit PUF can export a unique response sequence, which is key.Since the key and Internet of Things are believed
Cease the factors such as fabrication error when safety chip manufacture key that is related, therefore being generated by physics unclonable function circuit PUF
Has the characteristics that anti-intrusive attack and not reproducible.Central processor CPU can be by I2C interface 5, UART interface after reading key
6 and the data that transmit of SPI interface 7 carry out encryption and decryption, and the data after the completion of encryption and decryption are passed through into I2C interface 5, UART interface 6
It spreads out of with SPI interface 7.
Physics unclonable function circuit PUF is connect with on-chip bus, it may also be used for chip authentication, that is to say, that physics is not
Functional circuit PUF, which can be cloned, can be used for chip authentication, it can also be used to which the generation of key, unclonable characteristic have chip
Very strong antifalse effect.I2C interface 5, UART interface 6 and SPI interface 7 connect with on-chip bus, for realizing with outside chip
The communication of the equipment in portion, I/O mouth 8 are connect, for interacting with external equipment with on-chip bus, the Internet of Things information security core
Piece can also realize logic control, data operation etc., and controlled and interacted by I/O mouth 8.It is total in jtag interface 9 and piece
Line connection is used for program on-line debugging, can effectively improve programming efficiency.Timer 10 connect with on-chip bus, for realizing
Accurate timing.
Central processor CPU, SM2 Encryption Algorithm unit 1, SM3 encryption calculation are integrated in the Internet of Things information security chip
The hardware modules such as method unit 2, SM4 Encryption Algorithm unit 3 and AES encryption algorithm unit 4.During secret communication, for fortune
The biggish data encrypting and deciphering part of calculation amount is completed by hardware, and central processor CPU is then responsible for the lesser data processing of operand
And operation control, which can reduce chip area and reduce power consumption under the premise of effectively improving encryption/decryption speed.Add simultaneously
Key in decrypting process is generated by physics unclonable function circuit PUF, and physics unclonable function circuit PUF generates key
Required input data is generated by real random number generator TRNG, this mode can be effective against intrusive attack, avoids key
It is replicated and steals.Physics unclonable function circuit PUF can also be used in the identification of chip uniqueness and certification simultaneously, further mention
The safe-guarding and anti-counterfeiting grade of high system.
The Internet of Things information security chip also has I2C interface 5, UART interface 6, SPI interface 7, I/O mouth 8 and timing
Device 10 etc. can satisfy the application demand under a variety of occasions.Central processor CPU can be with independent access SM2 Encryption Algorithm unit
1, SM3 Encryption Algorithm unit 2, SM4 Encryption Algorithm unit 3, AES encryption algorithm unit 4, real random number generator TRNG and physics
Unclonable function circuit PUF has very strong flexibility to effectively improve the flexibility and use scope of chip.This hair
Bright encryption and decryption arithmetic speed is very fast；With less hardware resource consumption and lower power consumption；Key is not reproducible and steals；It should
Internet of Things information security chip can accomplish that uniqueness identifies, and unclonable.
In the present embodiment, which further includes phaselocked loop 11, phaselocked loop 11 connect with on-chip bus,
Clock signal for frequency needed for locking clock phase and generating.The Internet of Things information security chip further includes power management list
Member 12, Power Management Unit 12 are integrated in the inside of the Internet of Things information security chip, and Power Management Unit 12 connects external electrical
Source, for being powered to the Internet of Things information security chip, guarantee the operation is stable of chip.
In short, the present invention, which provides one kind, is integrated with 32 low power processors (central processor CPU), SM2 Encryption Algorithm
Unit 1, SM3 Encryption Algorithm unit 2, SM4 Encryption Algorithm unit 3, AES encryption algorithm unit 4, real random number generator TRNG,
The Internet of Things information security chip of physics unclonable function circuit PUF, timer 10 and peripheral interface.Encryption and decryption of the present invention
Arithmetic speed is very fast, it is not reproducible with less hardware resource consumption and lower power consumption, key and steal, security level compared with
It is high.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all in essence of the invention
Within mind and principle, any modification, equivalent replacement, improvement and so on be should all be included in the protection scope of the present invention.
Claims (6)
1. a kind of Internet of Things information security chip, which is characterized in that add including central processing unit, dynamic memory, flash memory, SM2
Close algorithm unit, SM3 Encryption Algorithm unit, SM4 Encryption Algorithm unit, AES encryption algorithm unit, real random number generator, object
Reason unclonable function circuit, I2C interface, UART interface, SPI interface, I/O mouthfuls, jtag interface and timer, the SM4 add
Register is equipped in close algorithm unit, the central processing unit connects on-chip bus, for controlling the SM2 Encryption Algorithm list
Member, SM3 Encryption Algorithm unit and SM4 Encryption Algorithm unit realize the encryption, decryption and signature sign test of data, control it is described very with
The generation of the operating mode and true random number of machine number generator controls the operating mode of the physics unclonable function circuit
And read physics unclonable function circuit evolving key, and by the key send to the SM2 Encryption Algorithm unit,
SM3 Encryption Algorithm unit, SM4 Encryption Algorithm unit or AES encryption algorithm unit, control the I2C interface, UART interface and
SPI interface realizes the communication with the equipment of chip exterior, controls the existing control and control institute to external equipment of the I/O cause for gossip
State the work of timer；
The dynamic memory connects the on-chip bus, for storing the ephemeral data being currently running, the flash memory with it is described
On-chip bus connection is used for store code and constant, and the SM2 Encryption Algorithm unit is connect, for real with the on-chip bus
The point processing and modular arithmetic, the SM3 Encryption Algorithm unit of existing elliptic curve are connect, for realizing SM3 with the on-chip bus
Extension of message and Iteration Contraction in cryptographic Hash algorithm, message filling and message are grouped and are realized by the central processing unit, institute
Central processing unit is stated by key and needs encryption or the data decrypted by being always input in register in described, the SM4
Encryption Algorithm unit completes encryption or decryption operation, is sent by the on-chip bus to the central processing unit and reads data
Notice, the AES encryption algorithm unit are connect, for realizing number under the control of the central processing unit with the on-chip bus
According to secret communication；
The real random number generator connect with the on-chip bus, deposits for generating true random number, and by the true random number
Storage is in the flash memory, and the true random number is for generating the key, when needing using the key, the true random number
It is input to the physics unclonable function circuit by the on-chip bus, the physics unclonable function circuit receives institute
State and export a unique response sequence after true random number, the response sequence is used as the key, the physics can not gram
Grand functional circuit is connect, for the generation of chip authentication and the key with the on-chip bus, and the I2C interface, UART connect
Mouth and SPI interface are connect, for realizing the communication of the equipment with the chip exterior with the on-chip bus, I/O mouthfuls described
It is connect with the on-chip bus, for being interacted with the external equipment, the jtag interface connect with the on-chip bus,
For program on-line debugging, the timer is connect, for realizing timing with the on-chip bus.
2. Internet of Things information security chip according to claim 1, which is characterized in that it further include phaselocked loop, the locking phase
Ring is connect, for the clock signal of frequency needed for locking clock phase and generating with the on-chip bus.
3. Internet of Things information security chip according to claim 2, which is characterized in that it further include Power Management Unit, institute
State Power Management Unit connection external power supply, for being powered to the Internet of Things information security chip.
4. Internet of Things information security chip according to claim 3, which is characterized in that the external equipment includes external control
Device, sensor, LED, buzzer and key processed.
5. Internet of Things information security chip according to claim 4, which is characterized in that the point processing includes dot product, point
Adduction times point.
6. according to claim 1 to Internet of Things information security chip described in 5 any one, which is characterized in that the modular arithmetic
Subtract including mould plus mould, modular multiplication and mould it is inverse.
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| CN114584297A (en) * | 2022-03-01 | 2022-06-03 | 广东工业大学 | Encryption and decryption system and encryption and decryption method based on physical unclonable technology |
| CN114584297B (en) * | 2022-03-01 | 2024-02-27 | 广东工业大学 | Encryption and decryption system and encryption and decryption method based on physical unclonable technology |
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