CN109752603B - Synchronous sampling device of space electric field detector - Google Patents
Synchronous sampling device of space electric field detector Download PDFInfo
- Publication number
- CN109752603B CN109752603B CN201811502625.2A CN201811502625A CN109752603B CN 109752603 B CN109752603 B CN 109752603B CN 201811502625 A CN201811502625 A CN 201811502625A CN 109752603 B CN109752603 B CN 109752603B
- Authority
- CN
- China
- Prior art keywords
- dsp
- analog
- synchronous
- digital converter
- elf
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
The invention discloses a synchronous sampling device of a space electric field detector, which adopts a mixed mode of daisy chain connection of a plurality of analog-to-digital converters (ADC), a clock frequency division and synchronization circuit and host interface (HPI) handshake between double Digital Signal Processor (DSP) systems, realizes multi-band and multi-channel synchronous sampling of the space electric field detector, has the advantages of low occupation of the system during machine operation, easy expansion, stable and controllable synchronization relation and the like, and can meet the synchronous sampling requirement of performing multi-band and multi-channel data acquisition by adopting an acquisition system with 2 or more DSPs.
Description
Technical Field
The invention belongs to the technical field of space environment detection, and particularly relates to a synchronous sampling device of a space electric field detector.
Background
The space electric field detector needs to collect signals of ELF (6 Hz-2.2 kHz) and VLF (1.8 kHz-20 kHz) frequency bands, and in order to realize the combined observation of space electric fields spanning different frequency bands, a stable time sequence synchronization relation needs to be established between data collection of different frequency bands. Meanwhile, in order to detect the space electric field vector, each measurement channel of the same frequency band needs to be synchronously acquired. Therefore, it is necessary to design a circuit and a software system capable of realizing multi-band and multi-channel synchronous acquisition.
Disclosure of Invention
In view of this, the present invention provides a synchronous sampling device for a space electric field detector, which can realize multi-band and multi-channel synchronous sampling of the electric field detector and meet the requirement of high-precision detection of a space electric field.
A synchronous sampling device suitable for a space electric field detector comprises a clock source (1), a clock driving circuit (2), a DSP frequency division circuit (3), a master DSP (4), a slave DSP (5), a synchronous logic circuit (6), a sampling clock frequency division circuit (7), an ELF frequency band analog-to-digital converter group (8) and a VLF frequency band analog-to-digital converter group (9);
the ELF frequency band analog-to-digital converter group (8) comprises 4 serial analog-to-digital converters adopting ELF frequency bands connected in a daisy chain, and an ELF frequency band serial data signal (16) is acquired according to an input ELF frequency band sampling clock signal (14) and then output to the main DSP (4);
the VLF frequency band analog-to-digital converter group (9) comprises 4 VLF frequency band serial analog-to-digital converters connected by adopting a daisy chain, and an acquired VLF frequency band serial data signal (17) is output to the slave DSP (5);
the clock source (1) provides a system clock signal (10), and the system clock signal is respectively provided for the DSP frequency division circuit (3), the slave DSP (5), the synchronous logic circuit (6) and the sampling clock frequency division circuit (7) after being driven by the clock driving circuit (2);
the DSP frequency division circuit (3) divides the frequency of a system clock, and a clock signal divided into ELF frequency ranges provides the system clock for the main DSP (4);
the sampling clock frequency division circuit (7) divides a system clock signal (10), generates an ELF frequency band sampling clock signal (14) which is connected to a main clock pin of each analog-to-digital converter in the ELF frequency band analog-to-digital converter group (8), and generates a VLF frequency band sampling clock signal (15) which is connected to a main clock pin of each analog-to-digital converter in the VLF frequency band analog-to-digital converter group (9);
the synchronous logic circuit (6) respectively generates an ELF frequency range synchronous signal (12) and a VLF frequency range synchronous signal (13) according to a clock signal (10) and an acquisition instruction signal (11) generated by the main DSP (4), and is connected to a synchronous pin of each analog-to-digital converter in the ELF frequency range analog-to-digital converter group (8) and the VLF frequency range analog-to-digital converter group (9);
the data bus interface of the master DSP (4) is connected with the HPI interface of the slave DSP (5) by a parallel bus (18), and the communication is carried out by adopting a DMA interrupt mode;
after the system is powered on or reset, the main DSP (4) generates a synchronous logic signal (11) to control an ELF frequency band analog-to-digital converter group (8) and a VLF frequency band analog-to-digital converter group (9) to start synchronous acquisition; the method comprises the steps that output data of an ELF frequency range analog-to-digital converter group (8) are counted once by a master DSP (4) when the master DSP receives the data, serial port DMA interruption is generated on the master DSP (4) by the output data, the master DSP (4) communicates with an HPI (high-performance interface) of a slave DSP (5) according to the interruption, counting is sent to the slave DSP (5), DMA interruption response of the HPI of the slave DSP (5) is triggered, and counting receiving time is recorded according to an internal clock after the slave DSP (5) receives counting; after more than two times of counting is received and corresponding time is recorded, the slave DSP (5) calculates the arrival time of the next counting according to the time interval of the two times of counting of the master DSP (4), then the next counting sent by the master DSP (4) is compared with the calculated time, after more than 5 times of comparison, if the comparison result is consistent, the system is shown to keep stable synchronous time sequence relation among different frequency bands, and the corresponding relation between the counting of the master DSP (4) and the internal clock of the slave DSP (5) is established; the master DSP (4) counts the received ELF frequency range serial data signals (16), and the slave DSP (5) marks the acquisition time of the VLF frequency range serial data signals (17) according to the internal clock; according to the counting on the ELF frequency range serial data signal (16) and the acquisition time of the VLF frequency range serial data signal (17), synchronous operation of different frequency data can be completed;
if the comparison result of the next counting and the calculated time sent by the main DSP (4) is inconsistent, the synchronization between different frequency bands of the system is no longer synchronous, the main DSP (4) regenerates the synchronous logic signal (11), and the synchronous time sequence between the different frequency bands of the system is reestablished.
The invention has the following beneficial effects:
the synchronous sampling device of the space electric field detector adopts a mixed mode of daisy chain connection of a plurality of analog-to-digital converters (ADC), a clock frequency division and synchronization circuit and host interface (HPI) handshake between double Digital Signal Processor (DSP) systems, realizes multi-band and multi-channel synchronous sampling of the space electric field detector, has the advantages of low occupation of the system during machine operation, easy expansion, stable and controllable synchronous relation and the like, and can meet the synchronous sampling requirement of multi-band and multi-channel data acquisition by adopting an acquisition system with 2 or more DSPs.
Drawings
Fig. 1 is a schematic block diagram of a synchronous sampling device of a space electric field detector according to the present invention, wherein:
the device comprises a 1-clock source, a 2-clock driving circuit, a 3-DSP frequency division circuit, a 4-master DSP, a 5-slave DSP, a 6-synchronous logic circuit, a 7-sampling clock frequency division circuit, an 8-ELF frequency band analog-to-digital converter group, a 9-VLF frequency band analog-to-digital converter group, a 10-clock signal, an 11-synchronous logic signal, a 12-ELF frequency band synchronous signal, a 13-VLF frequency band synchronous signal, a 14-ELF frequency band sampling clock signal, a 15-VLF frequency band sampling clock signal, a 16-ELF frequency band serial data signal, a 17-VLF frequency band serial data signal and an 18-parallel bus.
Detailed Description
The invention is described in detail below by way of example with reference to the accompanying drawings.
The invention relates to a synchronous sampling device suitable for a space electric field detector, which is shown in figure 1 and comprises: the device comprises a clock source 1, a clock driving circuit 2, a DSP frequency dividing circuit 3, a master DSP4, a slave DSP5, a synchronous logic circuit 6, a sampling clock frequency dividing circuit 7, an ELF frequency band analog-to-digital converter group 8 and a VLF frequency band analog-to-digital converter group 9.
The ELF frequency band analog-to-digital converter group 8 comprises 4 serial analog-to-digital converters adopting ELF frequency bands connected in a daisy chain mode, an ELF frequency band serial data signal 16 is collected according to an input ELF frequency band sampling clock signal 14 and then output to the main DSP4, and the main DSP4 realizes data reading in a serial DMA interrupt mode.
The VLF frequency band analog-to-digital converter group 9 comprises 4 serial analog-to-digital converters connected in daisy chain, the collected serial data signals 17 of the VLF frequency band are output to the slave DSP5, and the slave DSP5 realizes data reading by adopting a serial DMA interrupt mode.
The clock source 1 provides a system clock signal 10, and the system clock is respectively provided to the DSP frequency dividing circuit 3, the slave DSP5, the synchronous logic circuit 6 and the sampling clock frequency dividing circuit 7 after being driven by the clock driving circuit 2.
The DSP frequency dividing circuit 3 divides the system clock, and the clock signal divided into ELF bands supplies the system clock to the host DSP 4.
The sampling clock frequency division circuit 7 divides the frequency of a system clock signal 10, generates an ELF frequency band sampling clock signal 14 which is connected to a main clock pin of each analog-to-digital converter in the ELF frequency band analog-to-digital converter group 8, and generates a VLF frequency band sampling clock signal 15 which is connected to a main clock pin of each analog-to-digital converter in the VLF frequency band analog-to-digital converter group 9, so that the sampling clock frequency requirements of different frequency bands and the synchronous sampling requirements of the same frequency band are met.
The synchronous logic circuit 6 generates an ELF band synchronous signal 12 and a VLF band synchronous signal 13 respectively according to a clock signal 10 and an acquisition instruction signal 11 generated by the host DSP4, and is connected to the synchronous pins of the analog-to-digital converters in the ELF band analog-to-digital converter group 8 and the VLF band analog-to-digital converter group 9, so as to realize initial synchronization of acquisition timings of each band and each channel. The acquisition instruction signal 11 generated by the main DSP4 is generated according to actual use requirements, and generally includes a data acquisition start instruction, an acquisition end instruction, and the like; the clock signal 10 is used to calibrate the acquisition instruction signal 11, so that the acquisition instruction signal 11 is resynchronized, thereby generating an ELF band synchronizing signal 12 and a VLF band synchronizing signal 13 whose timings are perfectly aligned with the ELF band sampling clock signal 14 and the VLF band sampling clock signal 15, thereby ensuring that signals of different bands are synchronously acquired.
The data bus interface of the master DSP4 and the HPI interface of the slave DSP5 are connected by a parallel bus 18 and communicate by a DMA interrupt mode.
After the system is powered on or reset, the main DSP4 generates a synchronous logic signal 11 to control the ELF frequency band analog-to-digital converter group 8 and the VLF frequency band analog-to-digital converter group 9 to start synchronous acquisition; the master DSP4 counts once when receiving data, the output data generates serial DMA interrupt in the master DSP4, the master DSP4 communicates with the HPI interface of the slave DSP5 according to the interrupt, sends the count to the slave DSP5 and triggers the DMA interrupt response of the HPI interface of the slave DSP5, and the slave DSP5 records the counting time according to the internal clock after receiving one count; after receiving more than two times of counting and recording corresponding time, the slave DSP5 calculates the arrival time of the next counting according to the time interval of the two times of counting of the master DSP4, then compares the next counting sent by the master DSP4 with the calculated time, and after more than 5 times of comparison, if the comparison result is consistent, the system is shown to keep stable synchronous time sequence relation among different frequency bands, and accordingly, the corresponding relation between the counting of the master DSP4 and the internal clock of the slave DSP5 is established; the master DSP4 counts the received ELF frequency band serial data signals 16 and the slave DSP5 marks the acquisition time of the VLF frequency band serial data signals 17 according to the internal clock; because the corresponding relationship between the count of the master DSP4 and the internal clock of the slave DSP5 is established in advance, synchronous operation of data of different frequencies can be completed according to the count of the ELF band serial data signal 16 and the acquisition time of the VLF band serial data signal 17 during subsequent data processing.
If the comparison result of the next counting sent by the main DSP4 is inconsistent with the calculated time, which indicates that the different frequency bands of the system are not synchronized any more, the main DSP4 regenerates the synchronous logic signal 11, and reestablishes the synchronous timing sequence of the different frequency bands of the system.
In summary, the above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (1)
1. A synchronous sampling device suitable for a space electric field detector is characterized by comprising a clock source (1), a clock driving circuit (2), a DSP frequency dividing circuit (3), a master DSP (4), a slave DSP (5), a synchronous logic circuit (6), a sampling clock frequency dividing circuit (7), an ELF frequency band analog-to-digital converter group (8) and a VLF frequency band analog-to-digital converter group (9);
the ELF frequency band analog-to-digital converter group (8) comprises 4 serial analog-to-digital converters adopting ELF frequency bands connected in a daisy chain, and an ELF frequency band serial data signal (16) is acquired according to an input ELF frequency band sampling clock signal (14) and then output to the main DSP (4);
the VLF frequency band analog-to-digital converter group (9) comprises 4 VLF frequency band serial analog-to-digital converters connected by adopting a daisy chain, and an acquired VLF frequency band serial data signal (17) is output to the slave DSP (5);
the clock source (1) provides a system clock signal (10), and the system clock signal is respectively provided for the DSP frequency division circuit (3), the slave DSP (5), the synchronous logic circuit (6) and the sampling clock frequency division circuit (7) after being driven by the clock driving circuit (2);
the DSP frequency division circuit (3) divides the frequency of a system clock, and a clock signal divided into ELF frequency ranges provides the system clock for the main DSP (4);
the sampling clock frequency division circuit (7) divides a system clock signal (10), generates an ELF frequency band sampling clock signal (14) which is connected to a main clock pin of each analog-to-digital converter in the ELF frequency band analog-to-digital converter group (8), and generates a VLF frequency band sampling clock signal (15) which is connected to a main clock pin of each analog-to-digital converter in the VLF frequency band analog-to-digital converter group (9);
the synchronous logic circuit (6) respectively generates an ELF frequency range synchronous signal (12) and a VLF frequency range synchronous signal (13) according to a system clock signal (10) and an acquisition instruction signal (11) generated by the main DSP (4), wherein the ELF frequency range synchronous signal (12) is connected to a synchronous pin of each analog-to-digital converter in the ELF frequency range analog-to-digital converter group (8), and the VLF frequency range synchronous signal (13) is connected to a synchronous pin of each analog-to-digital converter in the VLF frequency range analog-to-digital converter group (9);
the data bus interface of the master DSP (4) is connected with the HPI interface of the slave DSP (5) by a parallel bus (18), and the communication is carried out by adopting a DMA interrupt mode;
after the system is powered on or reset, the main DSP (4) generates an acquisition instruction signal (11) to control an ELF frequency band analog-to-digital converter group (8) and a VLF frequency band analog-to-digital converter group (9) to start synchronous acquisition; the ELF frequency range analog-to-digital converter group (8) outputs data, the master DSP (4) counts once when receiving the data, the output data generates serial port DMA interruption in the master DSP (4), the master DSP (4) communicates with the HPI interface of the slave DSP (5) according to the interruption, sends counting to the slave DSP (5) and triggers the DMA interruption response of the HPI interface of the slave DSP (5), and the slave DSP (5) records the counting time according to an internal clock after receiving counting; after more than two times of counting is received and corresponding time is recorded, the slave DSP (5) calculates the next counting arrival time according to the time interval of the two times of counting of the master DSP (4), then the time of receiving the next counting of the slave DSP (5) is compared with the calculated time, after more than 5 times of comparison, if the comparison result is consistent, the system is shown to keep stable synchronous time sequence relation among different frequency bands, and the corresponding relation between the counting of the master DSP (4) and the internal clock of the slave DSP (5) is established; the master DSP (4) counts the received ELF frequency range serial data signals (16), and the slave DSP (5) marks the acquisition time of the VLF frequency range serial data signals (17) according to the internal clock; according to the counting on the ELF frequency range serial data signal (16) and the acquisition time of the VLF frequency range serial data signal (17), synchronous operation of different frequency data can be completed;
if the comparison result of the time of the next counting received by the slave DSP (5) is inconsistent with the calculated time, the result indicates that the different frequency bands of the system are not synchronous any more, the master DSP (4) regenerates the acquisition instruction signal (11) and reestablishes the synchronous time sequence of the different frequency bands of the system.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811502625.2A CN109752603B (en) | 2018-12-10 | 2018-12-10 | Synchronous sampling device of space electric field detector |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811502625.2A CN109752603B (en) | 2018-12-10 | 2018-12-10 | Synchronous sampling device of space electric field detector |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109752603A CN109752603A (en) | 2019-05-14 |
| CN109752603B true CN109752603B (en) | 2021-02-19 |
Family
ID=66403514
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811502625.2A Active CN109752603B (en) | 2018-12-10 | 2018-12-10 | Synchronous sampling device of space electric field detector |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109752603B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114706134A (en) * | 2021-07-30 | 2022-07-05 | 应急管理部国家自然灾害防治研究院 | Electric field detector data processing method and system |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1545257A (en) * | 2003-11-18 | 2004-11-10 | 欣 耿 | System and method for frequency range segregation and signal synthesis in broadband signal measurement |
| CN1588804A (en) * | 2004-09-10 | 2005-03-02 | 深圳市中实科技有限公司 | Method and its device for broad band signal frequency band separating and signal synthesizing |
| CN1973251A (en) * | 2004-06-24 | 2007-05-30 | 泰拉丁公司 | Synchronization between low frequency and high frequency digital signals |
| CN103593487A (en) * | 2013-09-06 | 2014-02-19 | 北京理工大学 | Signal acquisition processing board |
| EP1987637B1 (en) * | 2006-02-17 | 2015-04-08 | Microchip Technology Germany GmbH | System and method for transferring data packets through a communication system |
| CN105871378A (en) * | 2016-03-24 | 2016-08-17 | 航天科技控股集团股份有限公司 | Sync circuit of multichannel high speed ADCs and DACs |
| CN106406174A (en) * | 2016-09-29 | 2017-02-15 | 中国电子科技集团公司第二十九研究所 | Multi-module multi-channel acquisition synchronization system and the working method thereof |
| CN106444505A (en) * | 2015-10-14 | 2017-02-22 | 北京信息科技大学 | Multichannel synchronizing signal collection system |
| CN108761524A (en) * | 2018-05-21 | 2018-11-06 | 山东大学 | A kind of portable tunnel seismic wave forward probe system and method |
-
2018
- 2018-12-10 CN CN201811502625.2A patent/CN109752603B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1545257A (en) * | 2003-11-18 | 2004-11-10 | 欣 耿 | System and method for frequency range segregation and signal synthesis in broadband signal measurement |
| CN1973251A (en) * | 2004-06-24 | 2007-05-30 | 泰拉丁公司 | Synchronization between low frequency and high frequency digital signals |
| CN1588804A (en) * | 2004-09-10 | 2005-03-02 | 深圳市中实科技有限公司 | Method and its device for broad band signal frequency band separating and signal synthesizing |
| EP1987637B1 (en) * | 2006-02-17 | 2015-04-08 | Microchip Technology Germany GmbH | System and method for transferring data packets through a communication system |
| CN103593487A (en) * | 2013-09-06 | 2014-02-19 | 北京理工大学 | Signal acquisition processing board |
| CN106444505A (en) * | 2015-10-14 | 2017-02-22 | 北京信息科技大学 | Multichannel synchronizing signal collection system |
| CN105871378A (en) * | 2016-03-24 | 2016-08-17 | 航天科技控股集团股份有限公司 | Sync circuit of multichannel high speed ADCs and DACs |
| CN106406174A (en) * | 2016-09-29 | 2017-02-15 | 中国电子科技集团公司第二十九研究所 | Multi-module multi-channel acquisition synchronization system and the working method thereof |
| CN108761524A (en) * | 2018-05-21 | 2018-11-06 | 山东大学 | A kind of portable tunnel seismic wave forward probe system and method |
Non-Patent Citations (1)
| Title |
|---|
| 基于PXIe总线的高速数据采集程控系统;刘玄烨 等;《机电工程》;20150131;第32卷(第1期);第60-63页 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109752603A (en) | 2019-05-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| RU164156U1 (en) | HIGH SPEED MULTI-CHANNEL DATA COLLECTION BOARD | |
| CN106385256A (en) | Multi-channel parallel acquisition system with storage function and synchronous recognition function | |
| JP2018534686A (en) | Apparatus and method for synchronizing controllers and sensors | |
| CN107994896B (en) | Multi-channel high-speed pulse counting system and counting method | |
| CN109752603B (en) | Synchronous sampling device of space electric field detector | |
| CN107104670A (en) | Many board synchronous collection methods of base when triggering PLL based on pulse | |
| SG11201803662SA (en) | Method for synchronising data converters by means of a signal transmitted from one to the next | |
| CN203455835U (en) | Bus triggering backplate applied to PXI (PCI extension for instrumentation) test platform | |
| CN109683567A (en) | Based on system clock synchronizing method in RS485 network | |
| CN103197139A (en) | Clock frequency test method and clock frequency test circuit | |
| EP3403186A1 (en) | Bus ownership hand-off techniques | |
| US9116561B2 (en) | Time reference systems for CPU-based and optionally FPGA-based subsystems | |
| CN203883848U (en) | Clock synchronization device for intelligent substation synchronization tests | |
| CN109543811B (en) | Counting circuit, counting method and chip | |
| CN104485962A (en) | Portable data acquisition system and acquisition method thereof | |
| CN212646963U (en) | Multichannel nuclear magnetic resonance imaging spectrometer system | |
| CN109407752A (en) | The synchronous GIS breaker on-line monitoring system of clock is realized in RS485 communication | |
| CN114063703A (en) | Data synchronization method and device, data processing equipment and storage medium | |
| CN113960413A (en) | Time synchronization method for collecting unit and collecting unit in fault indicator | |
| CN209842446U (en) | Digital frequency synthesis chip full-coherent signal source circuit | |
| CN103645658B (en) | A kind of phase synchronization method of multi-disc signal converter, device and FPGA controller | |
| WO2016183955A1 (en) | Speech synchronization method and device | |
| CN205195718U (en) | Embedded network synchronization system based on FPGA | |
| CN111061145B (en) | Time delay settable time interval measuring device and measuring method based on FPGA | |
| CN106027192B (en) | A kind of parallel data synchronous acquisition device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |