CN109726063A - A kind of automation evaluation method of behavior based on instruction to the Verilog MIPS processor realized - Google Patents
A kind of automation evaluation method of behavior based on instruction to the Verilog MIPS processor realized Download PDFInfo
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Abstract
The present invention proposes that a kind of behavior based on instruction belongs to teaching tool field to the automation evaluation method of the Verilog MIPS processor realized.It include: to execute MIPS assembler language by the instruction sequence of write-in register and write-in data storage in construction same period to write test program；Display sentence is inserted into general register and data memory module as requested calls the Simulation Engineering of hardware emulating software creation to emulate to by tcl script；It initially dissolves in two queues, whether IA, writing address and the content of write-in for comparing two records are identical；The evaluation result of comprehensive each item instruction behavior, obtains the correctness evaluation result of MIPS processor.The present invention judges the correctness of MIPS processor and to the automated teaching householder method for the related prompt message that makes mistake, and improves efficiency of teaching, reduces the debugging difficulty of learner.
Description
Technical field
The invention belongs to teaching tool field, it is related to the MIPS write for Verilog (hardware description language)
The automation evaluation method of processor, this method judge the correctness of MIPS processor from instruction behavior angle, and
It was found that providing the prompt information that can help developer's orientation problem when mistake, it is suitable for Principles of Computer Composition, computer body
MIPS processor related experiment in the courses such as architecture.
Background of invention
MIPS (Microprocessor without Interlocked Pipeline Stages, no inner interlocked stream
Water grade microprocessor) framework is a kind of compacting instruction set processor framework proposed by Stanford University, all fingers in the framework
Order is all made of same word length, realizes that details is visible to programmer inside processor.Based on above-mentioned characteristic, realized by autonomous Design
MIPS processor can help learner to understand Principles of Computer Composition and Computer Architecture relevant knowledge, manage correlation
Booster action is played by the teaching of course.
Verilog is a kind of hardware description language (Hardware Description Language), and crystal can be used
The different abstract levels such as pipe grade, logic gate level, Method at Register Transfer Level, behavioral scaling model digital circuit, are widely used in microelectronics
Industry.The digital circuit modeled using Verilog, can be mapped as logic gate level netlist by logic synthesis tool, further, benefit
FPGA (Field Programmable Gate Array, field programmable gate array), ASIC can be produced with netlist
Integrated circuit device such as (Application-Specific Integrated Circuit, specific integrated circuits).
Existing MIPS processor correctness evaluation method can be divided mainly into waveform comparison method and register (data storage
Device) comparison method.Simulation waveform is analyzed and is compared with needing to carry out Cycle by Cycle for the former, is typically only capable to refer to individual instructions or on a small quantity
The simulation waveform of order is judged, while judge also being required to have deep understanding to MIPS instruction set and framework, it is difficult to automatic
Change and complete, manpower costs are big, and misdetection rate is high.The latter is then by general register and data storage before and after execution test program
The comparison of middle institute's storage content, to judge the correctness of MIPS processor, this method, which has the drawback that, can not position wrong hair
Raw specific location, further, since MIPS processor only has 32 general registers, when test program design is incomplete,
Successor instruction covers the write-in to general register or data storage before this, in fact it could happen that leakage wrong in implementation procedure
Sentence.
Summary of the invention
For in field research, MIPS processor designs related experiment correctness and judges difficult, learner's debugging the present invention
The problems such as inconvenient, proposing one kind, behavior is to the automation evaluation method of the Verilog MIPS processor realized based on instruction
The correctness of a kind of pair of MIPS processor judge and to the automated teaching householder method of related prompt message of making mistake, with
Efficiency of teaching is improved, the debugging difficulty of learner is reduced.
Behavior based on instruction of the invention includes as follows to the automation evaluation method of the Verilog MIPS processor realized
Step:
Step 1: writing test program using MIPS assembler language, test program is collected, obtain MIPS machine generation
The initialization content of code and data storage.
Step 2: the test program write in load step 1 in the Mars after customization, opening state equipments of recording
Statement Recorder is linked to current operating environment, then executes test program.Statement Recorder will be transported
The write-in behavior of general register, MD register and data storage records in the form of text during row, and exports as note
Record file A.
In the step 2, when recording the write-in behavior of general register, MD register and data storage, often
Item record is write comprising generating IA, current write request hexadecimal writing address and the hexadecimal of current write request
Enter content；In derived record file A, every row includes a write-in behavior record, and record sequence cannot be upset.
Step 3: hardware emulating software being called by tcl script, creates Simulation Engineering, and by MIPS processor to be judged
Verilog source file (collection), the machine code in step 1, data storage initialization content motivate file together with testbench
Engineering is added, engineering is emulated according to preset emulation duration.
It is built-in in the general register and data memory module of the MIPS processor to be judged of the step 3
Display order when each write request in simulation process reaches, exports following information to standard output stream (STDOUT):
Current emulation moment, IA, current write request hexadecimal writing address and the hexadecimal for generating current write request
Content is written.It is record file B by the text information dump in standard output stream after emulation.Record every row in file B
It is recorded comprising a write request, record sequence cannot be upset.
Step 4: the write request of the general register and data storage that record in file A is pressed in two queues of initialization
Sequence is stored in two queues respectively；The write request in record file B is read line by line, and corresponding queue is chosen according to the type of request
Head of the queue record, whether IA (program counter value), writing address and the content of write-in for comparing two records identical,
Then think that the instruction execution is correct if they are the same, otherwise it is assumed that the preamble instruction execution of the instruction or the instruction malfunctions.
In the step 4, also screened at monocycle or multicycle using the current emulation moment recorded in step 3
Reason device and pipeline processor, specific method are: adjacent general register being added in the test program constructed in step 1 and writes
Enter instruction and data memory write instruction, moment difference is written if it does not exist and is no more than for the write request in detection record file B
The general register and data storage write-in record of one emulation cycle, then prove that the MIPS processor is not pipeline processes
Device.
Step 5: the evaluation result of each item instruction behavior, the correctness for obtaining MIPS processor judge knot in combining step 4
Fruit, and for the MIPS processor of mistake, it can be to the position range for a faulting instruction of informing against.
The present invention advantage and has the active effect that compared to existing MIPS processor correctness evaluation method
(1) method proposed by the invention can carry out fine-grained analysis to simulation result, not only avoid complexity
Waveform analysis, additionally it is possible to which more accurate faulting instruction position letter is provided while providing MIPS processor correctness evaluation result
Breath, assisted learning person modify to design, improve exploitation debugging efficiency.
(2) method proposed by the invention reduce to MIPS processor design constraint condition, learner only need by
Display sentence is inserted into general register and data memory module by as requested, without paying close attention to module name, module
The details such as hierarchical relationship.
(3) method proposed by the invention utilizes the design feature of MIPS pipeline processor, by constructing same period
Interior write-in register and the instruction sequence that data storage is written, realize and handle MIPS instruction set monocycle (or multicycle)
The examination of device and pipeline processor has the advantages of versatility is good, confidentiality is strong, will not routinely be obscured method interference, keeps away
Exempt from learner and pretends to be the realization higher pipeline processes of difficulty using realization difficulty lower monocycle (or multicycle) processor
Device.
Detailed description of the invention
Fig. 1 is the stream the present invention is based on instruction behavior to the automation evaluation method of the Verilog MIPS processor realized
Journey schematic diagram；
Fig. 2 is general register write request record order example；
Fig. 3 is data storage write request record order example.
Specific embodiment
Illustrate technical solution of the present invention with reference to the accompanying drawings and examples.
The present invention is based on instruction behaviors to the automation evaluation method of the Verilog MIPS processor realized, such as Fig. 1 institute
Show, including following five steps.
Step 1: writing test program using MIPS assembler language, collected by assembler, obtain MIPS machine generation
The initialization content of code and data storage.Assembler used in MIPS assembler such as Mars and the embodiment of the present invention.
The initialization content of MIPS machine code i.e. command memory.
When writing test program using MIPS assembler language, can be needed according to teaching single in any combination instruction set or
A plurality of instruction, both can hand-coding, can also be generated by automatized script.
The initialization content of obtained command memory that collects and the initialization content of data storage, with independent text
The storage of this document form is read in by the $ readmemh order in Verilog source file to relational storage in emulation.
Step 2: the test program write in load step 1 in the Mars after customization, opening state equipments of recording
Statement Recorder is linked to current operating environment, then executes test program.Statement Recorder will be transported
The write-in behavior of general register, MD register (hi, lo) and data storage records in the form of text during row, and
Export as record file A.Mars after the customization refers to and increases state recording tool on the basis of original Mars
Statement Recorder。
When recording the write-in behavior of general register, MD register (hi, lo) and data storage, every record
IA (hexadecimal program Counter Value), current write request hexadecimal write-in ground comprising generating current write request
Content is written in location and hexadecimal, different according to instruction, and write-in content-length can be 1-4 byte.Each item record is mutual
It is independent, can not sequentially it upset.
In derived record file A, every row includes a write-in behavior record, and record sequence can not be upset, with file knot
Beam accords with EOF ending.
Step 3: hardware emulating software being called by tcl (Tool Command Language) script, such as ISE Simulator, creation
Simulation Engineering, and will be in the command memory initialization in MIPS processor Verilog source file (collection) be judged, step 1
Hold, the data storage in step 1 initializes content together with general testbench excitation file addition engineering, according to preparatory
The emulation duration of setting emulates engineering.
In simulation process, general register and as depicted in figs. 1 and 2 built in data memory module in MIPS processor
$ display order when each write request is reached with certain format to standard output stream (STDOUT) output information.$
Every write request record of display order output includes: the current emulation moment is decimal integer, is free of unit；It generates
The IA of current write request is hexadecimal program Counter Value；Current write request hexadecimal writing address and ten
Content is written in senary.Different according to instruction, write-in content-length can be 1-4 byte, if do not need the examination monocycle (or
Multicycle) processor and pipeline processor, then currently emulation time information can omit.
As shown in Fig. 2, when general register write-in functions are called, will execute built-in $ display order, it is defeated
Moment time is currently emulated out；Generate the IA WPC of current write request；Current write request hexadecimal writing address
Waddr；And content Wdata is written in hexadecimal.Time is decimal integer, is free of unit.WPC is hexadecimal program meter
Number device value.Different according to instruction, write-in content-length can be 1-4 byte.
Similarly, as shown in figure 3, when data storage write-in functions are called, will execute built-in $ display life
It enables, exports current emulation moment time；Generate the IA PC of current write request；Current write request hexadecimal writing address
addr；And content din is written in hexadecimal.Time is decimal integer, is free of unit.WPC is hexadecimal program counting
Device value.Different according to instruction, write-in content-length can be 1-4 byte.
It is record file B by the text information dump in standard output stream after emulation.It records in file B, every row packet
It is recorded containing a write request, record sequence can not be upset, and be ended up with EOF.
The effect of tcl script used in this step is the alternative pattern interface operation Xilinx under the scenes such as server
ISE Design Suite tool realizes automatic test, improves testing efficiency.
The effect of the excitation file of testbench used in this step is: providing pumping signal, including week for MIPS processor
Phase property clock signal and reset signal.
Step 4: two queues of initialization will record the general register in file A and data memory write request by suitable
Sequence is stored in respectively in two queues；The write request in record file B is read line by line, and the head of the queue of corresponding queue is chosen according to its type
Record, whether IA (program counter value), writing address and the content of write-in for comparing two records are identical, if they are the same
Then think that the instruction execution is correct, otherwise it is assumed that the preamble instruction execution of the instruction or the instruction malfunctions.
Particularly, since the value perseverance of MIPS instruction integrated general register 0 (zero) is 0, when the register is written into
When, regardless of whether write-in behavior is recorded, it should be all regarded as correct behavior, and ignore the difference that content is written in record.
In the method for the present invention, using write request record in current emulation time information screen the monocycle (or multicycle)
Processor and pipeline processor, specific method are: adjacent general register being added in the test program constructed in step 1
Write instruction and data storage write instruction, it is inevitable same imitative due to the design feature of assembly line MIPS processor itself
General register and data storage are respectively written into true cycle.Write request in detection record file B, when being written if it does not exist
General register and data storage write-in record that difference is no more than an emulation cycle are carved, then proves the MIPS processor not
It is the pipeline processor of specification.
Be given below one instructs the compilation that can be used for screening the monocycle (or multicycle) processor formed to refer to by two
Enable sequence:
1:ori $ t1, $ t0,0xffff# are tied general register $ t0 and immediate 0xffff progress or operation
Register $ t1 is written in fruit
The unit that address is 0 in data storage is written in the value of general register $ t1 by 2:sw $ t1,0 ($ 0) #
In the MIPS processor of Pyatyi flowing structure, when memory access pipelining-stage (MEM grades) executes instruction 2 data storage
When write operation, followed by write register pipelining-stage (WB grades) just execute instruction 1 general register write operation.?
During different Verilog is realized, the writing mode of data storage and general register may be rising edge write-in or failing edge
Write-in, but which kind of writing mode combination no matter is taken, in the MIPS processor of Pyatyi flowing structure, instruction 1 is write with instruction 2
Entering operation can complete in same emulation cycle, this is the feature that single processor cycle or multicycle processor can not simulate.
For screening the monocycle assembler of (or multicycle) processor and pipeline processor, refer to comprising an energy
Behavior is written in the instruction and an adjacent data storage that can generate for generating general register (non-0 register) write-in behavior
Successor instruction any assembler.
Step 5: the evaluation result of each item instruction behavior, the correctness for obtaining MIPS processor judge knot in combining step 4
Fruit, and for the MIPS processor of mistake, it can be to a faulting instruction relevant information of informing against, to help learner to find and solve
Certainly there are problems in design.
The first faulting instruction relevant information, using the evaluation method of behavior is found based on instruction in step 4
First item error write command (instruction of write-in register or data storage), can be likely to occur mistake for judged MIPS processor
Between the successor instruction and current write command of range shorter supreme one correct write command accidentally, in practical applications, the range
Interior instruction number is typically not greater than 3, can effectively help learner to find wrong root, quickly solve the problems, such as.
Claims (3)
1. a kind of behavior based on instruction includes the following steps: the automation evaluation method of the Verilog MIPS processor realized
Step 1: write test program using MIPS assembler language, test program collected, obtain MIPS machine code and
The initialization content of data storage；
Step 2: the test program write in load step 1 in Mars, opening state equipments of recording Statement
Recorder is linked to current operating environment, then executes test program, and Statement Recorder will lead in operational process
It is recorded in the form of text with the write-in behavior of register, MD register and data storage, and exports as record file A；
Step 3: hardware emulating software being called by tcl script, Simulation Engineering is created, by MIPS processor to be judged
Machine code, data storage initialization content in Verilog source file, step 1 are added together with testbench excitation file
Engineering emulates engineering according to preset emulation duration；
It is characterized in that,
In the step 2, when recording the write-in behavior of general register, MD register and data storage, every note
In record IA, current write request hexadecimal writing address and hexadecimal write-in comprising generating current write request
Hold；In derived record file A, every row includes a write-in behavior record, and record sequence cannot be upset；
It is built-in in the general register and data memory module of MIPS processor in simulation process in the step 3
Display order exports following information to standard output stream when each write request is reached: current emulation moment, generation are current
Content is written in IA, current write request hexadecimal writing address and the hexadecimal of write request；After emulation,
It is record file B by the text information dump in standard output stream；Recording every row in file B includes a write request record,
Record sequence cannot be upset；
Step 4: two queues of initialization divide the general register recorded in file A and data memory write request in order
It Cun Ru not be in two queues；The write request in record file B is read line by line, and the head of the queue of corresponding queue is chosen according to the type of request
Record, whether IA, writing address and the content of write-in for comparing two records are identical, then think that the instruction is held if they are the same
Row is correct, otherwise it is assumed that the preamble instruction execution of the instruction or the instruction malfunctions；
Step 5: the evaluation result of each item instruction behavior in combining step 4 obtains the correctness evaluation result of MIPS processor, and
And for the MIPS processor of mistake, to the position range for a faulting instruction of informing against；
Wherein, MIPS is no inner interlocked pipelining-stage microprocessor, and Verilog is hardware description language, and Mars is MIPS compilation
Running simulation device.
2. the method according to claim 1, wherein file B and record text will be being recorded in the step 4
When part A compares, when general register 0 is written into, regardless of whether write-in behavior is recorded, it is all regarded as correct behavior, and ignore
The difference of content is written in record.
3. the method according to claim 1, wherein also being discriminated using the current emulation moment in the step 4
Other monocycle or multicycle processor and pipeline processor are added in the test program constructed in step 1 adjacent general
Instruction and data memory write instruction is written in register, and moment phase is written in the write request in detection record file B if it does not exist
Difference is no more than the general register and data storage write-in record of an emulation cycle, then the MIPS processor is not assembly line
Processor.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110598320A (en) * | 2019-09-11 | 2019-12-20 | 上海高性能集成电路设计中心 | Instruction set simulator calibration method based on hardware simulation accelerator |
| CN110727584A (en) * | 2019-09-10 | 2020-01-24 | 无锡江南计算技术研究所 | Real-time comparison method of RTL (real time language) and reference model for pre-silicon verification of processor |
| CN116720554A (en) * | 2023-08-11 | 2023-09-08 | 南京师范大学 | Method for realizing multi-section linear fitting neuron circuit based on FPGA technology |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110727584A (en) * | 2019-09-10 | 2020-01-24 | 无锡江南计算技术研究所 | Real-time comparison method of RTL (real time language) and reference model for pre-silicon verification of processor |
| CN110598320A (en) * | 2019-09-11 | 2019-12-20 | 上海高性能集成电路设计中心 | Instruction set simulator calibration method based on hardware simulation accelerator |
| CN110598320B (en) * | 2019-09-11 | 2023-06-16 | 上海高性能集成电路设计中心 | Instruction set simulator calibration method based on hardware simulation accelerator |
| CN116720554A (en) * | 2023-08-11 | 2023-09-08 | 南京师范大学 | Method for realizing multi-section linear fitting neuron circuit based on FPGA technology |
| CN116720554B (en) * | 2023-08-11 | 2023-11-14 | 南京师范大学 | Method for realizing multi-section linear fitting neuron circuit based on FPGA technology |
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