CN109688606B - Data processing method and device, computer equipment and storage medium - Google Patents
Data processing method and device, computer equipment and storage medium Download PDFInfo
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- H04W28/02—Traffic management, e.g. flow control or congestion control
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- H04W28/065—Optimizing the usage of the radio link, e.g. header compression, information sizing, discarding information using assembly or disassembly of packets
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Abstract
The invention discloses a data processing method, a data processing device, computer equipment and a storage medium, aiming at the problem that the time overhead of the process of processing data between processors is large in the prior art. The method comprises the following steps: processing, by a first processor, an input first type data packet into at least one data block according to a first protocol stack function set, and generating at least one descriptor; the at least one data block is used for splicing into a second type data packet; copying a data block corresponding to each descriptor from a starting address in the descriptor according to the length in each descriptor in the at least one descriptor, and splicing the data block with the copied data block in the at least one data block to form the second-type data packet; processing, by the second processor, the second type of packet according to a second set of protocol stack functions.
Description
Technical Field
The present invention relates to the field of wireless communications, and in particular, to a data processing method and apparatus, a computer device, and a storage medium.
Background
In the wireless communication process, the base station end firstly converts the transmission block and then transmits the converted data packet, and the complexity of the whole processing process is high. The radio access network has a high throughput requirement, which means that a large number of data packets are transmitted, and the data packets are converted before transmission, so that a bottleneck occurs in the processing process as the number of data packets increases.
In the prior art, the industry adopts a method of multi-processor cooperation to complete the processing of the transport block, thereby overcoming the processing bottleneck. However, the multi-processor cooperation method only increases the number of data packets that can be processed by the base station, but still needs to convert the transmission block in one processor, perform the complex process, and then process the transmission block after the other processor waits for the completion of the conversion of the transmission block, which results in a large time overhead.
Therefore, the time overhead of the process of processing data between the processors in the prior art is a problem to be solved.
Disclosure of Invention
The embodiment of the application provides a data processing method and device, computer equipment and a storage medium, and solves the problem that in the prior art, the time overhead of a process of processing data between processors is large.
The embodiment of the invention provides a data processing method, which comprises the following steps:
processing, by a first processor, an input first type data packet into at least one data block according to a first protocol stack function set, and generating at least one descriptor; the at least one data block is used for splicing into a second type data packet; each descriptor in the at least one descriptor corresponds to one data block in the at least one data block, and the descriptor comprises a starting address and a length of the data block;
copying a data block corresponding to each descriptor from a starting address in the descriptor according to the length in each descriptor in the at least one descriptor, and splicing the data block with the copied data block in the at least one data block to form the second-type data packet;
processing, by the second processor, the second type of packet according to a second set of protocol stack functions.
Optionally, if the second processor copies the data block from the first processor in an address-aligned copy manner, the descriptor of the first data block further includes byte enable indication information of data corresponding to a head address and a tail address of the first data block, where the byte enable indication information is used to indicate invalid data in the first data block; the first data block is any one of the at least one data block;
and after copying the first data block, the second processor removes invalid data in the first data block according to the byte enabling indication information, and splices the data block from which the invalid data is removed from the first data block with the copied data block in the at least one data block to form the second-type data packet.
Optionally, the manner of copying the data block corresponding to the descriptor is a direct memory access DMA mode.
Optionally, the protocol layers in the first protocol stack function set and the second protocol stack function set include at least one of the following: the system comprises a physical PHY layer, a multiple access channel MAC layer, a no-link layer control RLC layer, a packet data convergence protocol PDCP layer, a service data adaptation protocol SDAP layer and a general packet radio service technology tunneling protocol user plane GTP-U layer.
Optionally, the at least one data block is spliced into the second type data packet according to the sequence of each descriptor in the at least one descriptor.
In the embodiment of the invention, the first processor processes the input first type data packet into a second type data packet comprising at least one data block according to the first protocol stack function set, and generates a descriptor comprising the starting address and the length of the data block for each data block. According to the length and the starting address in each descriptor, a second type data packet which can be directly processed by a second processor does not need to be formed in the first processor, the second type data packet is sequentially finished by the second processor in a mode of copying each data block and splicing the copied data block and the copied data block, and time overhead is reduced.
The embodiment of the invention provides computer equipment which comprises a memory, a first processor and a second processor, wherein a computer program is stored in the memory, and the first processor and the second processor realize a data processing method and an optional method provided by the embodiment of the invention when executing the computer program.
Embodiments of the present invention provide a computer-readable storage medium having stored thereon a computer program, which, when executed, performs a data processing method and an optional method as provided by embodiments of the present invention.
An embodiment of the present invention provides a data processing apparatus, including:
the first processing module is used for processing an input first type data packet into at least one data block according to a first protocol stack function set through a first processor and generating at least one descriptor; the at least one data block is used for splicing into a second type data packet; each descriptor in the at least one descriptor corresponds to one data block in the at least one data block, and the descriptor comprises a starting address and a length of the data block;
a data transmission module, configured to copy, by a second processor, a data block corresponding to each descriptor from a start address in the descriptor according to a length in the descriptor, and splice the data block with a copied data block in the at least one data block to form the second type data packet;
and the second processing module is used for processing the second type data packet according to a second protocol stack function set through the second processor.
Optionally, if the second processor copies the data block from the first processor in an address-aligned copy manner, the descriptor of the first data block further includes byte enable indication information of data corresponding to a head address and a tail address of the first data block, where the byte enable indication information is used to indicate invalid data in the first data block; the first data block is any one of the at least one data block;
the data transmission module is further configured to, after the second processor copies the first data block, remove invalid data from the first data block according to the byte enable indication information, and splice the data block from which the invalid data is removed from the first data block with a copied data block of the at least one data block, so as to form the second-type data packet.
Optionally, the data transmission module is configured to copy the data block corresponding to the descriptor in a direct memory access DMA mode.
Optionally, the protocol layers in the first protocol stack function set and the second protocol stack function set include at least one of the following: the system comprises a physical PHY layer, a multiple access channel MAC layer, a no-link layer control RLC layer, a packet data convergence protocol PDCP layer, a service data adaptation protocol SDAP layer and a general packet radio service technology tunneling protocol user plane GTP-U layer.
Optionally, the data transmission module is configured to splice the at least one data block into the second type data packet according to a sequence of each descriptor in the at least one descriptor.
Drawings
Fig. 1 is a diagram illustrating processing of a transport block according to an embodiment of the present invention;
fig. 2 is a flowchart illustrating steps corresponding to a data processing method according to an embodiment of the present invention;
fig. 3 is a schematic diagram of interaction between multiple processors according to a data processing method provided in the embodiment of the present invention;
fig. 4 is a schematic diagram illustrating that a first type data packet corresponding to a data processing method provided in an embodiment of the present invention is processed into at least one data block;
fig. 5 is a schematic diagram illustrating at least one data block corresponding to a data processing method provided in an embodiment of the present invention is spliced into a second type of data packet;
fig. 6 is a schematic diagram of removing redundant data according to a data processing method provided in an embodiment of the present invention;
fig. 7 is a schematic structural diagram of a data processing apparatus according to an embodiment of the present invention.
Detailed Description
In order to better understand the technical solutions, the technical solutions will be described in detail below with reference to the drawings and the specific embodiments of the specification, and it should be understood that the specific features in the embodiments and examples of the present application are detailed descriptions of the technical solutions of the present application, but not limitations of the technical solutions of the present application, and the technical features in the embodiments and examples of the present application may be combined with each other without conflict.
With the explosion of internet applications, the demand of people for traffic is increasing day by day, and wireless communication is the most popular way for traffic access, and has been continuously evolved and developed, including the evolution of wireless broadband and the evolution of mobile broadband, to support efficient traffic access. Regardless of the mobile broadband or the wireless broadband, the main function of the method is to convert the return bandwidth into the wireless access bandwidth so as to efficiently support the access of the mobile terminal, and further enable the terminal to develop various internet applications. In the wireless communication process, the base station end firstly converts the transmission block and then transmits the converted data packet, and the complexity of the whole processing process is high. The radio access network has a high throughput requirement, which means that a large number of data packets are transmitted, and the data packets are converted before transmission, so that a bottleneck occurs in the processing process as the number of data packets increases.
Fig. 1 is a schematic diagram of processing a transport block in the prior art according to an embodiment of the present invention.
The Data format used by the return side of the base station is an Internet Protocol (IP) Data packet, and the Data format used by the air interface side is a Multiple Access Channel (MAC) Data packet and a Protocol Data Unit (PDU) Data packet. Therefore, at the base station, Packet conversion is required, a Data Packet belonging to the same User Equipment (UE) is extracted during the conversion, and first, at the S1 layer, header information GTP Hrd is removed for the received GTP PDUs through a General Packet Radio Service tunneling Protocol (GTP), and the Data Packet is converted into a Packet Data Convergence Protocol (PDCP) Service Data Unit (Service Data Unit, SDU). Then, forming PDCP PDU as SDU of Radio Link Control protocol (RLC) layer to the header information PDCP Hrd of IP data packet adding layer; then, according to the size of the empty port scheduling resource, cutting the PDCP data packets, and then selecting a plurality of PDCP data packets, wherein the PDCP data packets are cut, and header information RLC Hrd added after splicing together is used to form an RLC PDU, which is used as SDU of a Multiple Access Channel (MAC) layer, and then adding MAC layer header information MAC Hrd and Padding content Padding to the RLC data packets to form an MAC PDU, which is used as a transmission block to be transmitted to a Physical layer (PHY), thereby completing format conversion between the IP packet and the empty port packet, so as to perform signal transceiving on a wireless side, and the complexity of the whole processing process is very high. The high throughput requirement of the radio access network means that a large number of data packets are transmitted, which inevitably results in an increased packet conversion processing load and directly challenges the processing capability of the base station.
In the prior art, the industry adopts a method of multi-processor cooperation to complete the processing of the transport block, thereby overcoming the processing bottleneck. However, the multi-processor cooperation method only increases the number of data packets that can be processed by the base station, but still needs to convert the transmission block in one processor, perform the complex process, and then process the transmission block after the other processor waits for the completion of the conversion of the transmission block, which results in a large time overhead.
Therefore, the time overhead of the process of processing data between the processors in the prior art is a problem to be solved.
Fig. 2 is a flowchart illustrating steps corresponding to a data processing method according to an embodiment of the present invention.
Step 201: processing, by a first processor, an incoming first type of packet into a second type of packet according to a first set of protocol stack functions, and generating at least one descriptor.
Step 202: and copying a data block corresponding to the descriptor from a starting address in the descriptor according to the length in each descriptor in the at least one descriptor through a second processor, and splicing the data block with the copied data block in the at least one data block to form the second-type data packet.
Step 203: processing, by the second processor, the second type of data according to a second set of protocol stack functions.
In steps 201 to 203, the protocol layers corresponding to the first protocol stack function set and the second protocol stack function set include at least one of the following: the physical PHY layer, the MAC layer, the RLC layer and the PDCP layer, the SDAP layer, the GPRS tunneling Protocol User Plane (GTP-U) layer. It should be noted that the corresponding protocol layers in the first protocol stack function set and the second protocol stack function set are only exemplified by the protocol layers, and are not limited to the protocol layers. The following describes steps 201 to 203 in detail with reference to fig. 3, and fig. 3 is a schematic diagram of multiprocessor interaction corresponding to a data processing method according to an embodiment of the present invention.
In step 201, the first type data packet input to the first processor 301 is an initial transport block unprocessed by the base station, and includes one or more data blocks. Both the first type of packet and the second type of packet are stored in the first memory 3011 of the first processor, and the first type of packet needs to be retrieved from the first memory 3011. Specifically, the first protocol stack function set processing module 3012 processes the first type data packet into a second type data packet according to the first protocol stack function set. The second type of data packet comprises at least one data block; each descriptor in the at least one descriptor corresponds to a data block in the at least one data block, the descriptor includes a start address and a length of the data block, and the at least one descriptor is distributed in a descriptor list and is specifically executed by the descriptor configuration module 3013. In an alternative embodiment, the order of arrangement between the descriptors in the descriptor list is determined according to the starting address of each descriptor in the at least one descriptor. The specific way of processing the input first type data packet into the second type data packet is as follows: (1) if the data block of the first type data packet needs to remove the information such as the header, only generating and recording the initial address and the length of the data block; (2) if the data block of the first type data packet needs to add the header information and the like corresponding to each protocol layer in the first protocol stack function set, the data block corresponding to the protocol layer is directly added to the tail part of the processed first type data packet, and the initial address and the length of the data block are recorded.
It should be noted that although at least one data block includes a data block corresponding to each protocol layer, the at least one data block cannot be directly processed by the second processor 302, and the sequence of each data block is not adjusted, so that during the transmission to the second memory 3021 of the second processor 302, each data block of the at least one data block that is to form the second type data packet needs to be spliced.
In step 202, since each descriptor in the at least one descriptor includes the start address and the length of the corresponding data block, the second processor 302 copies and concatenates the data blocks according to each descriptor. An optional way to copy the data block corresponding to the descriptor is a Direct Memory Access (DMA) mode.
Specifically, the second processor 302 first obtains the descriptor list through the descriptor receiving module 3023, and copies and splices the data blocks in sequence by the data copy control module 3022 according to the sequence of the data blocks in the second type of data packet that can be directly processed by the second processor 302. In step 201, as already described, the order of arrangement between the descriptors in the descriptor list is determined according to the starting address of each descriptor in the at least one descriptor. The second processor 302 splices at least one data block into a second type of data packet directly according to the ordering. Specifically, the second processor 302 copies from the start address of one descriptor until the length of the copy data reaches the data length recorded in the descriptor, and directly adds this copied data block to the copied data blocks in the arrangement order.
If the first data block stores data in a data alignment manner, an optional implementation manner of this step is that the descriptor of the first data block further includes byte enable indication information of data corresponding to the head address and the tail address of the first data block, where the byte enable indication information is used to indicate invalid data in the first data block; the first data block is any one of at least one data block; and after copying the first data block, the second processor removes invalid data in the first data block according to the byte enabling indication information, and splices the data block from which the invalid data is removed from the first data block with the copied data block in at least one data block to form a second type data packet.
In step 203, the second processor 302 forms a second type data packet capable of being directly processed after completing the splicing of at least one data block. The second protocol stack function set processing module 3024 processes the second type data packet according to each protocol layer function related in the second protocol stack function set.
With respect to the data processing method and optional implementation manner in step 201 to step 203, an embodiment of the present invention provides a computer device, including a memory, a first processor, and a second processor, where the memory stores a computer program, and the first processor and the second processor are configured to implement step 201 to step 203 by executing the computer program.
For a data processing method and optional implementation manner in step 201 to step 203, an embodiment of the present invention provides a computer-readable storage medium, on which a computer program is stored, and the computer program implements step 201 to step 203 when executed.
A specific embodiment of a data processing method is described below with specific examples:
as shown in fig. 4, a schematic diagram of processing a first type data packet corresponding to a data processing method provided in the embodiment of the present invention into at least one data block is shown.
The first processor allocates a storage space with the storage size of 64MB to be used as a receiving cache of the IP data packet, and the base address of the storage space is BaseAddrForIPdata; and allocating a storage space with the storage size of 8MB to be used as a cache of the header information, and recording the base address as BaseAddrForHrd. And buffering the received three IP data packets in a storage space pointed by BaseAddrForIPdata at a transmission time interval corresponding to the T0 moment. At least one data block is a transmission block of GTP1 Hdr to idle subchunks.
In the transmission time interval, the resource size scheduled by the resource scheduler to user 1 can just load 2.5 IP packets, so the first processor removes GTP1 Hdr, GTP2 Hdr, GTP3 Hdr and idle sub-blocks according to the packet conversion processing steps, adds PDCP Hrd to the three IP packet loads, then adds RLC Hrd, and finally adds MAC Hrd and Padding, thereby determining the current transmission time interval, where the second type of packet is composed of 9 data blocks, that is, one MAC Hrd, one RLC Hrd, three PDCP Hrd, three IP loads, and one Padding. Therefore, the processor 1 needs to form a descriptor list including 9 descriptors, each descriptor corresponding to the start address and the data length of one of the 9 data blocks, and considering the forming process of the whole transport block, there is an order arrangement between different sub-blocks, therefore, the arrangement of the descriptors in the descriptor list needs to be consistent with the arrangement order of each data block in the transport block, and finally, a descriptor list is formed, each descriptor including the start address and the length of the corresponding data block, i.e., { startAi, Leni }, i ═ 0,1, …,8 in fig. 4, and is sent to the second processor.
As shown in fig. 5, a schematic diagram that at least one data block corresponding to a data processing method provided in the embodiment of the present invention is spliced into a second type data packet.
After receiving the descriptor list, the second processor takes out each descriptor one by one, copies the data from the first memory of the first processor to the second memory of the second processor according to the starting address and the data length pointed by the descriptor, and completes data splicing of a transmission block, wherein the storage form after splicing is a complete transmission block as shown in fig. 5, namely a second type data packet.
After the second processor finishes copying the second type data packet, the second processor triggers the operation of the second protocol layer function set, and finally finishes the processing of one transmission block. It should be noted that, if the first processor performs the data copying process from the second processor, the data can only be copied according to a certain bit width alignment (for example, 32-bit alignment), and the data block data is stored according to another bit width alignment (for example, 8-bit alignment), the descriptor-based data block data copying process may cause some redundant byte data to appear at the head and the tail of each data block due to the copying according to the 32-bit alignment, that is, blank cells in fig. 6, and finally cause that the data of different data blocks cannot be stored strictly continuously after being copied.
Therefore, an operation of removing invalid data included between data blocks needs to be added in the data copy control module, so as to ensure that after the data is copied, the invalid data is strictly and continuously stored between the data blocks in the second storage. Specifically, the second type of data packet and the respective data blocks are stored from right to left in fig. 6. For example, the first valid byte of data block 0 is D0B0, so data block 0 is stored to the second type of packet directly starting from D0B0, and similarly, the remaining redundant data in data block 0 is also skipped. When the transmission of one data block is finished, the next data block still provides redundant data according to the mode, and finally a second type data packet which is strictly and continuously stored is obtained.
In the prior art, a first processor needs to splice IP data sub-blocks and header information data sub-blocks dispersed in a memory of the first processor into a complete second-type data packet shown in fig. 5, and then sends the complete transmission block to a second processor. By adopting the scheme of the invention, the processing process of the first processor to the transmission block only needs to calculate the number of packets forming one transmission block and the corresponding packet header information, and the splicing of the sub-block data is finished in a sequential manner in the copying process without introducing overhead, so that the first processor does not need to copy and splice the sub-blocks with huge number and dispersed storage addresses, the time overhead of the first processor is effectively reduced, and the processing capacity of the whole system is improved. The invention greatly improves the processing throughput of the whole system by utilizing the high-complexity operation of splicing the sub-block data into a complete transmission block in the data transmission process among the processors as the protocol stack processing sharing data packet format conversion process.
In the embodiment of the invention, the first processor processes the input first type data packet into a second type data packet comprising at least one data block according to the first protocol stack function set, and generates a descriptor comprising the starting address and the length of the data block for each data block. According to the length and the starting address in each descriptor, a second type data packet which can be directly processed by a second processor does not need to be formed in the first processor, the second type data packet is sequentially finished by the second processor in a mode of copying each data block and splicing the copied data block and the copied data block, and time overhead is reduced.
Fig. 7 is a schematic structural diagram of a data processing apparatus according to an embodiment of the present invention.
An embodiment of the present invention provides a data processing apparatus, including:
a first processing module 701, configured to process, by a first processor, an input first type data packet into at least one data block according to a first protocol stack function set, and generate at least one descriptor; the at least one data block is used for splicing into a second type data packet; each descriptor in the at least one descriptor corresponds to one data block in the at least one data block, and the descriptor comprises a starting address and a length of the data block;
a data transmission module 702, configured to copy, by the second processor, a data block corresponding to each descriptor from a start address in the descriptor according to a length in the descriptor, and splice the data block with a copied data block in the at least one data block to form the second type data packet;
the second processing module 703 is configured to process, by the second processor, the second type data packet according to a second protocol stack function set.
Optionally, if the second processor copies the data block from the first processor in an address-aligned copy manner, the descriptor of the first data block further includes byte enable indication information of data corresponding to a head address and a tail address of the first data block, where the byte enable indication information is used to indicate invalid data in the first data block; the first data block is any one of the at least one data block;
the data transmission module 702 is further configured to, after the second processor copies the first data block, remove invalid data from the first data block according to the byte enable indication information, and splice the data block from which the invalid data is removed from the first data block with a copied data block of the at least one data block, so as to form the second type data packet.
Optionally, the data transmission module 702 is configured to copy the data block corresponding to the descriptor in a direct memory access DMA mode.
Optionally, the protocol layers in the first protocol stack function set and the second protocol stack function set include at least one of the following: the system comprises a physical PHY layer, a multiple access channel MAC layer, a no-link layer control RLC layer, a packet data convergence protocol PDCP layer, a service data adaptation protocol SDAP layer and a general packet radio service technology tunneling protocol user plane GTP-U layer.
Optionally, the data transmission module 702 is configured to splice the at least one data block into the second type data packet according to a sequence of each descriptor in the at least one descriptor.
As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (8)
1. A data processing method, comprising:
processing, by a first processor, an input first type data packet into at least one data block according to a first protocol stack function set, and generating at least one descriptor; the at least one data block is used for splicing into a second type data packet; each descriptor in the at least one descriptor corresponds to one data block in the at least one data block, the descriptor includes byte enabling indication information of data corresponding to a start address and a length of the data block and a head address and a tail address of the data block, and the byte enabling indication information is used for indicating invalid data in the data block;
copying a data block corresponding to each descriptor from a start address in the descriptor by adopting an address alignment copying mode according to the length of each descriptor in the at least one descriptor through a second processor, removing invalid data in a first data block according to the byte enabling indication information, and splicing the data block from which the invalid data are removed in the first data block with a copied data block in the at least one data block to form the second-type data packet, wherein the first data block is any one of the at least one data block;
processing, by the second processor, the second type of packet according to a second set of protocol stack functions.
2. The method of claim 1, wherein the data block corresponding to the descriptor is copied in a Direct Memory Access (DMA) mode.
3. The method of any of claims 1-2, comprising:
the corresponding protocol layers in the first set of protocol stack functions and the second set of protocol stack functions include at least one of: the system comprises a physical PHY layer, a multiple access channel MAC layer, a no-link layer control RLC layer, a packet data convergence protocol PDCP layer, a service data adaptation protocol SDAP layer and a general packet radio service technology tunneling protocol user plane GTP-U layer.
4. The method of any of claims 1-2, further comprising:
and splicing the at least one data block into the second type data packet according to the sequence of each descriptor in the at least one descriptor.
5. A data processing apparatus, comprising:
the first processing module is used for processing an input first type data packet into at least one data block according to a first protocol stack function set through a first processor and generating at least one descriptor; the at least one data block is used for splicing into a second type data packet; each descriptor in the at least one descriptor corresponds to one data block in the at least one data block, the descriptor includes byte enabling indication information of data corresponding to a start address and a length of the data block and a head address and a tail address of the data block, and the byte enabling indication information is used for indicating invalid data in the data block;
a data transmission module, configured to copy, by a second processor, a data block corresponding to each descriptor from a start address in the descriptor in an address-aligned copy manner according to a length in each descriptor in the at least one descriptor, remove invalid data from a first data block according to the byte enable indication information, and splice the data block from which the invalid data is removed with a copied data block in the at least one data block to form the second-type data packet, where the first data block is any data block in the at least one data block;
and the second processing module is used for processing the second type data packet according to a second protocol stack function set through the second processor.
6. The apparatus of claim 5,
and the data transmission module is used for copying the data block corresponding to the descriptor in a Direct Memory Access (DMA) mode.
7. A computer device comprising a memory, a first processor and a second processor, the memory storing a computer program, wherein the first processor and the second processor when executing the computer program implement the steps of the method of any one of claims 1 to 4.
8. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the method of any one of claims 1 to 4.
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| CN110474924B (en) * | 2019-09-17 | 2021-11-02 | 京信网络系统股份有限公司 | Data transmission method and device, computer equipment and storage medium |
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