CN109687972B - Circuit supporting multiple Hash algorithms - Google Patents
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/32—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials
- H04L9/3236—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials using cryptographic hash functions
- H04L9/3239—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials using cryptographic hash functions involving non-keyed hash functions, e.g. modification detection codes [MDCs], MD5, SHA or RIPEMD
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
- H04L9/0643—Hash functions, e.g. MD5, SHA, HMAC or f9 MAC
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
- H04L2209/12—Details relating to cryptographic hardware or logic circuitry
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Abstract
The invention provides a circuit supporting multiple Hash algorithms, which comprises initialization logic, constant selection logic, message processing logic, iteration logic, a MUX and a Hash value register array. The Hash algorithm supported by the design comprises the following steps: MD5, SHA0, SHA1, SHA224, SHA256, SHA384, SHA512, SM 3. The method supports continuous processing of a message, and only needs to load an iteration initial value defined by a corresponding Hash algorithm into a Hash value register array before the first block of the message starts iteration, and then continuously process the message. In addition, the design also supports the segmented processing of one message, the processing of another message can be inserted between two segments of one message, and in the mode, the iteration result of the previous segment of the message is loaded to the Hash value register array through the initialization logic before the iteration starts.
Description
Technical Field
The invention belongs to the technical field of information security and password, and particularly relates to a circuit implementation and design method supporting multiple Hash algorithms.
Background
The Hash algorithm, also called Hash algorithm, is a method for generating small numbers by operating on any file. Like fingerprints, the Hash algorithm is a mark for ensuring the uniqueness of a file by using shorter information. A good Hash algorithm has the following characteristics:
1) the forward direction is fast. Given a plaintext and a Hash algorithm, a Hash value can be calculated within a finite time and a finite resource.
2) The reverse direction is difficult. Given the Hash value, it is difficult to extrapolate the plaintext backwards within a limited time.
3) The input is sensitive. Slight changes in the original input information will produce very different Hash values.
4) Collision avoidance. It is difficult to find two pieces of plaintext that differ in content so that their Hash values are identical (collision occurs). That is, for any two different data blocks, the probability that the Hash values are the same is extremely low; for a given block, it is extremely difficult to find the same block as its Hash value.
The Hash algorithm mainly has the following application scenarios:
1) digital signature: the Hash value (abstract) of the message is generated through a Hash algorithm, and then the Hash value is operated through a public key algorithm to generate a digital signature of the message. The reason that the digital signature of the message is generated by performing public key operation on the Hash value instead of directly performing public key operation on the message is that the efficiency of a public key algorithm is low, the data volume of the Hash value is generally much smaller than that of the message, and the efficiency of the signature can be greatly improved by performing public key operation on the Hash value of the message.
2) Digital fingerprint: the Hash algorithm can change the input with any length into the output with determined length, and different inputs correspond to different outputs, so that the digital fingerprint (Hash value) of the program or the document can be obtained based on the Hash algorithm, and the modification of the program or the document by the virus or the intruder can be found by comparing the digital fingerprint with the original digital fingerprint stored in a safe place.
3) And storing the password. The Hash value of the password is generated based on the Hash algorithm, and then the Hash value of the password is stored in the system instead of the password, so that the safety of the system can be improved. Even if a hacker steals the Hash value stored in the system, the hacker still cannot acquire the password, and cannot log in to the system.
In the prior art, the hardware implementation scheme of the Hash algorithm can only realize one Hash algorithm, and multiple Hash algorithms need to be realized by multiple hardware schemes, so that the universality is poor and the cost is high.
Disclosure of Invention
In view of this, the present invention aims to provide a circuit supporting multiple Hash algorithms, so as to provide an efficient, general and low-cost hardware implementation scheme for Hash algorithms.
In order to achieve the purpose, the technical scheme of the invention is realized as follows:
a circuit supporting multiple Hash algorithms, comprising: initialization logic, constant selection logic, message processing logic, iteration logic, MUX, and Hash value register array,
initialization logic for initializing the Hash value register array before iteration begins;
constant selection logic, which selects the constant value to be sent to the iterative logic for operation according to the specific Hash algorithm type and the iterative round number;
the message processing logic is used for calculating a message value required by each iteration according to the input original message;
the iterative logic is used for carrying out iterative calculation on the input message according to the constant selection logic, the message processing logic and the input value provided by the Hash value register array, and the result of each iterative calculation is stored in the Hash value register array;
the MUX is used for switching the on-off of the Hash value register array and the initialization logic or the iteration logic;
and the Hash value register array is used for storing the result of each iteration.
Furthermore, continuous processing of a message is supported, and segmented processing of a message is also supported;
the initialization logic includes two cases: in the first case, for the first block of a message, loading an iteration initial value defined by a corresponding Hash algorithm to a Hash value register array before iteration starts; the second case is for the segmentation process, for a non-first block of a message, loading the Hash value register array with the iteration result of the previous segment of the same message before the iteration starts.
Further, the constant selection logic specifically selects the constant value through a plurality of multiplexers MUX, and the control signal during selection includes a message input enable signal, an algorithm type indication signal, and an iteration round number.
Further, the message processing logic includes a message register array to register messages and perform iterative processing and updating.
Further, the multiple Hash algorithms include MD5, SHA0, SHA1, SHA224, SHA256, SHA384, SHA512, SM 3.
Further, the message processing logic starts iterative computations when a first original message value is input for the non-SM 3 algorithm and when a fourth original message value is input for the SM3 algorithm.
Further, the iteration logic is realized by a plurality of adders, the input ends of the adders are arranged according to the types of the algorithms, and the input end which is not used by the adders is connected with 0.
Further, the MUX is a control switch for selecting 1 from 2, and the initialization logic and the Hash value register array are switched on when the first block of the message is input and the first block of the non-first subsection of the message is input; and after the initialization is finished, switching to iterative logic to be connected with the Hash value register array.
Further, after the last iteration is finished, the value in the Hash value register array is subjected to an exclusive or operation on the algorithm SM3 to obtain a final Hash value; and performing an addition operation on the non-SM 3 algorithm to obtain a final Hash value.
Compared with the prior art, the circuit has the following advantages:
(1) the circuit implementation scheme supports the current mainstream Hash algorithm, including MD5, SHA0, SHA1, SHA224, SHA256, SHA384, SHA512 and SM3, and shares hardware resources to the maximum extent while supporting the Hash algorithm, thereby achieving the purposes of universality and low cost.
(2) The invention carries out a round of iterative computation and reasonably designs the circuit through each clock cycle to reach the highest clock frequency, thereby realizing high efficiency.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate an embodiment of the invention and, together with the description, serve to explain the invention and not to limit the invention. In the drawings:
FIG. 1 is a block diagram of the overall circuit configuration of an embodiment of the present invention;
FIG. 2 is a schematic diagram of a continuous processing data flow according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a data flow for a segmented processing according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a non-SM 3 algorithm input message delivery sequence according to an embodiment of the present invention;
fig. 5 is a schematic diagram of the input message passing sequence of the SM3 algorithm according to the embodiment of the present invention.
Detailed Description
It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict.
The present invention will be described in detail below with reference to the embodiments with reference to the attached drawings.
In this embodiment, a circuit supporting multiple Hash algorithms includes MD5, SHA0, SHA1, SHA224, SHA256, SHA384, SHA512, and SM 3; the circuit supports continuous processing of a message and also supports segmented processing of the message, namely, another message can be inserted between two segments of the message for processing;
as shown in fig. 1, the circuit includes: initialization logic, constant selection logic, message processing logic, iteration logic, MUX, and Hash value register array,
the initialization logic is used for completing initialization of the Hash value register array, namely, an initial value is given to the Hash value register array before iteration starts; the specific implementation includes two cases: in the first case, for the first block of a message (message 1.block1 in the case of continuous processing or message 1.block1 in the case of segmented processing), the iteration initial value defined by the corresponding Hash algorithm is loaded into the Hash value register array before the iteration starts; in the second case, for a non-first block of a message (message 1. segment 2.block1, message 1. segment 3.block1, message 1. segment 4.block1, … … in the case of segmentation), the iteration result (Hash median) of the previous segment of the same message, input through the interface, is loaded into the Hash value register array before the iteration starts; the initialization logic inputs the Hash initial value from the outside so as to support the segmented processing function of the message;
the constant selection logic selects constant values which need to be sent to the iterative logic for operation according to the specific Hash algorithm type and the iterative round number, and particularly selects the constant values through a plurality of Multiplexers (MUX);
the message processing logic comprises 16 registers with 64 bits, namely a message register array (w 0-w 15), and is used for calculating a message value required by each iteration according to input original messages, registering the input messages into the message register array, registering and shifting the input messages, and performing iterative calculation after one block is completely input so as to continuously update the message register array;
the iterative logic is used for performing iterative processing on the input message according to the constant selection logic, the message processing logic and the input value provided by the Hash value register array, namely performing iterative calculation, and storing the result of each iterative calculation in the Hash value register array; the method is realized by a plurality of adders, and comprises 1 4-input adder with 64-bit width, 1 6-input adder with 64-bit width and a 7-input adder with 64-bit width; the three adders are provided by integrating the requirements of various Hash algorithms, the Hash algorithm with the largest demand of the adders is supported, the inputs of the adders are different when different Hash algorithm operations are carried out, and the unused input end of the adder is connected with 0 for the Hash algorithm with small demand of the adder;
the MUX is a control switch with 1 selected from 2, when the first block of the message is input and the first block of the non-first segment of the message is input, the initialization logic and the Hash value register array are switched on, the initialization of the Hash value register array is completed after one clock cycle, and the message data is simultaneously registered in w 0-w 15 of the message register array; and after initialization is finished, switching to iterative logic to be connected with the Hash value register array, starting iterative calculation, and then updating the Hash value register array after each iteration by the iterative logic.
And the Hash value register array is used for storing the result of each iteration. The specification of the Hash value register array meets the Hash algorithm with the largest demand quantity, and for other Hash algorithms, only the low order and the high order of each register of the Hash value register array are used.
The initialization logic, as shown in fig. 2, supports continuous processing of a message, and loads an iteration initial value defined by a corresponding Hash algorithm into the Hash value register array before the first block of the message starts iteration; as shown in fig. 3, while supporting the fragment processing of one message, another message may be inserted between two segments of one message for processing; loading the iteration result (Hash intermediate value) of the previous segment into a Hash value register array before the iteration starts;
for example, a segment of message 2 may be processed after one segment of message 1 is processed, and then the next segments of message 1 may be processed; for the next segment of message 1, the iteration result of the previous segment of message only needs to be loaded into the Hash value register array by the initialization logic before the iteration starts.
In specific implementation, the control signal when the constant selection logic selects includes a message input enable signal, an algorithm type indication signal, and an iteration round number, and the selected constant values include the following:
the MD5 algorithm: t [ i ], s;
SHA0, SHA1 algorithm: kt；
SHA224, SHA256 algorithm: kt；
SHA384, SHA512 algorithm: kt；
The SM3 algorithm: t isj。
The above constant values are constants of corresponding standard algorithms, and the meaning thereof is described in detail in a public document and is not described herein again.
In a specific implementation process, the message processing logic counts the length of the message in the input process of the message, and fills (padding) the message at the end of the message, wherein different Hash algorithms have different specific filling modes, and the message processing logic performs corresponding filling according to the selected Hash algorithm. For a segmented message, the statistics of the message length will continue on the basis of the previous segment of the message, which is input into the message processing logic along with the incoming message.
The message processing logic comprises 16 registers with 64 bits, namely a message register array (w 0-w 15), and for non-SM 3 algorithm, the input is connected with the outputStarting with the iterative computation at the first original message value, the order of delivery of the input messages (i.e., the shift pattern for the MD5, SHA0, SHA1, SHA224, SHA256, SHA384, SHA512 algorithms) is shown in FIG. 4, where W15 is taken as W15jParticipating in the operation of iterative logic;
for the SM3 algorithm, iterative computation starts when the fourth original message value is input, and the order of delivery of the input messages (i.e., the shift pattern for the SM3 algorithm) is shown in fig. 5, where W15 is taken as Wj, and participates in the operation of the iterative logic together with W' j.
In particular, for the MD5 algorithm, after all messages are input into the message register array (i.e. after 16 rounds of calculation), values w 0-w 14 are replaced with values w15 alternately, so that the message values required by the current round of iteration are always maintained in w15, thereby shortening the length of the iterative logic critical path; the sequence of substitutions is as follows:
w0 wheels 19,34,56
w1 wheels 16,22,39,49
w2 wheels 29,40,54
w3 wheels 26,35,61
w4 wheels 23,46,52
w5 wheels 20,41,59
w6 wheels 17,36,50
w7 wheels 30,47,57
w8 wheels 27,42,48,62
w9 wheels 24,37,55
w10 wheels 21,32,45,62
w11 wheels 18,43,53
w12 wheels 31,38,60
w13 wheels 28,33,51
w14 wheels 25,44,58
In a specific implementation process, the algorithm implemented by the iterative logic through the 4-input adder is SHA224, SHA256, SHA384, SHA512, and SM3, where:
the SHA224, SHA256 algorithm is calculated by a 4-input adder:
SHA384, SHA512 are calculated by a 4-input adder:
the SM3 algorithm calculates by a 4-input adder:
SS1＝((A<<<12)+E+(Tj<<<j))<<<7；
the algorithms implemented by the 6-input adder are MD5, SHA224, SHA256, SHA384, SHA512, SM3, where:
the MD5 algorithm calculates by a 6-input adder:
b+((a+F(b,c,d)+X[k]+T[i])<<<s)；
b+((a+G(b,c,d)+X[k]+T[i])<<<s)；
b+((a+H(b,c,d)+X[k]+T[i])<<<s)；
b+((a+I(b,c,d)+X[k]+T[i])<<<s)
the SHA224, SHA256, SHA384 and SHA512 algorithms use the adder to calculate
The SM3 algorithm calculates by a 6-input adder:
TT2＝GGj(E,F,G)+H+SS1+Wj
the algorithms implemented using 7-input adders are MD5, SHA0, SHA1, SHA224, SHA256, SHA384, SHA512, SM3, where:
the MD5 algorithm calculates by a 7-input adder:
a+F(b,c,d)+X[k]+T[i]；
a+G(b,c,d)+X[k]+T[i]；
a+H(b,c,d)+X[k]+T[i]；
a+I(b,c,d)+X[k]+T[i]
the SHA0, SHA1 algorithm calculates by 7-input adder:
T＝ROTL5(a)+ft(b,c,d)+e+Kt+Wt
SHA224 and SHA256 algorithm uses the adder to calculate
SHA384, SHA512 algorithm uses this adder to calculate
The SM3 algorithm calculates by a 7-input adder:
TT2＝FFj(A,B,C)+D+SS2+W'j。
the meaning of the above calculation formula and each symbol refers to a standard algorithm, and there are public documents corresponding to the standard algorithm for detailed description, which are not repeated herein.
In specific implementation, after the initialization is completed, the MUX is switched to the iterative logic and Hash value register array for connection in the next clock cycle (for non-SM 3 algorithm) or when the fourth data is input (for SM3 algorithm), and the iterative computation is started.
In specific implementation, the update time of the Hash value register array is divided into the following three stages:
stage 1: and (5) initializing.
And (2) stage: and (5) an iterative process.
And (3) stage: and (5) after the iteration is finished.
After the last iteration is finished, the values (a to H) in the Hash value register array are subjected to an exclusive or operation (for the algorithm SM3) or an addition operation (for the non-SM 3 algorithm) to obtain the final Hash value, and the operations are as follows:
for the SM3 algorithm:
A＝A^A_ini；B＝B^B_ini；C＝C^C_ini；D＝D^D_ini；E＝E^E_ini；F＝F^F_ini；G＝G^G _ini；H＝H^H_ini；
for the non-SM 3 algorithm:
A＝A+A_ini；B＝B+B_ini；C＝C+C_ini；D＝D+D_ini；E＝E+E_ini；F＝F+F_ini；G ＝G+G_ini；H＝H+H_ini。
the invention provides a circuit supporting multiple Hash algorithms, a working principle of the circuit and a design idea of the circuit. The method supports continuous processing of a message, and only needs to load an iteration initial value defined by a corresponding Hash algorithm into a Hash value register array before the first block of the message starts iteration, and then continuously process the message. In addition, the design also supports the segmented processing of one message, the processing of another message can be inserted between two segments of one message, and in the mode, the iteration result of the previous segment of the message is loaded to the Hash value register array through the initialization logic before the iteration starts.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (7)
1. A circuit for supporting multiple Hash algorithms, comprising: initialization logic, constant selection logic, message processing logic, iteration logic, MUX, and Hash value register array,
initialization logic for initializing the Hash value register array before iteration begins;
constant selection logic, which selects the constant value to be sent to the iterative logic for operation according to the specific Hash algorithm type and the iterative round number;
the message processing logic is used for calculating a message value required by each iteration according to the input original message;
the iterative logic is used for carrying out iterative calculation on the input message according to the constant selection logic, the message processing logic and the input value provided by the Hash value register array, and the result of each iterative calculation is stored in the Hash value register array;
the MUX is used for switching the on-off of the Hash value register array and the initialization logic or the iteration logic;
the Hash value register array is used for storing the result of each iteration;
the circuit supports continuous processing of a message and also supports segmented processing of a message;
the initialization logic includes two cases: in the first case, for the first block of a message, loading an iteration initial value defined by a corresponding Hash algorithm to a Hash value register array before iteration starts; the second case is for the segmentation process, for a non-first block of a message, loading the Hash value register array with the iteration result of the previous segment of the same message before the iteration starts.
2. The circuit supporting multiple Hash algorithms according to claim 1, wherein: the constant selection logic specifically selects a constant value through a plurality of Multiplexers (MUXs), and control signals during selection comprise a message input enabling signal, an algorithm type indicating signal and iteration rounds.
3. The circuit supporting multiple Hash algorithms according to claim 1, wherein: the message processing logic includes a message register array to register messages and perform iterative processing and updating.
4. The circuit supporting multiple Hash algorithms according to claim 1, wherein: the multiple Hash algorithms include MD5, SHA0, SHA1, SHA224, SHA256, SHA384, SHA512, SM 3.
5. The circuit supporting multiple Hash algorithms according to claim 4, wherein: the message processing logic begins iterative computations when the first original message value is entered for the non-SM 3 algorithm and when the fourth original message value is entered for the SM3 algorithm.
6. The circuit supporting multiple Hash algorithms according to claim 1, wherein: the iteration logic is realized by a plurality of adders, the input ends of the adders are arranged according to the types of algorithms, and the unused input end of the adder is connected with 0.
7. The circuit supporting multiple Hash algorithms according to claim 1, wherein: the MUX is a control switch with 1 selected from 2, and the initialization logic and the Hash value register array are switched on when the first block of the message is input and the first block of the non-first subsection of the message is input; and after the initialization is finished, switching to iterative logic to be connected with the Hash value register array.
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