CN109687972A - A kind of circuit for supporting a variety of hash algorithms - Google Patents
A kind of circuit for supporting a variety of hash algorithms Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/32—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials
- H04L9/3236—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials using cryptographic hash functions
- H04L9/3239—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials using cryptographic hash functions involving non-keyed hash functions, e.g. modification detection codes [MDCs], MD5, SHA or RIPEMD
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
- H04L9/0643—Hash functions, e.g. MD5, SHA, HMAC or f9 MAC
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
- H04L2209/12—Details relating to cryptographic hardware or logic circuitry
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Abstract
The present invention provides a kind of circuits for supporting a variety of hash algorithms, include initialization logic, constant selection logic, message processing logic, iterative logical, a MUX and hash value register array.The hash algorithm that the design supports includes: MD5, SHA0, SHA1, SHA224, SHA256, SHA384, SHA512, SM3.Support the continuous processing to a message, it is only necessary to the iteration initial value that corresponding hash algorithm defines is loaded into hash value register array before first block of message starts iteration, then continuously handle this message.In addition, the design also supports the segment processing to a message, the processing of another message can be inserted between two sections of a message, the iteration result before iteration starts by the previous segmentation of this message is only needed to be loaded into hash value register array by initialization logic in this mode.
Description
Technical field
The invention belongs to information security and art of cryptography, more particularly, to the circuit realization for supporting a variety of hash algorithms
And design method.
Background technique
Hash algorithm, also known as hash algorithm, hashing algorithm are a kind of to do operation to any file to generate small number
Method.As fingerprint, hash algorithm is exactly a kind of mark for guaranteeing file uniqueness with shorter information.One good
Hash algorithm has following characteristics:
1) positive quick.Given plaintext and hash algorithm, can calculate hash value in finite time and limited resources.
2) reverse difficult.Given hash value is difficult backstepping in finite time and goes out in plain text.
3) input is sensitive.The minor modifications of original input information can all make the hash value generated generate a great difference.
4) conflict avoidance.It is difficult to find two sections of different plaintexts of content, so that their hash value unanimously (rushes
It is prominent).A possibility that data block i.e. different for any two, hash value is identical, is minimum；The data block given for one,
It is extremely difficult to find data block identical with its hash value.
Hash algorithm mainly has following application scenarios:
1) digital signature: generating the hash value (abstract) of message by hash algorithm first, then passes through public key algorithm pair
Hash value does the digital signature that operation generates message.Why to hash value do public key calculation generate message digital signature without
It is that directly to do public key calculation to message be because the efficiency of public key algorithm is relatively low, and hash value data volume is generally than message itself
Much smaller, the efficiency of signature can greatly be improved by doing public key calculation by the Hash value to message.
2) digital finger-print: hash algorithm can become the input of random length determining the output of length, different defeated
Enter to correspond to different output, therefore the digital finger-print (hash value) of program or document can be obtained based on hash algorithm, compares
" digital finger-print " and the original " fingerprint " for being stored in place of safety can find the modification of virus or invader to program or document.
3) password storage.The hash value of password is generated based on hash algorithm, then saves the hash value of password in systems,
Rather than password itself, the safety of system can be improved in this way.Even if hacker has stolen the hash value saved in system, still
Password can not be obtained, system cannot be also logged into.
In the prior art, the hardware implementations of hash algorithm can only realize a kind of hash algorithm, need by multiple hard
Part scheme realizes a variety of hash algorithms, and poor universality is at high cost.
Summary of the invention
In view of this, the present invention is directed to propose a kind of circuit for supporting a variety of hash algorithms, a kind of efficient, logical to provide
With, low cost hash algorithm hardware implementations.
In order to achieve the above objectives, the technical scheme of the present invention is realized as follows:
A kind of circuit for supporting a variety of hash algorithms, comprising: initialization logic, constant selection logic, message processing logic,
Iterative logical, MUX and hash value register array,
Initialization logic, the forward direction hash value register array for starting in iteration assign initial value；
Constant selects logic, selects to need according to the wheel number of specific hash algorithm type and iteration to be sent to iteration and patrol
Collect the constant value for carrying out operation；
Message processing logic calculates the message value that every wheel iteration needs for the origination message according to input；
Iterative logical, it is defeated for selecting logic, message processing logic and hash value register array to provide according to constant
Enter value and calculating is iterated to the message of input, the result of every wheel iterative calculation is stored in hash value register array；
MUX, for switching the on-off of hash value register array and initialization logic or iterative logical；
Hash value register array, for storing the result of every wheel iteration.
Further, it supports also to support the segment processing to a message to the continuous processing of a message；
The initialization logic includes two kinds of situations: the first situation, for first block of a message, repeatedly
The iteration initial value that corresponding hash algorithm defines is loaded into hash value register array for before starting；Second situation is pair
In segment processing, for non-first block of a message, by the previous segmentation of same message before iteration starts
Iteration result is loaded into hash value register array.
Further, the constant selection logic selects constant value especially by several multiple selector MUX, is selected
Control signal when selecting includes message input enable signal, algorithm type indication signal, iteration wheel number.
Further, the message processing logic include message registers array, Lai Jicun message and do iterative processing and
It updates.
Further, a variety of hash algorithms include MD5, SHA0, SHA1, SHA224, SHA256, SHA384, SHA512,
SM3。
Further, the message processing logic starts to change for non-SM3 algorithm when inputting first origination message value
In generation, calculates, and for SM3 algorithm, starts to iterate to calculate when inputting the 4th origination message value.
Further, the iterative logical is realized by multiple adders, and the defeated of adder is arranged according to the type of algorithm
Enter end, the input termination 0 that adder does not use.
Further, the MUX selects 1 control switch for one 2, in first block input of message and disappears
When first block input of non-first segmentation of breath, initialization logic and hash value register array are connected；When initial
After the completion of change, that is, it is switched to iterative logical and hash value register array is connected.
Further, last take turns iteration after hash value register array in value, for algorithm SM3 using
One XOR operation is final hash value；For non-SM3 algorithm using an add operation be final hash value.
Compared with the existing technology, circuit of the present invention has the advantage that
(1) circuit implementing scheme of the present invention supports the hash algorithm of current mainstream, including MD5, SHA0, SHA1,
SHA224, SHA256, SHA384, SHA512, SM3 share hardware money to the greatest extent while supporting these hash algorithms
Source, it is general, inexpensive to achieve the purpose that with this.
(2) present invention carries out the design that a wheel iterates to calculate and reasonably carries out circuit by each clock cycle, reaches
To highest clock frequency, to realize high efficiency.
Detailed description of the invention
The attached drawing for constituting a part of the invention is used to provide further understanding of the present invention, schematic reality of the invention
It applies example and its explanation is used to explain the present invention, do not constitute improper limitations of the present invention.In the accompanying drawings:
Fig. 1 is the overall circuit configuration block diagram of the embodiment of the present invention；
Fig. 2 is continuous processing of embodiment of the present invention data flow diagram；
Fig. 3 is segment processing of embodiment of the present invention data flow diagram；
Fig. 4 is that the non-SM3 algorithm of the embodiment of the present invention inputs messaging sequences schematic diagram；
Fig. 5 is that SM3 of embodiment of the present invention algorithm inputs messaging sequences schematic diagram.
Specific embodiment
It should be noted that in the absence of conflict, the feature in embodiment and embodiment in the present invention can phase
Mutually combination.
The present invention will be described in detail below with reference to the accompanying drawings and embodiments.
A kind of circuit for supporting a variety of hash algorithms of the present embodiment, a variety of hash algorithms include MD5, SHA0, SHA1,
SHA224,SHA256,SHA384,SHA512,SM3；This circuit is supported also to support to disappear to one to the continuous processing of a message
The segment processing of breath can be inserted another message between two sections of a message and be handled；
As shown in Figure 1, the circuit include: initialization logic, constant selection logic, message processing logic, iterative logical,
MUX and hash value register array,
Initialization logic, for completing the initialization of hash value register array, i.e., the forward direction hash value started in iteration
Register array assigns initial value；It include two kinds of situations: the first situation when specific implementation, for first block of a message
(the message 1.block1 in the case of continuous processing or the message in the case of segment processing 1. are segmented 1.block1), opens in iteration
The iteration initial value that corresponding hash algorithm defines is loaded into hash value register array before beginning；Second situation, for one
A message non-first block (message 1. in the case of segment processing is segmented 2.block1, and message 1. is segmented 3.block1,
Message 1. is segmented 4.block1 ... ...), by the previous segmentation of the same message inputted by interface before iteration starts
Iteration result (Hash median) is loaded into hash value register array；Initialization logic is input from the outside Hash initial value, with this
To support the segment processing function of message；
Constant selects logic, selects to need according to the wheel number of specific hash algorithm type and iteration to be sent to iteration and patrol
The constant value for carrying out operation is collected, selects constant value specifically by several multiple selector MUX；
Message processing logic, the register comprising 16 64bit, i.e. message registers array (w0~w15) are used for basis
The origination message of input calculates the message value that every wheel iteration needs, and the message of input is deposited into message registers array, right
The message of input is deposited and is shifted, and is iterated calculating after a block is fully entered, is posted with continuing update message
Storage array；
Iterative logical, it is defeated for selecting logic, message processing logic and hash value register array to provide according to constant
Enter value and processing is iterated to the message of input, that is, be iterated calculating, the result of every wheel iterative calculation, which is stored in hash value, posts
In storage array；It is realized especially by multiple adders, 4 input summers comprising 1 64bit bit wide, 1 64bit bit wide
6 input summers and a 64bit bit wide 7 input summers；These three adders are the need of comprehensive various hash algorithms
It asks and proposes, the hash algorithm for supporting adder to have the call, adder is defeated when carrying out different hash algorithm operations
Enter difference, the hash algorithm small for adder demand, the input termination 0 that adder does not use；
MUX selects 1 control switch for one 2, in first block input of message and non-first of message
When first block input of segmentation, initialization logic and hash value register array are connected, is completed after a clock cycle
The initialization of hash value register array, while by message data deposit into w0~w15 of message registers array；When initial
After the completion of change, that is, it is switched to iterative logical and hash value register array is connected, and start to iterate to calculate, later by iterative logical
Hash value register array is updated after the completion of every wheel iteration.
Hash value register array, for storing the result of every wheel iteration.The specification of hash value register array meets need
The maximum hash algorithm of the amount of asking only uses the low level of each register of hash value register array for other hash algorithms, high
Position does not use.
The initialization logic, as shown in Fig. 2, the continuous processing to a message is supported, in first block of message
Start that the iteration initial value that corresponding hash algorithm defines is loaded into the hash value register array before iteration；Such as Fig. 3
It is shown, while supporting the segment processing to a message, the progress of another message can be inserted between two sections of a message
Processing；The iteration result of previous segmentation (Hash median) is loaded into hash value register array before iteration starts
In；
For example, can handle the segmentation of message 2 after a segmentation for having handled message 1, connecing for message 1 is then reprocessed
The segmentation got off；The next segmentation of message 1 is only needed the iteration result of the last period message before iteration starts
It is loaded into hash value register array by the initialization logic.
When it is implemented, control signal when constant selection logic is selected include message input enable signal,
Algorithm type indication signal, iteration wheel number, the constant value of selection include following several:
MD5 algorithm: T [i], s；
SHA0, SHA1 algorithm: Kt；
SHA224, SHA256 algorithm: Kt；
SHA384, SHA512 algorithm: Kt；
SM3 algorithm: Tj。
Above-mentioned constant value is all the constant of corresponding canonical algorithm, and meaning has open document to be described in detail, herein no longer
It is repeated.
In specific implementation process, the length of message processing logic statistical message in the input process of message is disappearing
The ending of breath is filled (padding) message, and the specific filling mode of different hash algorithms is different, message processing logic meeting
It is filled accordingly according to selected hash algorithm.For the message of segmentation, the statistics of message-length can be in this message
Continue to count on the basis of previous segmentation, the length of previous segmentation can be input to together message processing logic with input message
In.
Register of the message processing logic comprising 16 64bit, i.e. message registers array (w0~w15), for
Non- SM3 algorithm starts to iterate to calculate when inputting first origination message value, input message pass order (i.e. for MD5,
The displacement mode of SHA0, SHA1, SHA224, SHA256, SHA384, SHA512 algorithm) as shown in figure 4, wherein w15 is as Wj
Participate in the operation of iterative logical；
For SM3 algorithm, starts to iterate to calculate when inputting the 4th origination message value, input the pass order of message
(i.e. for the displacement mode of SM3 algorithm) is as shown in figure 5, wherein w15 participates in the fortune of iterative logical as Wj together with W ' j
It calculates.
Particularly, for MD5 algorithm, (i.e. 16 wheels are calculated after entire message is input to the message registers array
Afterwards), the value in w0~w14 and w15 is alternately replaced, so as to remain the message when front-wheel iteration needs in w15
Value, shortens the length of iterative logical critical path with this；The sequence of replacement is as follows:
W0: wheel 19,34,56 carries out
W1: wheel 16,22,39,49 carries out
W2: wheel 29,40,54 carries out
W3: wheel 26,35,61 carries out
W4: wheel 23,46,52 carries out
W5: wheel 20,41,59 carries out
W6: wheel 17,36,50 carries out
W7: wheel 30,47,57 carries out
W8: wheel 27,42,48,62 carries out
W9: wheel 24,37,55 carries out
W10: wheel 21,32,45,62 carries out
W11: wheel 18,43,53 carries out
W12: wheel 31,38,60 carries out
W13: wheel 28,33,51 carries out
W14: wheel 25,44,58 carries out
In specific implementation process, the iterative logical by 4 input summers realize algorithm be SHA224, SHA256,
SHA384, SHA512, SM3, in which:
SHA224, SHA256 algorithm are calculated by 4 input summers:
SHA384, SHA512 are calculated by 4 input summers:
SM3 algorithm is calculated by 4 input summers:
SS1=((A < < < 12)+E+ (Tj<<<j))<<<7；
It is MD5, SHA224, SHA256, SHA384, SHA512, SM3 by the algorithm that 6 input summers are realized, in which:
MD5 algorithm is calculated by 6 input summers:
b+((a+F(b,c,d)+X[k]+T[i])<<<s)；
b+((a+G(b,c,d)+X[k]+T[i])<<<s)；
b+((a+H(b,c,d)+X[k]+T[i])<<<s)；
b+((a+I(b,c,d)+X[k]+T[i])<<<s)
SHA224, SHA256, SHA384, SHA512 algorithm are calculated using this adder
SM3 algorithm is calculated by 6 input summers:
TT2=GGj(E,F,G)+H+SS1+Wj
Using 7 input summers realize algorithm be MD5, SHA0, SHA1, SHA224, SHA256, SHA384,
SHA512, SM3, in which:
MD5 algorithm is calculated by 7 input summers:
a+F(b,c,d)+X[k]+T[i]；
a+G(b,c,d)+X[k]+T[i]；
a+H(b,c,d)+X[k]+T[i]；
a+I(b,c,d)+X[k]+T[i]
SHA0, SHA1 algorithm are calculated by 7 input summers:
T=ROTL5(a)+ft(b,c,d)+e+Kt+Wt
SHA224, SHA256 algorithm are calculated using this adder
SHA384, SHA512 algorithm are calculated using this adder
SM3 algorithm is calculated by 7 input summers:
TT2=FFj(A,B,C)+D+SS2+W'j。
Above-mentioned calculation formula and the meaning of each symbol please refer to canonical algorithm, there is the open text of corresponding canonical algorithm
Shelves detailed description, is no longer repeated herein.
When it is implemented, after the completion of initialization, next one clock cycle (for non-SM3 algorithm) of MUX or input the
Iterative logical is switched to (for SM3 algorithm) when four data to connect with hash value register array and start to iterate to calculate.
When it is implemented, the opportunity of the update of the hash value register array is divided into the following three stage:
Stage 1: initialization.
Stage 2: iterative process.
Stage 3: after the completion of iteration.
(A to H) is (right using an XOR operation for value after last takes turns iteration in hash value register array
It is final Hash value in algorithm SM3) or add operation (for non-SM3 algorithm), operation is as follows:
For SM3 algorithm:
A=A^A_ini；B=B^B_ini；C=C^C_ini；D=D^D_ini；E=E^E_ini；F=F^F_ini；G=
G^G _ini；H=H^H_ini；
For non-SM3 algorithm:
A=A+A_ini；B=B+B_ini；C=C+C_ini；D=D+D_ini；E=E+E_ini；F=F+F_ini；G
=G+G_ini；H=H+H_ini.
The present invention provides a kind of design of circuit for supporting a variety of hash algorithms, the working principle of circuit and circuit think ofs
Road.Support the continuous processing to a message, it is only necessary to by corresponding Hash before first block of message starts iteration
The iteration initial value that algorithm defines is loaded into hash value register array, then continuously handles this message.In addition, this
Design also supports that the place of another message can be inserted between two sections of a message to the segment processing of a message
Reason only needs to patrol the iteration result of the previous segmentation of this message by initialization before iteration starts in this mode
It collects and is loaded into hash value register array.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all in essence of the invention
Within mind and principle, any modification, equivalent replacement, improvement and so on be should all be included in the protection scope of the present invention.
Claims (10)
1. a kind of circuit for supporting a variety of hash algorithms, characterized by comprising: initialization logic, constant select logic, message
Logic, iterative logical, MUX and hash value register array are handled,
Initialization logic, the forward direction hash value register array for starting in iteration assign initial value；
Constant selects logic, select to need according to the wheel number of specific hash algorithm type and iteration to be sent to iterative logical into
The constant value of row operation；
Message processing logic calculates the message value that every wheel iteration needs for the origination message according to input；
Iterative logical, the input value for selecting logic, message processing logic and hash value register array to provide according to constant
Calculating is iterated to the message of input, the result of every wheel iterative calculation is stored in hash value register array；
MUX, for switching the on-off of hash value register array and initialization logic or iterative logical；
Hash value register array, for storing the result of every wheel iteration.
2. a kind of circuit for supporting a variety of hash algorithms according to claim 1, it is characterised in that: support to a message
Continuous processing, also support the segment processing to a message；
The initialization logic includes two kinds of situations: the first situation opens first block of a message in iteration
The iteration initial value that corresponding hash algorithm defines is loaded into hash value register array before beginning；Second situation is for dividing
Section processing, for non-first block of a message, by the iteration of the previous segmentation of same message before iteration starts
As a result it is loaded into hash value register array.
3. a kind of circuit for supporting a variety of hash algorithms according to claim 1, it is characterised in that: the constant selection is patrolled
It collects and selects constant value especially by several multiple selector MUX, control signal when being selected includes that message input is enabled
Signal, algorithm type indication signal, iteration wheel number.
4. a kind of circuit for supporting a variety of hash algorithms according to claim 1, it is characterised in that: the Message Processing is patrolled
Collecting includes message registers array, and Lai Jicun message simultaneously does iterative processing and update.
5. a kind of circuit for supporting a variety of hash algorithms according to claim 1, it is characterised in that: a variety of hash algorithm packets
Include MD5, SHA0, SHA1, SHA224, SHA256, SHA384, SHA512, SM3.
6. a kind of circuit for supporting a variety of hash algorithms according to claim 5, it is characterised in that: the Message Processing is patrolled
It collects for non-SM3 algorithm, starts to iterate to calculate when inputting first origination message value, for SM3 algorithm, in input the 4th
Start to iterate to calculate when origination message value.
7. a kind of circuit for supporting a variety of hash algorithms according to claim 1, it is characterised in that: the iterative logical is logical
It crosses multiple adders to realize, the input terminal of adder is set according to the type of algorithm, the input termination 0 that adder does not use.
8. a kind of circuit for supporting a variety of hash algorithms according to claim 7, it is characterised in that: the iterative logical packet
Containing 14 input summer, 16 input summer and 7 input summers are by the algorithm that 4 input summers are realized
SHA224, SHA256, SHA384, SHA512, SM3, in which:
SHA224, SHA256 algorithm are calculated by 4 input summers:
SHA384, SHA512 are calculated by 4 input summers:
SM3 algorithm is calculated by 4 input summers:
SS1=((A < < < 12)+E+ (Tj<<<j))<<<7；
It is MD5, SHA224, SHA256, SHA384, SHA512, SM3 by the algorithm that 6 input summers are realized, in which:
MD5 algorithm is calculated by 6 input summers:
b+((a+F(b,c,d)+X[k]+T[i])<<<s)；
b+((a+G(b,c,d)+X[k]+T[i])<<<s)；
b+((a+H(b,c,d)+X[k]+T[i])<<<s)；
b+((a+I(b,c,d)+X[k]+T[i])<<<s)
SHA224, SHA256, SHA384, SHA512 algorithm are calculated using this adder
SM3 algorithm is calculated by 6 input summers:
TT2=GGj(E,F,G)+H+SS1+Wj
Using 7 input summers realize algorithm be MD5, SHA0, SHA1, SHA224, SHA256, SHA384, SHA512, SM3,
Wherein:
MD5 algorithm is calculated by 7 input summers:
a+F(b,c,d)+X[k]+T[i]；
a+G(b,c,d)+X[k]+T[i]；
a+H(b,c,d)+X[k]+T[i]；
a+I(b,c,d)+X[k]+T[i]
SHA0, SHA1 algorithm are calculated by 7 input summers:
T=ROTL5(a)+ft(b,c,d)+e+Kt+Wt
SHA224, SHA256 algorithm are calculated using this adder
SHA384, SHA512 algorithm are calculated using this adder
SM3 algorithm is calculated by 7 input summers:
TT2=FFj(A,B,C)+D+SS2+W'j。
9. a kind of circuit for supporting a variety of hash algorithms according to claim 1 or 2, it is characterised in that: the MUX is one
A 2 select 1 control switch, message first block input when and message it is non-first segmentation first block
When input, initialization logic and hash value register array are connected；After the completion of initialization, that is, it is switched to iterative logical and Hash
Value register array is connected.
10. a kind of circuit for supporting a variety of hash algorithms, it is characterised in that: hash value register after last takes turns iteration
Value in array, for algorithm SM3 using an XOR operation be final hash value；For non-SM3 algorithm using one
A add operation is final hash value.
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| CN111104165A (en) * | 2019-12-12 | 2020-05-05 | 南京万维御芯计算技术有限公司 | Edge calculation method for saving register resources |
| CN112787799A (en) * | 2020-12-30 | 2021-05-11 | 浙江萤火虫区块链科技有限公司 | Poseidon Hash algorithm implementation circuit and implementation method thereof |
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| CN109687972B (en) | 2021-08-10 |
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