CN109614049A - Flash memory control method, flash controller and flash memory system - Google Patents
Flash memory control method, flash controller and flash memory system Download PDFInfo
- Publication number
- CN109614049A CN109614049A CN201811511427.2A CN201811511427A CN109614049A CN 109614049 A CN109614049 A CN 109614049A CN 201811511427 A CN201811511427 A CN 201811511427A CN 109614049 A CN109614049 A CN 109614049A
- Authority
- CN
- China
- Prior art keywords
- lun
- target
- storage unit
- object run
- queue
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0604—Improving or facilitating administration, e.g. storage management
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Human Computer Interaction (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Debugging And Monitoring (AREA)
Abstract
The embodiment of the present invention proposes a kind of flash memory control method, flash controller and flash memory system, it is related to technical field of memory, in this method: flash controller is after obtaining the object run sent by firmware instruction, by the current state for monitoring target LUN, and when target LUN is in idle condition, object run instruction is added to command queue, and then all operational orders stored in command queue are sent respectively to storage unit by flash controller, so that storage unit executes all operational orders in command queue.A kind of flash memory control method, flash controller provided by inventive embodiments and flash memory system, can simplify the code of firmware, lifting system performance.
Description
Technical field
The present invention relates to technical field of memory, in particular to a kind of flash memory control method, flash controller and flash memory
System.
Background technique
Flash memory (Flash Memory) is used as solid state hard disk (Solid State Drives, SSD) core memory device, tool
It the advantages that standby non-volatile, storage density is high, and read or write speed is much higher than magnetic-based storage media, is in the industry cycle used widely.One
As for, according to the difference of flash capacity, a flush memory device encapsulates one or more target, also referred to as CE (Chip
Enable, chip gating), a CE contains one or more LUN (Logical Unit Number, logical unit number),
LUN is minimum basic administrative unit of the flash memory in communication, is the basic unit that a flash command executes.
Summary of the invention
The purpose of the present invention is to provide a kind of flash memory control method, flash controller and flash memory system, can simplify solid
The code of part, lifting system performance.
To achieve the goals above, technical solution used in the embodiment of the present invention is as follows:
In a first aspect, the embodiment of the invention provides a kind of flash memory control method, applied to what is be electrically connected with storage unit
Flash controller, the storage unit include multiple logical unit number LUN, which comprises obtain the target that firmware is sent
Operational order, wherein the object run instruction includes target LUN;Monitor the current state of the target LUN, wherein institute
Stating current state includes idle state or busy condition;When the target LUN is in idle condition, the object run is referred to
Order is added to command queue, wherein the operation that the command queue is used to record when all corresponding LUN are in idle condition refers to
It enables;Operational orders all in the command queue are sent respectively to the storage unit, so that the storage unit executes institute
State all operational orders in command queue.
Second aspect, the embodiment of the invention provides a kind of flash controllers, applied to the sudden strain of a muscle being electrically connected with storage unit
Memory controller, the storage unit include multiple logical unit number LUN, and the flash controller includes: the first transceiver module, are used
It is instructed in obtaining the object run that firmware is sent, wherein the object run instruction includes target LUN;Status monitoring module,
For monitoring the current state of the target LUN, wherein the current state includes idle state or busy condition;Instruction adds
Add module, for when the target LUN is in idle condition, object run instruction to be added to command queue, wherein
The command queue is used to record operational order when all corresponding LUN are in idle condition;Second transceiver module is used for institute
It states all operational orders in command queue and is sent respectively to the storage unit, so that the storage unit executes the order team
All operational orders in column.
The third aspect, the embodiment of the invention provides a kind of flash memory system, including firmware, storage unit and the present invention are real
Apply flash controller provided by a second aspect;The firmware is used to send object run instruction to the flash controller,
Wherein, the object run instruction includes target LUN;The flash controller is used for the current shape based on the target LUN
The target LUN is sent to the storage unit by state;The storage unit is for executing the object run instruction.
Compared with the existing technology, a kind of flash memory control method, flash controller provided by the embodiment of the present invention and flash memory
System, flash controller is after obtaining the object run sent by firmware instruction, by monitoring the current state of target LUN, and
When target LUN is in idle condition, object run instruction is added to command queue, and then by flash controller by order team
All operational orders stored in column are sent respectively to storage unit, so that storage unit executes all behaviour in command queue
It instructs, compared with the prior art, executes concurrent management and running between multiple LUN no longer by firmware, but by flash memory control
Device processed executes, and can simplify the code of firmware, lifting system performance.
To enable the above objects, features and advantages of the present invention to be clearer and more comprehensible, preferred embodiment is cited below particularly, and cooperate
Appended attached drawing, is described in detail below.
Detailed description of the invention
In order to illustrate the technical solution of the embodiments of the present invention more clearly, below will be to needed in the embodiment attached
Figure is briefly described, it should be understood that the following drawings illustrates only certain embodiments of the present invention, therefore is not construed as pair
The restriction of range for those of ordinary skill in the art without creative efforts, can also be according to this
A little attached drawings obtain other relevant attached drawings.
Fig. 1 is a kind of structural schematic diagram of flash memory system;
Fig. 2 has gone out a kind of a kind of schematic flow chart of flash memory control method provided by the embodiment of the present invention;
Fig. 3 is a kind of logic state schematic diagram of flash controller;
Fig. 4 is a kind of schematic flow chart of the sub-step of S300 in Fig. 2;
Fig. 5 is basic read command sequence diagram;
Fig. 6 is a kind of schematic flow chart of the sub-step of S500 in Fig. 2;
Fig. 7 shows a kind of a kind of schematic diagram of flash controller provided by the embodiment of the present invention;
It is schematic that Fig. 8 shows a kind of one kind of the instruction adding module of flash controller provided by the embodiment of the present invention
Structure chart;
It is schematic that Fig. 9 shows a kind of one kind of second transceiver module of flash controller provided by the embodiment of the present invention
Structure chart.
In figure: 10- flash memory system;100- firmware;200- flash controller;The first transceiver module of 210-;220- state prison
Listen module;230- instructs adding module;231- subqueue determination unit;232- instructs split cells;The addition of 233- subcommand is single
Member;The second transceiver module of 240-;The currently transmitted queue determination unit of 241-;242- instruction sending unit;The switching of 243- subqueue
Unit;300- storage unit.
Specific embodiment
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is
A part of the embodiment of the present invention, instead of all the embodiments.The present invention being usually described and illustrated herein in the accompanying drawings is implemented
The component of example can be arranged and be designed with a variety of different configurations.
Therefore, the detailed description of the embodiment of the present invention provided in the accompanying drawings is not intended to limit below claimed
The scope of the present invention, but be merely representative of selected embodiment of the invention.Based on the embodiments of the present invention, this field is common
Technical staff's every other embodiment obtained without creative efforts belongs to the model that the present invention protects
It encloses.
It should also be noted that similar label and letter indicate similar terms in following attached drawing, therefore, once a certain Xiang Yi
It is defined in a attached drawing, does not then need that it is further defined and explained in subsequent attached drawing.Meanwhile of the invention
In description, term " first ", " second " etc. are only used for distinguishing description, are not understood to indicate or imply relative importance.
It should be noted that, in this document, relational terms such as first and second and the like are used merely to a reality
Body or operation are distinguished with another entity or operation, are deposited without necessarily requiring or implying between these entities or operation
In any actual relationship or order or sequence.Moreover, the terms "include", "comprise" or its any other variant are intended to
Non-exclusive inclusion, so that the process, method, article or equipment including a series of elements is not only wanted including those
Element, but also including other elements that are not explicitly listed, or further include for this process, method, article or equipment
Intrinsic element.In the absence of more restrictions, the element limited by sentence "including a ...", it is not excluded that
There is also other identical elements in process, method, article or equipment including the element.
With reference to the accompanying drawing, it elaborates to some embodiments of the present invention.In the absence of conflict, following
Feature in embodiment and embodiment can be combined with each other.
Read-write wiping is the basic operation that flash memory completes data transfer, storage and management.From the point of view of flash memory, read command from
Flash memory internal storage array reads data;It writes (programming) order and completes data write-in flash memory internal storage array;Erasing order is complete
At flash memory internal storage array data dump.
For example, referring to Fig. 1, Fig. 1 be a kind of flash memory system 10 structural schematic diagram, in the flash memory system 10, including
There are firmware 100, flash controller 200 and storage unit 300, firmware 100 and flash controller 200 communicate to connect, and flash memory control
Device 200 processed is electrically connected with storage unit 300;Storage unit 300 includes multiple LUN, and all LUN are divided into multiple CE,
And every CE is electrically connected with flash controller 200, such as in schematic diagram as shown in Figure 1, it is assumed that is drawn according to every two LUN
It is divided into the principle of 1 CE, total divide of the LUN of 2n quantity has n CE.
Due to one of the characteristic of LUN are as follows: LUN does not allow to receive new instruction when executing operational order, this limitation energy
Enough ensure that LUN instruction is correctly performed.But for Multi-LUN flash memory system 10 as shown in Figure 1, in order to promote flash memory
Performance generally requires the concurrent of Multi-LUN, that is, multiple LUN are performed simultaneously respective instruction, such as shown in Figure 1
Schematic diagram in, although LUN1 when executing operational order, does not allow to receive new instruction, LUN2 either others LUN
Can receive the operational order of the transmission of flash controller 200, it is this make different LUN interlock execute the strategy of operational order can be with
Promote the performance of flash memory system 10.
And the concurrent capability of above-mentioned Multi-LUN depends on the management and running of flash memory system 10, in general, flash memory system
10 include LUN quantity it is more, and concurrent LUN quantity is more, and performance is better.For flash memory system 10 as shown in Figure 1, existing
Have in technology, it is general to realize that Multi-LUN's is concurrent by the way of firmware scheduling.For example flash memory system 10 is receiving user
When two of input read the operational order of data in two difference LUN respectively, two operational orders were carried out by firmware 100 before this
Resolution scheduling, then the operational order after parsing is sent to flash controller 200 again by firmware 100, flash controller 200 again under
It is sent to storage unit 300, so that storage unit 300 executes the operational order of user.
Above-mentioned technical proposal can flexibly complete the management and running of different LUN orders, the LUN of flexible handover execution command.
But since the scheduling of all LUN is operated by firmware 100, it is therefore desirable to it is above-mentioned to realize to increase the program of firmware 100
Management and running, it is higher so as to cause 100 complexity of firmware, and then make that system performance is caused to reduce.
Based on the defect of the above-mentioned prior art, a kind of improved procedure provided by the embodiment of the present invention is: flash memory control
Device 200 is after obtaining the object run sent by firmware 100 instruction, by monitoring the current state of target LUN, and in target
When LUN is in idle condition, object run instruction is added to command queue, and then by flash controller 200 by command queue
Middle stored all operational orders are sent respectively to storage unit 300, so that storage unit 300 executes the institute in command queue
There is operational order.
Referring to Fig. 2, Fig. 2 shows a kind of one kind of flash memory control method provided by the embodiment of the present invention schematically to flow
Cheng Tu, the flash memory control method are applied to the flash controller 200 in Fig. 1, in embodiments of the present invention, the flash memory control method
The following steps are included:
S100 obtains the object run instruction that firmware is sent.
S200 monitors the current state of target LUN;When the current state of target LUN is idle state, S300 is executed;
When the current state of target LUN is busy condition, S210 is executed.
In embodiments of the present invention, flash memory system 10 is when receiving ownership goal operational order, for example reads in LUN1
Data, firmware 100 no longer does management and running to object run instruction, and flash controller 200 is destined to, so that flash memory control
Device 200 processed is scheduled management to object run instruction, wherein includes target LUN, target LUN in object run instruction
The concrete operations object of object run instruction is characterized, such as in schematic diagram as shown in Figure 1, it is assumed that flash controller 200 connects
The target LUN for including in the object run instruction received is LUN1, then the operation object for characterizing object run instruction is LUN1.
Correspondingly, flash controller 200 obtain object run instruction when, according to object run instruct in include target
LUN monitors the current state of target LUN;Wherein, the current state of target LUN includes busy condition and idle state;Busy shape
State characterization target LUN is currently executing operational order, cannot receive new operational order;And idle state characterizes target LUN
It currently is not carried out operational order, can receive operational order.
Therefore, it when flash controller 200 monitors target LUN and determines that the current state of target LUN is idle state, holds
Row S300;And when flash controller 200 determines that the current state of target LUN is busy condition, execute S210.
Optionally, flash controller 200 is provided with lookup of state table in advance, and lookup of state table record has every LUN each
From current state, which not only can recorde whether every LUN idle or busy, and also record has LUN busy
When operated instruction content, for example, in schematic diagram as shown in Figure 1, it is assumed that LUN1 when executing the instruction for reading data,
The current state that LUN1 is recorded in lookup of state table is then " LUN1;It is busy;Read xxx ".Wherein, one in storage unit 300
The well matched register being equipped with for recording the respective current state of every LUN, flash controller 200 can be by reading in the register
The mode of the content of record, and then the current state of every LUN is recorded in lookup of state table.
As a result, in embodiments of the present invention, flash controller 200 monitors a kind of embodiment party of the current state of target LUN
Formula are as follows: current state corresponding with target LUN is searched in lookup of state table.Such as the LUN1 to include in CE0 in Fig. 1
It illustrates with LUN2, it is assumed that the current state of the LUN1 and both LUN2 that record in lookup of state table are respectively " LUN1;It is busy;It reads
Take xxx ", " LUN2;It is idle;", if the target LUN for including in the object run instruction that flash controller 200 obtains is LUN1,
It is then " busy according to the current state of the listened to target LUN of the lookup of state table;Xxx " is read, if flash controller 200 obtains
Object run instruction in include target LUN when being LUN2, then working as according to the listened to target LUN of lookup of state table
Preceding state is " free time ".
It is worth noting that flash controller 200 can also be adopted in a kind of embodiment of others of the embodiment of the present invention
The current state of target LUN is obtained with other some modes, for example does not configure lookup of state table in flash controller 200, and
It is when obtaining object run instruction, flash controller 200 directly reads the content of the record of the register in storage unit 300,
To directly obtain the current state of target LUN.In brief, as long as flash controller 200 is when obtaining object run instruction,
The current state for the target LUN for including in object run instruction can be obtained, such as, flash controller can also be used
200 modes directly communicated with CE belonging to target LUN, to obtain the current state of target LUN.
Please continue to refer to Fig. 2, S300, object run instruction is added to command queue.
When it is idle state that flash controller 200, which listens to target LUN current state, characterization target LUN is not held currently
Row operational order can receive new operational order, to respond the operation of user, at this point, flash controller 200 is then by the target
Operational order is added to command queue, wherein the command queue is used to record operation when all corresponding LUN are in idle condition
Instruction, that is to say, that the operational order recorded in command queue is the operational order that corresponding LUN can be executed directly.
Optionally, which includes multiple subqueues, and each subqueue is previously configured as storing at least one
The operational order of LUN.Such as Fig. 1 and Fig. 3 is please referred to, Fig. 3 is that a kind of logic state of flash controller 200 is illustrated
Command queue is gone out multiple subqueues according to the model split for dividing multiple CE in Fig. 1 by figure, and each subqueue is one corresponding
CE, then at this point, each subqueue then corresponds to the operational order of two LUN in schematic diagram as shown in Figure 3.
Also, in general, a complete operational order has generally included multiple subcommands, for example includes under order
Send out (operation command code+operation object), data input (programming), data output (reading) and LUN status monitoring etc., wherein LUN
Status monitoring predominantly detects LUN order execution state (ready/busy) and implementing result (fail/success), this is flash memory
Controller 200 sends new operational order and (does not receive new operation because of the LUN in busy condition to the important evidence of LUN
Instruction).
Therefore, in embodiments of the present invention, each subqueue in command queue is divided into first queue and second queue,
Wherein, first queue is used to store son life of the flash controller 200 before the current state for monitoring target LUN in operational order
It enables, and second queue is used to store flash controller 200 in operational order when monitoring the current state of target LUN or monitors mesh
Subcommand after marking the current state of LUN.
Therefore, as an implementation, referring to Fig. 4, one kind that Fig. 4 is the sub-step of S300 in Fig. 2 schematically flows
Cheng Tu, in embodiments of the present invention, S300 include following sub-step:
S310 determines target subqueue belonging to target LUN.
In embodiments of the present invention, flash controller 200 by object run instruction be added to command queue when, first according to
The target LUN for including in object run instruction, determine with target subqueue belonging to target LUN, such as in such as Fig. 1 and such as
In schematic diagram shown in Fig. 3, if the operational order of LUN1 is added to command queue by flash controller 200, flash controller
200 determine that CE belonging to the LUN1 is CE1, and flash controller 200 is using subqueue corresponding to CE1 as target as a result,
Queue.
S320 splits object run order, obtains first kind target subcommand and the second class target subcommand.
S330, first first kind target subcommand and the second class target subcommand are added separately in target subqueue
Queue and second queue.
As described above, a complete operational order has generally included multiple subcommands, for example, referring to Fig. 5, Fig. 5 is
Basic read command sequence diagram, which includes multiple subcommands, including order issues (operation command code+behaviour
Make object), address issues, data input (programming), data output (reading) and LUN status monitoring (output LUN status
+poll expected status).Flash controller 200 when storing the read command sequence, according to monitor target LUN when
Between sequence, which is divided, such as, according to tR the time of consumption (read), by the order sequence before tR
Column are divided into first kind target subcommand, and the command sequence after tR moment and tR is divided into the second class target subcommand,
Wherein, the subcommand before first kind target subcommand is the current state for monitoring target LUN in object run order, the second class
Target subcommand is when monitoring the current state of target LUN in object run order or after the current state of monitoring target LUN
Subcommand.Since the time of the acquisition first kind target subcommand of flash controller 200 is before obtaining the second class target subcommand,
Therefore, as an implementation, first kind target subcommand preferentially can be sent to storage unit 300 by flash controller 200,
So that target LUN preferentially executes first kind target subcommand.
As a result, after object run instruction is marked off first kind target subcommand and the second class target subcommand, flash memory
First kind target subcommand and the second class target subcommand are added separately to the first team in target subqueue by controller 200
Column and second queue, such as, flash controller 200 obtains basic read command sequence as shown in Figure 5, and the basic read command
The operation object of sequence is therefore LUN1, then reads this substantially since in schematic diagram as shown in Figure 1, LUN1 belongs to CE1
The first kind target subcommand that command sequence obtains after splitting is added in the first queue that CE1 as shown in Figure 3 includes, and incite somebody to action
Second class target subcommand is added in the second queue that CE1 as shown in Figure 3 includes.
As noted previously, as LUN cannot receive new operational order when executing operational order again, and it is stored in order
Operational order in queue is LUN operational order to be executed, and therefore, object run instruction is added in command queue,
Mean that target LUN in next one section of timing, cannot receive new operational order again.
Therefore, as an implementation, please continue to refer to Fig. 2, in embodiments of the present invention, after executing S300,
The flash memory control method is further comprising the steps of:
S400 updates lookup of state table.
In embodiments of the present invention, flash controller 200 is added in command queue by object run instruction, then is updated
Lookup of state table, so that current state of the target LUN in lookup of state table is revised as busy condition.For example, flash controller
The 200 object runs instructions that obtain are basic read command sequence as shown in Figure 5, and the effective object of the basic read command sequence
For LUN1, if flash controller 200 when obtaining the basic read command sequence, records the current state of LUN1 in lookup of state table
For " LUN1;It is idle;", which is then added to command queue by flash controller 200, and then more new state is looked into
Table is looked for, the current state that LUN1 is recorded in lookup of state table is updated to " LUN1;It is busy;";Moreover flash memory control
The command context of the basic read command sequence can also be updated in lookup of state table by device 200 processed, for example, looking into more new state
When looking for table, the current state that LUN1 is recorded in lookup of state table is updated to " LUN1;It is busy;Xxx " is read, and then is made subsequent
A period of time sequence in, other operational orders for acting on LUN1 are no longer added in command queue by flash controller 200.
Please continue to refer to Fig. 2, S500, operational orders all in command queue are sent respectively to storage unit.
It is that will be sent to storage unit 300 for holding as described above, being added to all operational orders of command queue
Capable operational order, flash controller 200 need all operational orders in command queue being sent respectively to storage unit
300, so that storage unit 300 executes all operational orders in command queue, to respond the operation of user.
It is worth noting that conventionally, as flash controller 200 can not once just refer to all operations
Order is sent to storage unit 300, needs that all operational orders in command queue are sent to storage unit item by item
300。
Therefore, it as an implementation, is asked based on the above-mentioned prior art in order to realize the con current control of Multi-LUN
Refering to Fig. 6, Fig. 6 be Fig. 2 in S500 sub-step a kind of schematic flow chart, in embodiments of the present invention, S500 include with
Lower sub-step:
S510 determines current subqueue in multiple subqueues.
S520, all subcommands for being included by the first queue in current subqueue are sent respectively to storage unit.
As shown in figure 3, in the command queue of flash controller 200, all operations that flash controller 200 can be obtained
Instruction carries out classification storage according to the LUN that each operational order includes, such as, according to classification as shown in Figure 1, by operation pair
As being stored in the corresponding subqueue of CE1 for the operational order of LUN1 or LUN2, the operation for being LUN3 or LUN4 by operation object
Instruction is stored in the corresponding subqueue of CE2.And so on, according to each operational order operation object carry out classification storage in
In multiple subqueues.
However, again since in the prior art, flash controller 200 can only be item by item by all behaviour in command queue
Make instruction and is sent to storage unit 300.Therefore, flash controller 200 is sent to by all operational orders in command queue
When storage unit 300, current subqueue is determined in multiple subqueues first, which is flash memory control
Currently selection is sent to the subqueue where the operational order of storage unit 300 to device 200.Such as flash controller 200 selects
When the corresponding subqueue of CE1 is as current subqueue, then the behaviour that flash controller 200 is currently sending to storage unit 300 is characterized
Make instruction and belongs to subqueue corresponding with CE1.
Wherein, when flash controller 200 determines current subqueue in multiple subqueues, round- can be used
Robin resolving strategy (Time Slice Circular Scheduling method), arbitrates out current subqueue in multiple subqueues, can also according to CE1,
The mode of CE2CEn sequentially determines current subqueue, as long as flash controller 200 can be in multiple sub- teams
Current subqueue is determined in column, such as, it, can be in some other possible embodiment of the embodiment of the present invention
Current subqueue is determined in multiple subqueues by the way of randomly selecting.
Also, as noted previously, as needing to instruct object run when storing object run instruction to command queue
It is split as first kind target subcommand and the second class target subcommand, and is respectively stored in target subqueue.That is, every
One operational order is split as two class subcommands when being stored to command queue, and is respectively stored in affiliated subqueue
In first queue and second queue.
Therefore, the above-mentioned current subqueue determined, the arbitration being only completed between the corresponding subqueue of different CE, in flash memory control
It include first queue and second queue in the current subqueue that device 200 processed is determined, wherein first queue storage is to dodge
Subcommand of the memory controller 200 before the current state for monitoring LUN, and second queue storage is that flash controller 200 exists
Therefore subcommand when monitoring the current state of LUN or after the current state of monitoring LUN in timing, stores in first queue
Subcommand earlier than the subcommand stored in second queue.
Therefore, in embodiments of the present invention, flash controller 200, preferentially will current son after determining current subqueue
All subcommands that first queue in queue is included are sent respectively to storage unit 300, so that corresponding in current subqueue
CE included LUN in realize it is concurrent.
Such as in schematic diagram as shown in Figures 1 and 3, since CE1 contains LUN1 and LUN2, then flash controller
200 when acquisition operation object is respectively two operational orders of LUN1 and LUN2, in the corresponding subqueue of CE1, the subqueue
First queue can store the first kind subcommand of LUN1 and LUN2, as a result, by all first kind subcommands in first queue
It is sent respectively to the LUN (LUN1 and LUN2) that CE1 includes, it is concurrent between multiple LUN to be realized inside CE1.
It is worth noting that the operation that may only only exist a LUN in current subqueue refers in application scenes
It enables, such as in the above-described example, if flash controller 200 only obtains the operational order that operation object is LUN1, at this point, CE1 pairs
In the first queue for the subqueue answered, then the first kind subcommand that operation object is LUN1 is contained only, then at this time in CE1
Portion, there is no the concurrent of multiple LUN.
S530, judge current LUN corresponding to current subqueue execute time of received subcommand whether reach pre-
If time threshold;When reached, S540 is executed;When not up to, returns and execute S510.
S540, by current LUN, corresponding subcommand is sent to storage unit in the second queue in current subqueue.
In general, storage unit 300 execute operational order need consumption time, for example, read command can consume it is tens of delicate
(tR), program command needs to consume several milliseconds (tPROG), and erasing order needs to consume several ms (tBERS), due to LUN
It is only allowed one order of execution in synchronization, therefore, flash controller 200 is sent to by the subcommand in first queue
When storage unit 300, then other subcommands cannot be received again with current LUN corresponding to current subqueue, that is to say, that dodge
Subcommand in first queue and second queue continuously cannot be sent to same LUN by memory controller 200, it is necessary to be waited pending
Give storage unit 300 subcommand be performed after the completion of, the corresponding subcommand in second queue of the current LUN could be sent
To storage unit 300, so that current LUN is continued to execute in the second queue of current subqueue, belong to the subcommand of current LUN.
If the subcommand in first queue is waited to execute completion, then execute each comfortable order team of LUN that other CE include
The operational order stored in column, then may storage unit 300 can be only done the LUN in CE corresponding to current subqueue execution
Operational order.
Therefore, in embodiments of the present invention, the time for needing to consume in execution operational order based on storage unit 300, dodge
Memory controller 200 starts timing when all subcommands in first queue are sent respectively to storage unit 300, when by the
After all subcommands in one queue are sent to storage unit 300, flash controller 200 then judges corresponding to current subqueue
Current LUN execute time of received subcommand whether reach preset time threshold, be to judge storage unit 300 with this
It is no to have executed the received order of institute.
Wherein, after all subcommands in first queue are sent respectively to storage unit 300 by flash controller 200,
If the time that flash controller 200 determines that current LUN executes received subcommand corresponding to current subqueue reaches pre-
If when time threshold, characterizing current LUN can receive new subcommand, at this point, executing S540, flash controller 200 will be current
LUN corresponding subcommand in the second queue in current subqueue is sent to storage unit 300 so that storage unit 300 after
It is continuous to execute the remaining subcommand of operational order;Conversely, when flash controller 200 determines current LUN corresponding to current subqueue
When executing received subcommand and being not up to preset time threshold, then current LUN is characterized currently also in executing first queue
Subcommand, be in busy condition, new subcommand cannot be executed, at this time flash controller 200 then by return execute S510, weight
Newly determine new subqueue as current subqueue, and then again using the LUN that other CE are included as send subcommand pair
As realizing that multiple LUN's between different CE is concurrent by 200 end of flash controller.
Based on above-mentioned design, a kind of flash memory control method provided by the embodiment of the present invention, flash controller 200 is being obtained
After the object run instruction sent by firmware 100, idle shape is in by monitoring the current state of target LUN, and in target LUN
When state, object run instruction is added to command queue, and then all by what is stored in command queue by flash controller 200
Operational order is sent respectively to storage unit 300, so that storage unit 300 executes all operational orders in command queue, phase
Than executing concurrent management and running between multiple LUN no longer by firmware 100, but by flash controller 200
It executes, can simplify the code of firmware 100, lifting system performance.
It as an implementation, is busy when monitoring the current state of acquisition target LUN by S200 please continue to refer to Fig. 2
When commonplace state, the flash memory control method is further comprising the steps of:
Object run instruction is added to waiting list by S210.
Flash controller 200 is when monitoring the current state of target LUN, if flash controller 200 determines that target LUN is current
In busy condition, then the currently obtained object run instruction of flash controller 200 cannot be executed by characterizing target LUN at this time,
Object run instruction is then added in waiting list by flash controller 200 as a result, so that flash controller 200 is subsequent
When the operational order stored in waiting list is re-used as object run instruction, S200 is continued to execute.
Referring to Fig. 7, Fig. 7 shows a kind of one kind of flash controller 200 provided by the embodiment of the present invention schematically
Structure chart, the flash controller 200 can be used as flash controller 200 as shown in figure 1, in embodiments of the present invention, the flash memory control
Device 200 processed includes the first transceiver module 210, status monitoring module 220, instruction adding module 230 and the second transceiver module 240.
First transceiver module 210 is used to obtain the object run instruction of the transmission of firmware 100, wherein the object run refers to
Order includes target LUN.
Status monitoring module 220 is used to monitor the current state of the target LUN, wherein the current state includes sky
Not busy state or busy condition.
Optionally, as an implementation, the flash controller 200 is provided with lookup of state table, the shape in advance
State look-up table record has every respective current state of a LUN.The status monitoring module 220 is used in the lookup of state table
Search current state corresponding with the target LUN.
It instructs adding module 230 to be used for when the target LUN is in idle condition, the object run is instructed and is added
To command queue, wherein the command queue is used to record operational order when all corresponding LUN are in idle condition.
Optionally, as an implementation, referring to Fig. 8, Fig. 8 shows a kind of sudden strain of a muscle provided by the embodiment of the present invention
A kind of schematic diagram of the instruction adding module 230 of memory controller 200, in embodiments of the present invention, the instruction add mould
Block 230 includes subqueue determination unit 231, instruction split cells 232 and subcommand adding unit 233.
Subqueue determination unit 231 is for determining target subqueue belonging to the target LUN.
Instruction split cells 232 obtains first kind target subcommand and the second class for splitting the object run order
Target subcommand, wherein the first kind target subcommand is to monitor the current of the target LUN in the object run order
Subcommand before state, the second class target subcommand are to monitor working as the target LUN in the object run order
Subcommand when preceding state or after the current state of the monitoring target LUN.
Subcommand adding unit 233 is used to distinguish the first kind target subcommand and the second class target subcommand
The first queue and second queue being added in the target subqueue.
Please continue to refer to Fig. 7, the second transceiver module 240 for sending operational orders all in the command queue respectively
To the storage unit 300, so that the storage unit 300 executes all operational orders in the command queue.
Referring to Fig. 9, Fig. 9 shows a kind of second transmitting-receiving mould of flash controller 200 provided by the embodiment of the present invention
A kind of schematic diagram of block 240, in embodiments of the present invention, second transceiver module 240 include that currently transmitted queue is true
Order member 241 and instruction sending unit 242.
Currently transmitted queue determination unit 241 in the multiple subqueue for determining current subqueue.
Instruction sending unit 242 is used for all subcommands for being included by the first queue in the current subqueue and distinguishes
It is sent to the storage unit 300.
It is received that described instruction transmission unit 242 is also used to work as current LUN execution institute corresponding to the current subqueue
It is when the time of subcommand reaches preset time threshold, the current LUN is right in the second queue in the current subqueue
The subcommand answered is sent to the storage unit 300.
Optionally, as an implementation, in embodiments of the present invention, second transceiver module 240 further includes son
Queue switch unit 243, the subqueue switch unit 243 are used to work as current LUN corresponding to the current subqueue and execute
Time of received subcommand when being not up to preset time threshold, switch the current subqueue, by the currently transmitted team
Current subqueue is determined in the continuation of column determination unit 241 in the multiple subqueue.
Optionally, as an implementation, please continue to refer to Fig. 7, in embodiments of the present invention, described instruction adds mould
Block 230 is also used to when the target LUN is in busy condition, and object run instruction is added to waiting list.
The embodiment of the invention also provides a kind of flash memory system 10, including firmware 100, storage unit 300 and above-mentioned
Flash controller 200, the firmware 100 are used to send object run instruction to the flash controller 200, wherein the mesh
Marking operational order includes target LUN;The flash controller 200 is used for the current state based on the target LUN, will be described
Target LUN is sent to the storage unit 300;The storage unit 300 is for executing the object run instruction.
In embodiment provided herein, it should be understood that disclosed device and method, it can also be by other
Mode realize.The apparatus embodiments described above are merely exemplary, for example, the flow chart and block diagram in attached drawing are shown
Device, the architectural framework in the cards of method and computer program product, function of multiple embodiments according to the present invention
And operation.In this regard, each box in flowchart or block diagram can represent one of a module, section or code
Point, a part of the module, section or code includes one or more for implementing the specified logical function executable
Instruction.It should also be noted that function marked in the box can also be attached to be different from some implementations as replacement
The sequence marked in figure occurs.For example, two continuous boxes can actually be basically executed in parallel, they sometimes may be used
To execute in the opposite order, this depends on the function involved.It is also noted that each of block diagram and or flow chart
The combination of box in box and block diagram and or flow chart can be based on the defined function of execution or the dedicated of movement
The system of hardware is realized, or can be realized using a combination of dedicated hardware and computer instructions.
In addition, each functional module in each embodiment of the present invention can integrate one independent portion of formation together
Point, it is also possible to modules individualism, an independent part can also be integrated to form with two or more modules.
In conclusion a kind of flash memory control method, flash controller provided by the embodiment of the present invention and flash memory system, dodge
Memory controller 200 obtains after the object run instruction sent by firmware 100, by the current state of monitoring target LUN, and
When target LUN is in idle condition, object run instruction is added to command queue, and then will be ordered by flash controller 200
All operational orders stored in queue are sent respectively to storage unit 300, so that storage unit 300 executes in command queue
All operational orders execute concurrent management and running between multiple LUN no longer by firmware 100 compared with the prior art, and
It is to be executed by flash controller 200, the code of firmware 100, lifting system performance can be simplified.
The foregoing is only a preferred embodiment of the present invention, is not intended to restrict the invention, for the skill of this field
For art personnel, the invention may be variously modified and varied.All within the spirits and principles of the present invention, made any to repair
Change, equivalent replacement, improvement etc., should all be included in the protection scope of the present invention.
It is obvious to a person skilled in the art that invention is not limited to the details of the above exemplary embodiments, Er Qie
In the case where without departing substantially from spirit or essential attributes of the invention, the present invention can be realized in other specific forms.Therefore, no matter
From the point of view of which point, the present embodiments are to be considered as illustrative and not restrictive, and the scope of the present invention is by appended power
Benefit requires rather than above description limits, it is intended that all by what is fallen within the meaning and scope of the equivalent elements of the claims
Variation is included within the present invention.Any reference signs in the claims should not be construed as limiting the involved claims.
Claims (10)
1. a kind of flash memory control method, which is characterized in that applied to the flash controller being electrically connected with storage unit, the storage
Unit includes multiple logical unit number LUN, which comprises
Obtain the object run instruction that firmware is sent, wherein the object run instruction includes target LUN;
Monitor the current state of the target LUN, wherein the current state includes idle state or busy condition;
When the target LUN is in idle condition, object run instruction is added to command queue, wherein the life
Enable queue for recording operational order when all corresponding LUN are in idle condition;
Operational orders all in the command queue are sent respectively to the storage unit, so that the storage unit executes institute
State all operational orders in command queue.
2. the method as described in claim 1, which is characterized in that the flash controller is provided with lookup of state table, institute in advance
Stating lookup of state table record has every respective current state of a LUN;
The step of current state for monitoring the target LUN, comprising:
Current state corresponding with the target LUN is searched in the lookup of state table.
3. method according to claim 2, which is characterized in that object run instruction is added to command queue described
The step of after, the method also includes:
Update the lookup of state table so that current state of the target LUN in the lookup of state table be revised as it is busy
State.
4. the method as described in claim 1, which is characterized in that the command queue includes multiple subqueues, each son
Queue is previously configured as storing the operational order of at least one LUN, and each subqueue includes first queue and
Two queues;
Described the step of object run instruction is added to command queue, comprising:
Determine target subqueue belonging to the target LUN;
The object run order is split, obtains first kind target subcommand and the second class target subcommand, wherein described first
Class target subcommand be the current state for monitoring the target LUN in the object run order before subcommand, described the
Two class target subcommands are when monitoring the current state of the target LUN in the object run order or to monitor the target
Subcommand after the current state of LUN;
The first kind target subcommand and the second class target subcommand are added separately in the target subqueue
First queue and second queue.
5. method as claimed in claim 4, which is characterized in that described to send out operational orders all in the command queue respectively
The step of giving the storage unit, comprising:
Current subqueue is determined in the multiple subqueue;
All subcommands that first queue in the current subqueue is included are sent respectively to the storage unit;
The current LUN corresponding to the current subqueue execute time of received subcommand reach preset time threshold
When, by the current LUN, corresponding subcommand is sent to the storage unit in the second queue in the current subqueue.
6. method as claimed in claim 5, which is characterized in that described to send out operational orders all in the command queue respectively
The step of giving the storage unit, further includes:
The current LUN corresponding to the current subqueue execute time of received subcommand be not up to preset time threshold
When, it returns and executes described the step of determining current subqueue in the multiple subqueue.
7. the method as described in claim 1, which is characterized in that the method also includes:
When the target LUN is in busy condition, object run instruction is added to waiting list.
8. a kind of flash controller, which is characterized in that applied to the flash controller being electrically connected with storage unit, the storage is single
Member includes multiple logical unit number LUN, and the flash controller includes:
First transceiver module, for obtaining the object run instruction of firmware transmission, wherein the object run instruction includes mesh
Mark LUN;
Status monitoring module, for monitoring the current state of the target LUN, wherein the current state includes idle state
Or busy condition;
Adding module is instructed, for when the target LUN is in idle condition, object run instruction to be added to order
Queue, wherein the command queue is used to record operational order when all corresponding LUN are in idle condition;
Second transceiver module, for operational orders all in the command queue to be sent respectively to the storage unit, so that
The storage unit executes all operational orders in the command queue.
9. flash controller as claimed in claim 8, which is characterized in that described instruction adding module is also used to, when the mesh
When mark LUN is in busy condition, object run instruction is added to waiting list.
10. a kind of flash memory system, which is characterized in that including firmware, storage unit and flash memory as claimed in claim 8 or 9
Controller;
The firmware is used to send object run instruction to the flash controller, wherein the object run, which instructs, includes
Target LUN;
The flash controller is used for the current state based on the target LUN, and it is single that the target LUN is sent to the storage
Member;
The storage unit is for executing the object run instruction.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201811511427.2A CN109614049B (en) | 2018-12-11 | 2018-12-11 | Flash memory control method, flash memory controller and flash memory system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201811511427.2A CN109614049B (en) | 2018-12-11 | 2018-12-11 | Flash memory control method, flash memory controller and flash memory system |
Publications (2)
Publication Number | Publication Date |
---|---|
CN109614049A true CN109614049A (en) | 2019-04-12 |
CN109614049B CN109614049B (en) | 2022-03-25 |
Family
ID=66007802
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201811511427.2A Active CN109614049B (en) | 2018-12-11 | 2018-12-11 | Flash memory control method, flash memory controller and flash memory system |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN109614049B (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2021136068A1 (en) * | 2019-12-30 | 2021-07-08 | 中兴通讯股份有限公司 | Resource dispatching method and apparatus, electronic device, and computer readable medium |
CN113157205A (en) * | 2021-02-26 | 2021-07-23 | 西安微电子技术研究所 | Control method of NAND array, controller, electronic device and storage medium |
CN114489488A (en) * | 2021-12-29 | 2022-05-13 | 山东云海国创云计算装备产业创新中心有限公司 | Data read-write method, NAND controller and computer readable storage medium |
CN114546287A (en) * | 2022-02-27 | 2022-05-27 | 山东云海国创云计算装备产业创新中心有限公司 | Method and device for single-channel multi-logic-unit number cross transmission |
Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1445660A (en) * | 2003-04-15 | 2003-10-01 | 威盛电子股份有限公司 | Method for reading out stored data in system storage by display controller |
CN101082891A (en) * | 2007-05-10 | 2007-12-05 | 忆正存储技术(深圳)有限公司 | Paralleling flash memory controller |
JP2008070919A (en) * | 2006-09-12 | 2008-03-27 | Tdk Corp | Memory controller, flash memory system having memory controller, and method for controlling flash memory |
CN102053913A (en) * | 2009-10-30 | 2011-05-11 | 慧荣科技股份有限公司 | Memory device and data access method thereof |
US20130019053A1 (en) * | 2011-07-14 | 2013-01-17 | Vinay Ashok Somanache | Flash controller hardware architecture for flash devices |
CN103136136A (en) * | 2012-11-23 | 2013-06-05 | 香港应用科技研究院有限公司 | Method and system for performing data transmission of flash memory media |
CN103137203A (en) * | 2011-11-21 | 2013-06-05 | 三星电子株式会社 | Nonvolatile memory device, memory system and controller operating method |
CN103282887A (en) * | 2010-12-30 | 2013-09-04 | 桑迪士克科技股份有限公司 | Controller and method for performing background operations |
CN108021516A (en) * | 2017-12-19 | 2018-05-11 | 联芸科技(杭州)有限公司 | The command scheduling management system and method for a kind of parallel memorizing media storage controller |
-
2018
- 2018-12-11 CN CN201811511427.2A patent/CN109614049B/en active Active
Patent Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1445660A (en) * | 2003-04-15 | 2003-10-01 | 威盛电子股份有限公司 | Method for reading out stored data in system storage by display controller |
JP2008070919A (en) * | 2006-09-12 | 2008-03-27 | Tdk Corp | Memory controller, flash memory system having memory controller, and method for controlling flash memory |
CN101082891A (en) * | 2007-05-10 | 2007-12-05 | 忆正存储技术(深圳)有限公司 | Paralleling flash memory controller |
CN102053913A (en) * | 2009-10-30 | 2011-05-11 | 慧荣科技股份有限公司 | Memory device and data access method thereof |
CN103282887A (en) * | 2010-12-30 | 2013-09-04 | 桑迪士克科技股份有限公司 | Controller and method for performing background operations |
US20130019053A1 (en) * | 2011-07-14 | 2013-01-17 | Vinay Ashok Somanache | Flash controller hardware architecture for flash devices |
CN103092782A (en) * | 2011-07-14 | 2013-05-08 | Lsi公司 | Flash controller hardware architecture for flash devices |
CN103137203A (en) * | 2011-11-21 | 2013-06-05 | 三星电子株式会社 | Nonvolatile memory device, memory system and controller operating method |
CN103136136A (en) * | 2012-11-23 | 2013-06-05 | 香港应用科技研究院有限公司 | Method and system for performing data transmission of flash memory media |
CN108021516A (en) * | 2017-12-19 | 2018-05-11 | 联芸科技(杭州)有限公司 | The command scheduling management system and method for a kind of parallel memorizing media storage controller |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2021136068A1 (en) * | 2019-12-30 | 2021-07-08 | 中兴通讯股份有限公司 | Resource dispatching method and apparatus, electronic device, and computer readable medium |
CN113157205A (en) * | 2021-02-26 | 2021-07-23 | 西安微电子技术研究所 | Control method of NAND array, controller, electronic device and storage medium |
CN113157205B (en) * | 2021-02-26 | 2023-03-14 | 西安微电子技术研究所 | Control method of NAND array, controller, electronic device and storage medium |
CN114489488A (en) * | 2021-12-29 | 2022-05-13 | 山东云海国创云计算装备产业创新中心有限公司 | Data read-write method, NAND controller and computer readable storage medium |
CN114546287A (en) * | 2022-02-27 | 2022-05-27 | 山东云海国创云计算装备产业创新中心有限公司 | Method and device for single-channel multi-logic-unit number cross transmission |
Also Published As
Publication number | Publication date |
---|---|
CN109614049B (en) | 2022-03-25 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN109614049A (en) | Flash memory control method, flash controller and flash memory system | |
CN105867844B (en) | A kind of order control method and storage equipment | |
US8661188B2 (en) | Parallel flash memory controller, chip and control method thereof | |
CN102959502B (en) | The method that asynchronous event notification is provided in systems | |
CN1282066C (en) | Method and system for accessing tape devices in computer system | |
CN105243033A (en) | Data processing method and electronic device | |
US20070106843A1 (en) | Management of number of disk groups that can be activated in storage device | |
CN103019971A (en) | Method of quickly responding to trim command, SSD (Solid State Disk) controller and system | |
JP2010079526A5 (en) | ||
US8332480B2 (en) | Storage system | |
JPH0772888B2 (en) | Dynamic polling device, machine processing method, controller and data processing system | |
CN104216796B (en) | A kind of data backup, restoration methods and electronic equipment | |
CN103631849B (en) | data retention management | |
US20180260162A1 (en) | Storage system, storage device, and hard disk drive scheduling method | |
CN100518078C (en) | Network daily-record data management system and method | |
CN106409337B (en) | The control method of eMMC and eMMC controller based on FPGA | |
US20140025979A1 (en) | Interface device and interface method | |
CN112506431B (en) | I/O instruction scheduling method and device based on disk device attributes | |
CN112463064B (en) | I/O instruction management method and device based on double linked list structure | |
US20070083708A1 (en) | Controller of redundant arrays of independent disks and operation method thereof | |
CN104133781A (en) | Network storage equipment and method thereof for improving data access speed | |
KR101135313B1 (en) | Nand flash memory apparatus and method for scheduling requested operations | |
JP4997858B2 (en) | Data recording apparatus and data recording program | |
CN101290602A (en) | Memory management method and system | |
US8819363B2 (en) | Data copying method |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |