CN109522679B - Method and system for generating functional excitation vector based on classification processing - Google Patents
Method and system for generating functional excitation vector based on classification processing Download PDFInfo
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Abstract
The invention discloses a method and a system for generating a functional excitation vector based on classification processing, wherein the method is used for classifying a target digital circuit into a data path class circuit and a control path class circuit according to functional attributes, if the classification result is the data path class circuit, a uniform excitation distribution strategy is adopted to obtain test vectors uniformly and randomly distributed in a verification space, and a specific boundary condition traversal strategy is adopted to obtain test vectors covering a specific boundary condition mode; and if the classification result is that the control path class circuit, a specific functional mode coverage strategy is adopted to obtain a test vector for covering a specific functional mode in the verification space. According to the invention, different excitation generation methods are provided according to different functional attributes, so that high-efficiency random excitation automatic generation can be realized for different types of circuits under the condition of not adding additional constraint and with less manual intervention, and the completeness and the high efficiency of simulation verification are improved.
Description
Technical Field
The invention relates to the field of integrated circuit design verification, in particular to a functional excitation vector generation method and a system based on classification processing, which are used for realizing efficient random excitation automatic generation aiming at a data path class circuit and a control path class circuit.
Background
Analog verification remains the primary verification means in the integrated circuit design verification process. Simulation verification determines if the design is correct by applying stimulus at the system inputs and observing the outputs. Therefore, in order to ensure completeness and efficiency of verification, a method for generating functional incentives is very important. However, the circuits have different functional properties, and using a unified functional stimulus generation method will result in a stimulus generation of low quality, resulting in a low verification efficiency. For a control path class circuit to control a corresponding plurality of functional behaviors in a plurality of functional modes in the circuit, we need to generate stimulus to traverse all the functional modes of the circuit under legal constraints. However, for the data path circuit, which is generally used for data transmission and arithmetic operation, the corresponding verification space is huge, if the excitation is generated by adopting a traversing mode, the verification efficiency is too low, and good verification coverage rate cannot be obtained in a certain time space. It is therefore necessary to generate the stimulus in a classification process based on the functional properties of the circuit. How to realize the generation of the functional excitation vector based on the classification processing is still a technical problem to be solved.
Disclosure of Invention
The invention aims to solve the technical problems: aiming at the problems in the prior art, the invention provides a functional excitation vector generation method and a system based on classification processing, and provides excitation generation methods respectively suitable for different types of circuits according to the functional behaviors of digital circuits with different functional attributes, wherein the methods can realize high-efficiency random excitation automatic generation for different types of circuits under the condition of not adding additional constraint and less manual intervention, improve the completeness and the high efficiency of analog verification, and can be used for the design verification and test stage of digital integrated circuits.
In order to solve the technical problems, the invention adopts the following technical scheme:
a functional excitation vector generation method based on classification processing includes the implementation steps:
1) Classifying the target digital circuit into a data path class circuit and a control path class circuit according to the functional attribute, and jumping to execute the step 2) if the classification result is the data path class circuit; otherwise, jumping to execute the step 3);
2) The test vectors uniformly and randomly distributed in the verification space are obtained by adopting an excitation uniform distribution strategy, the test vectors covering a specific boundary condition mode are obtained by adopting a specific boundary condition traversing strategy, and the test is exited;
3) And obtaining the test vector covering the specific functional mode in the verification space by adopting the specific functional mode covering strategy.
Preferably, the detailed step of obtaining test vectors uniformly and randomly distributed in the verification space using the excitation uniform distribution strategy in step 2) includes: dividing legal value domain space corresponding to each data path port in the target digital circuit, and equally dividing the legal value domain space into a plurality of value domain subspaces according to the preset dividing block number; orthogonal combination is carried out on the value domain subspaces decomposed by the different data path ports, and each combination is combined with legal value domains of all the control path ports to form all verification subspaces; the method comprises the steps of circularly traversing all verification subspaces, and randomly picking a test vector from the verification subspace after each traversal to a certain verification subspace.
Preferably, the detailed step of acquiring the test vector covering the specific boundary condition pattern in step 2) using the specific boundary condition traversal policy includes: acquiring a boundary value set of each data path port in the data path class circuit; respectively carrying out orthogonal combination on boundary values of different data access ports and each legal value of different control access ports to obtain a specific functional mode related to the internal boundary of the verification space; all the specific functional modes of the verification space are traversed, and a test vector is generated for each specific functional mode, so that the test vector covering the specific boundary condition modes is realized.
Preferably, the step of obtaining the test vector covering the specific functional mode in the verification space by using the specific functional mode coverage policy in step 3) includes: and solving legal value fields of all control path ports under normal operation by using a constraint solver aiming at the control path class circuit, and carrying out orthogonal combination on each legal value of different control path ports to obtain a test vector covering a specific functional mode in a verification space.
The invention also provides a method for generating the functional excitation vector based on classification processing, which comprises the following implementation steps:
s1) aiming at a target digital circuit, classifying the target digital circuit into a data path class circuit and a control path class circuit according to the functional attribute, and executing the step S2) in a jumping manner if the classification result is the data path class circuit;
s2) obtaining test vectors uniformly and randomly distributed in a verification space by adopting an excitation uniform distribution strategy, and obtaining test vectors covering a specific boundary condition mode by adopting a specific boundary condition traversing strategy.
Preferably, the detailed step of obtaining test vectors uniformly and randomly distributed in the verification space using the excitation uniform distribution strategy in step S2) includes: dividing legal value domain space corresponding to each data path port in the target digital circuit, and equally dividing the legal value domain space into a plurality of value domain subspaces according to the preset dividing block number; orthogonal combination is carried out on the value domain subspaces decomposed by the different data path ports, and each combination is combined with legal value domains of all the control path ports to form all verification subspaces; the method comprises the steps of circularly traversing all verification subspaces, and randomly picking a test vector from the verification subspace after each traversal to a certain verification subspace.
Preferably, the detailed step of acquiring the test vector covering the specific boundary condition pattern using the specific boundary condition traversal policy in step S2) includes: acquiring a boundary value set of each data path port in the data path class circuit; respectively carrying out orthogonal combination on boundary values of different data access ports and each legal value of different control access ports to obtain a specific functional mode related to the internal boundary of the verification space; all the specific functional modes of the verification space are traversed, and a test vector is generated for each specific functional mode, so that the test vector covering the specific boundary condition modes is realized.
Preferably, step S1) further includes a step of determining for the control path class circuit, and if the classification result is that the control path class circuit, a specific function mode coverage policy is adopted to obtain a test vector covering a specific function mode in the verification space, and the step of obtaining a detailed step of obtaining the test vector covering the specific function mode in the verification space by adopting the specific function mode coverage policy includes: and solving legal value fields of all control path ports under normal operation by using a constraint solver aiming at the control path class circuit, and carrying out orthogonal combination on each legal value of different control path ports to obtain a test vector covering a specific functional mode in a verification space.
The present invention also provides a classification processing-based functional excitation vector generation system, comprising a computer device programmed to perform the steps of the aforementioned classification processing-based functional excitation vector generation method of the present invention, or a computer program programmed to perform the aforementioned classification processing-based functional excitation vector generation method of the present invention is stored in a storage medium of the computer device.
The present invention also provides a storage medium having stored therein a computer program programmed to perform the aforementioned classification processing-based functional excitation vector generation method of the present invention.
Compared with the prior art, the invention has the following advantages: the invention classifies the digital circuits according to the functional attributes, divides the digital circuits into the data path type circuits and the control path type circuits, adopts the thought of dividing into treatment, and respectively adopts a proper functional excitation vector generation method to improve the quality of the functional excitation vector so as to realize complete and efficient verification of the two circuits.
Drawings
Fig. 1 is a basic flow chart of a first embodiment of the present invention.
Fig. 2 is a schematic diagram of the basic principle of the first embodiment of the present invention.
FIG. 3 is a detailed process flow diagram of a first embodiment of the present invention.
Fig. 4 is a basic flow chart of a second embodiment of the present invention.
Detailed Description
Embodiment one:
as shown in fig. 1, 2 and 3, the implementation steps of the method for generating a functional excitation vector based on classification processing in this embodiment include:
1) Classifying the target digital circuit into a data path class circuit and a control path class circuit according to the functional attribute, and jumping to execute the step 2) if the classification result is the data path class circuit; otherwise, jumping to execute the step 3);
2) The test vectors uniformly and randomly distributed in the verification space are obtained by adopting an excitation uniform distribution strategy, the test vectors covering a specific boundary condition mode are obtained by adopting a specific boundary condition traversing strategy, and the test is exited;
3) And obtaining the test vector covering the specific functional mode in the verification space by adopting the specific functional mode covering strategy.
According to the method, the digital circuits are classified into the data path class circuits and the control path class circuits according to the functional attributes, and the data path class circuit excitation generation method and the control path class circuit excitation generation method are respectively designed according to different functional behavior attribute characteristics of the two classes of circuits, so that efficient random excitation automatic generation can be realized for different types of circuits under the condition of not adding additional constraint under the condition of less manual intervention. Fig. 2 is a schematic diagram of the overall structure of the method for generating a functional excitation vector based on classification processing according to the present embodiment. As shown in fig. 2, the method classifies digital circuits according to functional attributes based on numerical constraints of input ports, divides the circuits into a data path class circuit and a control path class circuit, respectively designs a data path class circuit excitation generation method and a control path class circuit excitation generation method according to different functional behavior attribute characteristics of the two classes of circuits, and generates high-quality test vectors under the assistance of a constraint solver and a special boundary value knowledge base so as to realize complete verification of functions of the two types of circuits.
In this embodiment, the data path class circuit is a circuit for performing data transmission and arithmetic operation and has data path ports, which are generally longer in bit width and larger in legal finger space, so the data path class circuit often corresponds to a huge verification space. In the embodiment, aiming at the data path class circuit, an excitation uniform distribution strategy and a specific boundary condition traversing strategy are adopted, so that high-quality directional excitation and random excitation are generated for the data path class circuit, and complete and efficient verification of the data path class circuit is realized.
The test vectors uniformly and randomly distributed in the verification space are obtained by adopting an excitation uniform distribution strategy, and the verification space is decomposed into subspaces, so that the method for uniformly and respectively verifying the subspaces by the random test vectors is ensured, the problem that the random test vectors are not uniform in the verification space is solved, and the random excitation quality of the data path class circuit is improved.
As shown in fig. 3, the detailed step of obtaining test vectors uniformly and randomly distributed in the verification space by using the excitation uniform distribution strategy in step 2) includes: dividing legal value domain space corresponding to each data path port in the target digital circuit, and equally dividing the legal value domain space into a plurality of value domain subspaces according to the preset dividing block number; orthogonal combination is carried out on the value domain subspaces decomposed by the different data path ports, and each combination is combined with legal value domains of all the control path ports to form all verification subspaces; the method comprises the steps of circularly traversing all verification subspaces, and randomly picking a test vector from the verification subspace after each traversal to a certain verification subspace.
The test vector covering the specific functional mode in the verification space can be obtained by adopting a specific functional mode covering strategy, a boundary value set of each data path port can be obtained by adopting human analysis or an expert knowledge base, and different port boundary values can be used for ensuring the mode coverage of the specific boundary condition in a combined traversing mode. The expert knowledge base contains the relevant prior knowledge of the method of the invention. These a priori knowledge support a reasonable decomposition of the value range space of the data path ports and enables a set of boundary values of the data path ports to be derived based on the data type. Meanwhile, for manual intervention in the implementation process of the method of the embodiment, the expert knowledge base records the manual intervention, so that internal priori knowledge is continuously expanded.
As shown in fig. 3, the detailed steps of obtaining test vectors covering a specific boundary condition pattern in step 2) using a specific boundary condition traversal strategy include: acquiring a boundary value set of each data path port in the data path class circuit; respectively carrying out orthogonal combination on boundary values of different data access ports and each legal value of different control access ports to obtain a specific functional mode related to the internal boundary of the verification space; all the specific functional modes of the verification space are traversed, and a test vector is generated for each specific functional mode, so that the test vector covering the specific boundary condition modes is realized.
In this embodiment, the control path type circuit is a control circuit for implementing multiple functional behaviors corresponding to multiple functional modes, and its ports are control path ports, where the control path ports are used for switching different working modes of the control circuit, and the bit width is generally shorter, but each legal value corresponds to one working mode. In this embodiment, a specific functional mode coverage policy is adopted for the control path class circuit, so as to excite the control path class circuit, thereby implementing complete and efficient verification of the control path class circuit.
And obtaining a test vector covering a specific functional mode in the verification space by adopting a specific functional mode covering strategy, obtaining legal value fields of all control path ports under normal operation by using a constraint solver, and carrying out orthogonal combination on each legal value of different control path ports so as to obtain the full coverage of the specific functional mode in the verification space.
As shown in fig. 3, the detailed steps of obtaining test vectors covering a specific functional mode in the verification space using the specific functional mode coverage policy in step 3) include: and solving legal value fields of all control path ports under normal operation by using a constraint solver aiming at the control path class circuit, and carrying out orthogonal combination on each legal value of different control path ports to obtain a test vector covering a specific functional mode in a verification space. The constraint solver may employ an off-the-shelf solver such as zchaff, miniSAT solver, a Z3 solver, etc., or a constraint solver that invokes a constraint logic programming system such as ECLiPSe, as desired.
The present embodiment also provides a classification processing-based functional excitation vector generation system, including a computer device programmed to perform the steps of the foregoing classification processing-based functional excitation vector generation method of the present embodiment, or a computer program programmed to perform the foregoing classification processing-based functional excitation vector generation method of the present embodiment is stored in a storage medium of the computer device. The present embodiment also provides a storage medium having stored therein a computer program programmed to perform the aforementioned classification processing-based function excitation vector generation method of the present embodiment.
Embodiment two:
the present embodiment is basically the same as the first embodiment, and the steps S1) and 1) of the first embodiment correspond to the steps S2) and 2) of the first embodiment, and the main difference is that the determination jump and the processing manner after the classification of the data path class circuit and the control path class circuit in the step S1) of the present embodiment are different.
As shown in fig. 4, the implementation steps of the method for generating a functional excitation vector based on classification processing in this embodiment include:
s1) aiming at a target digital circuit, classifying the target digital circuit into a data path class circuit and a control path class circuit according to the functional attribute, and executing the step S2) in a jumping manner if the classification result is the data path class circuit;
s2) obtaining test vectors uniformly and randomly distributed in a verification space by adopting an excitation uniform distribution strategy, and obtaining test vectors covering a specific boundary condition mode by adopting a specific boundary condition traversing strategy.
In this embodiment, the detailed step of obtaining test vectors uniformly and randomly distributed in the verification space by using the excitation uniform distribution strategy in step S2) includes: dividing legal value domain space corresponding to each data path port in the target digital circuit, and equally dividing the legal value domain space into a plurality of value domain subspaces according to the preset dividing block number; orthogonal combination is carried out on the value domain subspaces decomposed by the different data path ports, and each combination is combined with legal value domains of all the control path ports to form all verification subspaces; the method comprises the steps of circularly traversing all verification subspaces, and randomly picking a test vector from the verification subspace after each traversal to a certain verification subspace.
In this embodiment, the detailed step of obtaining the test vector covering the specific boundary condition pattern in step S2) by using the specific boundary condition traversal policy includes: acquiring a boundary value set of each data path port in the data path class circuit; respectively carrying out orthogonal combination on boundary values of different data access ports and each legal value of different control access ports to obtain a specific functional mode related to the internal boundary of the verification space; all the specific functional modes of the verification space are traversed, and a test vector is generated for each specific functional mode, so that the test vector covering the specific boundary condition modes is realized.
In this embodiment, step S1) further includes a step of determining a control path class circuit, and if the classification result is that the control path class circuit uses a specific functional mode coverage policy to obtain a test vector covering a specific functional mode in the verification space, and the detailed step of using the specific functional mode coverage policy to obtain the test vector covering the specific functional mode in the verification space includes: and solving legal value fields of all control path ports under normal operation by using a constraint solver aiming at the control path class circuit, and carrying out orthogonal combination on each legal value of different control path ports to obtain a test vector covering a specific functional mode in a verification space. In step 1) of the first embodiment, a judgment manner similar to "if … … is … …", and in step S1) of the present embodiment, a judgment manner similar to "if … … is … …", so that the judgment jump and the processing manner after classification into the data path class circuit and the control path class circuit in step S1) of the present embodiment are different.
Also, the present embodiment also provides a classification processing-based functional excitation vector generation system, including a computer device programmed to perform the steps of the foregoing classification processing-based functional excitation vector generation method of the present embodiment, or a computer program programmed to perform the foregoing classification processing-based functional excitation vector generation method of the present embodiment, stored in a storage medium of the computer device. The present embodiment also provides a storage medium having stored therein a computer program programmed to perform the aforementioned classification processing-based function excitation vector generation method of the present embodiment.
The above description is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above examples, and all technical solutions belonging to the concept of the present invention belong to the protection scope of the present invention. It should be noted that modifications and adaptations to the present invention may occur to one skilled in the art without departing from the principles of the present invention and are intended to be within the scope of the present invention.
Claims (6)
1. A functional excitation vector generation method based on classification processing is characterized by comprising the following implementation steps:
1) Classifying the target digital circuit into a data path class circuit and a control path class circuit according to the functional attribute, and jumping to execute the step 2) if the classification result is the data path class circuit; otherwise, jumping to execute the step 3);
2) The test vectors uniformly and randomly distributed in the verification space are obtained by adopting an excitation uniform distribution strategy, the test vectors covering a specific boundary condition mode are obtained by adopting a specific boundary condition traversing strategy, and the test is exited;
3) Obtaining a test vector covering a specific functional mode in the verification space by adopting a specific functional mode covering strategy;
the step 2) of obtaining test vectors uniformly and randomly distributed in the verification space by adopting an excitation uniform distribution strategy comprises the following detailed steps: dividing legal value domain space corresponding to each data path port in the target digital circuit, and equally dividing the legal value domain space into a plurality of value domain subspaces according to the preset dividing block number; orthogonal combination is carried out on the value domain subspaces decomposed by the different data path ports, and each combination is combined with legal value domains of all the control path ports to form all verification subspaces; cycling through all verification subspaces, and randomly selecting a test vector from the verification subspace when each cycle is traversed to a certain verification subspace;
the step 2) of obtaining the test vector covering the specific boundary condition mode by adopting the specific boundary condition traversal strategy comprises the following steps: acquiring a boundary value set of each data path port in the data path class circuit; respectively carrying out orthogonal combination on boundary values of different data access ports and each legal value of different control access ports to obtain a specific functional mode related to the internal boundary of the verification space; all the specific functional modes of the verification space are traversed, and a test vector is generated for each specific functional mode, so that the test vector covering the specific boundary condition modes is realized.
2. The method for generating a functional excitation vector based on classification processing according to claim 1, wherein the step of obtaining a test vector covering a specific functional mode in the verification space using the specific functional mode coverage policy in step 3) comprises: and solving legal value fields of all control path ports under normal operation by using a constraint solver aiming at the control path class circuit, and carrying out orthogonal combination on each legal value of different control path ports to obtain a test vector covering a specific functional mode in a verification space.
3. A functional excitation vector generation method based on classification processing is characterized by comprising the following implementation steps:
s1) aiming at a target digital circuit, classifying the target digital circuit into a data path class circuit and a control path class circuit according to the functional attribute, and executing the step S2) in a jumping manner if the classification result is the data path class circuit;
s2) obtaining test vectors uniformly and randomly distributed in a verification space by adopting an excitation uniform distribution strategy, and obtaining test vectors covering a specific boundary condition mode by adopting a specific boundary condition traversing strategy;
the step S2) of obtaining test vectors uniformly and randomly distributed in the verification space by adopting an excitation uniform distribution strategy comprises the following detailed steps: dividing legal value domain space corresponding to each data path port in the target digital circuit, and equally dividing the legal value domain space into a plurality of value domain subspaces according to the preset dividing block number; orthogonal combination is carried out on the value domain subspaces decomposed by the different data path ports, and each combination is combined with legal value domains of all the control path ports to form all verification subspaces; cycling through all verification subspaces, and randomly selecting a test vector from the verification subspace when each cycle is traversed to a certain verification subspace;
the step S2) of acquiring the test vector covering the specific boundary condition mode by adopting the specific boundary condition traversal strategy comprises the following steps: acquiring a boundary value set of each data path port in the data path class circuit; respectively carrying out orthogonal combination on boundary values of different data access ports and each legal value of different control access ports to obtain a specific functional mode related to the internal boundary of the verification space; all the specific functional modes of the verification space are traversed, and a test vector is generated for each specific functional mode, so that the test vector covering the specific boundary condition modes is realized.
4. A method for generating a functional excitation vector based on classification processing according to claim 3, wherein step S1) further comprises a step of determining for the control path class circuit, and if the classification result is that the control path class circuit, a specific functional mode coverage policy is used to obtain a test vector covering a specific functional mode in the verification space, and the step of using the specific functional mode coverage policy to obtain a detailed test vector covering the specific functional mode in the verification space comprises: and solving legal value fields of all control path ports under normal operation by using a constraint solver aiming at the control path class circuit, and carrying out orthogonal combination on each legal value of different control path ports to obtain a test vector covering a specific functional mode in a verification space.
5. A classification processing-based functional stimulus vector generation system comprising a computer device characterized in that: the computer device is programmed to perform the steps of the classification process based functional excitation vector generation method of any one of claims 1 to 4 or a computer program programmed to perform the classification process based functional excitation vector generation method of any one of claims 1 to 4 is stored in a storage medium of the computer device.
6. A storage medium, characterized by: the storage medium stores therein a computer program programmed to execute the classification processing-based function excitation vector generation method according to any one of claims 1 to 4.
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| CN102879731A (en) * | 2012-09-26 | 2013-01-16 | 清华大学 | Digital integrated circuit test method |
| CN106777720A (en) * | 2016-12-23 | 2017-05-31 | 深圳市国微电子有限公司 | Circuit verification method and device |
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| CN102879731A (en) * | 2012-09-26 | 2013-01-16 | 清华大学 | Digital integrated circuit test method |
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