CN107315863B

CN107315863B - Layout optimization method and device, terminal and storage medium

Info

Publication number: CN107315863B
Application number: CN201710439297.5A
Authority: CN
Inventors: 谭宇泉; 陈燕生; 温长清
Original assignee: Shenzhen State Micro Electronics Co Ltd
Current assignee: Shenzhen State Micro Electronics Co Ltd
Priority date: 2017-06-12
Filing date: 2017-06-12
Publication date: 2021-01-08
Anticipated expiration: 2037-06-12
Also published as: CN107315863A

Abstract

The embodiment of the invention provides a layout optimization method and device, a terminal and a storage medium, wherein a critical path is obtained by analyzing the existing design netlist, and after copying examples on the critical path, the examples are inserted into a specific position, so that the loose value between the examples on the critical path can be reduced, the layout effect of the design netlist is improved, the existing design netlist is optimized to a certain extent, and the use experience of a user is enhanced.

Description

Layout optimization method and device, terminal and storage medium

Technical Field

The present invention relates to the Field of FPGA (Field-Programmable Gate Array), and in particular, to a layout optimization method and apparatus, a terminal, and a storage medium.

Background

The FPGA chip has the advantages of strong functionality, flexibility and the like, has huge use potential in the electronic market, has strict functional requirements on a chip hardware framework, and has higher performance requirements on electronic design automation software matched with the chip hardware framework. However, since the development and development of the programmable chip in China are late, the related leading-edge technology and products are monopolized abroad at present, so that the development in the field is in a passive state, and the development of the domestic independent research and development electronic market is not facilitated.

The software for the programmable chip is supported based on EDA (Electronic Design Automation) technology, and may be referred to as EDA software. The EDA software mainly analyzes the application design obtained by a user by using a hardware description language, then carries out further logic synthesis, then carries out layout and wiring, and finally successfully generates a bit stream to be downloaded to a chip to realize the user function.

The layout and the wiring are the most important processing parts of the EDA software, and determine the number of logic units and the routing mode used by a user for designing a chip and meet the design timing sequence. This is also the primary quality measure for EDA software performance. The layout and wiring mainly comprises the steps that logic units used by user design are reasonably placed according to process requirements, user time sequence requirements, constraint requirements and the like, then wiring of connecting lines among the logic units is determined, and the layout and wiring need to meet the functional requirements and the time sequence requirements of users on the design as far as possible.

Disclosure of Invention

The embodiment of the invention provides a layout optimization method and device, a terminal and a storage medium, which are used for optimizing an existing design netlist to a certain extent.

In one aspect, a layout optimization method is provided, including:

analyzing the netlist of the design to be optimized to obtain a critical path;

traversing the examples on the key path, and determining the examples to be copied;

calculating the insertion position of the example to be copied according to a preset algorithm;

and copying the example to be copied and inserting the example to be copied into the corresponding insertion position to generate the optimized design netlist.

Further, analyzing the netlist of the design to be optimized, and acquiring the critical path includes:

calculating the routing delay of each path in the design netlist to be optimized;

determining a worst relaxation value according to the delay value of the design netlist to be optimized;

correcting the worst relaxation value, and determining a screening threshold value;

and taking the path with the routing delay larger than the screening threshold value as a critical path.

Further, calculating the insertion position of the to-be-copied instance according to a preset algorithm includes:

determining a boundary box according to an end point example driven by an example to be copied;

dividing the boundary box to determine a sub-box;

and taking the preset position of the terminal instance in the sub-box as the insertion position of the instance to be copied.

Further, the step of inserting the copied instances into corresponding insertion positions after copying the instances to be copied to generate the optimized design netlist includes:

copying the instance to be copied to generate a copied instance;

inserting the replicated instance into a corresponding insertion location;

acquiring a driving example of an example to be copied;

a connection driver instance, a replication instance, and an endpoint instance.

Further, the method also comprises the following steps:

performing overall time sequence analysis on the netlist to be optimized, and outputting a time sequence analysis result before optimization;

performing overall time sequence analysis on the optimized design netlist, and outputting an optimized time sequence analysis result;

judging whether the time sequence analysis result after optimization is superior to the time sequence analysis result before optimization;

if yes, outputting an optimized design netlist;

and if not, returning the optimized design netlist to the design netlist to be optimized.

In one aspect, the present invention also provides a layout optimization apparatus, including:

the obtaining module is used for analyzing the design netlist to be optimized and obtaining a critical path;

the determining module is used for traversing the examples on the key path and determining the examples to be copied;

the calculation module is used for calculating the insertion position of the example to be copied according to a preset algorithm;

and the optimization module is used for inserting the copied instances into corresponding insertion positions after copying the instances to be copied to generate an optimized design netlist.

Further, the obtaining module is configured to:

Further, the calculation module is configured to:

dividing the boundary box to determine a sub-box;

Further, the optimization module is configured to:

copying the instance to be copied to generate a copied instance;

inserting the replicated instance into a corresponding insertion location;

acquiring a driving example of an example to be copied;

a connection driver instance, a replication instance, and an endpoint instance.

Further, the optimization module is further configured to:

if yes, outputting an optimized design netlist;

In one aspect, a terminal is provided, including: the layout optimization system comprises a processor, a memory and a layout optimization program stored on the memory and capable of running on the processor, wherein the layout optimization program realizes the steps of the layout optimization method provided by the invention when being executed by the processor.

In another aspect, a computer-readable storage medium is provided, where a layout optimization program is stored on the computer-readable storage medium, and when executed, the layout optimization program implements the steps of the layout optimization method provided by the present invention.

The embodiment of the invention has the following beneficial effects:

Drawings

Fig. 1 is a block diagram of a layout optimization apparatus according to a first embodiment of the present invention;

FIG. 2 is a flowchart of a layout optimization method according to a first embodiment of the present invention;

fig. 3 is a block diagram of a terminal according to a first embodiment of the present invention;

FIG. 4 is a flowchart of a layout optimization method according to a second embodiment of the present invention;

FIG. 5 is a comparison graph of layout optimization results according to a second embodiment of the present invention;

FIG. 6 is a schematic diagram of the subdivision of the sub-box according to a second embodiment of the present invention;

FIG. 7 is a diagram illustrating an effect of an example copy insertion according to a second embodiment of the present invention;

FIG. 8 is a flowchart of a layout optimization method according to a third embodiment of the present invention;

FIG. 9 is a diagram illustrating a traversal direction of a critical path according to a third embodiment of the present invention;

FIG. 10 is a schematic diagram of the subdivision of the sub-box provided by a third embodiment of the present invention;

FIG. 11 is a first partial diagram of an original design netlist according to a third embodiment of the present invention;

FIG. 12 is a first partial schematic diagram of a new design netlist according to a third embodiment of the present invention;

fig. 13 is a schematic diagram of a copy example insertion position according to a third embodiment of the present invention;

FIG. 14 is a second partial diagram of an original design netlist according to a third embodiment of the present invention;

FIG. 15 is a second partial diagram of a newly designed netlist according to a third embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The invention will now be further explained by means of embodiments in conjunction with the accompanying drawings.

The first embodiment:

fig. 1 is a block diagram of a layout optimization apparatus according to a first embodiment of the present invention, and as can be seen from fig. 1, the layout optimization apparatus according to this embodiment includes:

the obtaining module 11 is configured to analyze the to-be-optimized design netlist and obtain a critical path;

the determining module 12 is configured to traverse the instance on the critical path and determine the instance to be copied;

the calculation module 13 is used for calculating the insertion position of the example to be copied according to a preset algorithm;

and the optimization module 14 is configured to copy the to-be-copied instance and insert the to-be-copied instance into the corresponding insertion position to generate an optimized design netlist.

In some embodiments, the obtaining module 11 in the above embodiments is configured to:

In some embodiments, the calculation module 13 in the above embodiments is configured to:

dividing the boundary box to determine a sub-box;

In some embodiments, the optimization module 14 in the above embodiments is configured to:

copying the instance to be copied to generate a copied instance;

inserting the replicated instance into a corresponding insertion location;

acquiring a driving example of an example to be copied;

a connection driver instance, a replication instance, and an endpoint instance.

In some embodiments, the optimization module 14 in the above embodiments is further configured to:

if yes, outputting an optimized design netlist;

Fig. 2 is a flowchart of a layout optimization method according to a first embodiment of the present invention, and as can be seen from fig. 2, the layout optimization method according to this embodiment includes:

s201: analyzing the netlist of the design to be optimized to obtain a critical path;

s202: traversing the examples on the key path, and determining the examples to be copied;

s203: calculating the insertion position of the example to be copied according to a preset algorithm;

s204: and copying the example to be copied and inserting the example to be copied into the corresponding insertion position to generate the optimized design netlist.

In some embodiments, analyzing the netlist to be optimized in the above embodiments, and acquiring the critical path includes:

In some embodiments, the calculating the insertion position of the to-be-copied instance according to the preset algorithm in the above embodiments includes:

dividing the boundary box to determine a sub-box;

In some embodiments, the inserting the copied instances into the corresponding insertion positions after copying the instances to be copied and generating the optimized design netlist in the above embodiments includes:

copying the instance to be copied to generate a copied instance;

inserting the replicated instance into a corresponding insertion location;

acquiring a driving example of an example to be copied;

a connection driver instance, a replication instance, and an endpoint instance.

In some embodiments, the layout optimization method in the above embodiments further includes:

if yes, outputting an optimized design netlist;

Fig. 3 is a block diagram of a terminal according to a first embodiment of the present invention; as can be seen from fig. 3, the terminal provided in this embodiment includes: a processor 31, a memory 32, a communication bus 33, and a layout optimization program stored on the memory 32 and operable on the processor 31, the layout optimization program, when executed by the processor, implementing the steps of the layout optimization method provided by the present invention; wherein the content of the first and second substances,

the communication bus 33 is used for realizing connection communication between the processor 31 and the memory 32;

the processor 31 is adapted to execute the program stored in the memory 32 to implement the steps of:

analyzing the netlist of the design to be optimized to obtain a critical path;

In some embodiments, the processor 31 is configured to execute a program stored in the memory 32 to perform the following steps:

dividing the boundary box to determine a sub-box;

copying the instance to be copied to generate a copied instance;

inserting the replicated instance into a corresponding insertion location;

acquiring a driving example of an example to be copied;

a connection driver instance, a replication instance, and an endpoint instance.

if yes, outputting an optimized design netlist;

In some embodiments, the present invention also provides a computer readable storage medium storing one or more programs, the one or more programs being executed to implement the steps of:

analyzing the netlist of the design to be optimized to obtain a critical path;

In some embodiments, one or more of the procedures in the above embodiments are performed to implement the steps of:

dividing the boundary box to determine a sub-box;

copying the instance to be copied to generate a copied instance;

inserting the replicated instance into a corresponding insertion location;

acquiring a driving example of an example to be copied;

a connection driver instance, a replication instance, and an endpoint instance.

if yes, outputting an optimized design netlist;

The present invention will now be further explained with reference to specific application scenarios.

The second example:

the example is directed to a layout algorithm, and based on the currently mainstream layout algorithm, a logic unit used for design is abstracted into instance (example).

As shown in (1) in fig. 5, when an output of an instance is connected to a plurality of instances, and the locations of the latter instances are distributed far away, after the placement, the optimal location of a is generally in the middle of them, and then e and c may be far away from a, which may result in large trace delay and poor timing, for such a path, this application is referred to as critical paths.

Aiming at the situation, under the premise that the original logic is not changed, the middle a is copied and inserted into the design netlist, and the middle a is reasonably placed through time sequence driving, so that as shown in (2) in fig. 5, the actual distances from a to c and e are shorter, and the routing from b and d to a is more direct, so that the time sequence is effectively improved.

Specifically, in the present embodiment, aiming at the fact that the layout and wiring module of the EDA software needs to meet the requirement of the user for designing the time sequence as much as possible, an instance replication method is provided in the middle of the mainstream layout and wiring process, so as to improve the original layout result, facilitate the wiring processing in the later stage, and further improve the time sequence as much as possible, thereby achieving the purpose of optimizing the time sequence designed by the user.

As shown in fig. 4, the layout optimization method provided in this embodiment includes the following steps:

s401: traversing the example;

in this embodiment, instances on the critical path are sorted according to the criteria of the size of the slack value and the height of the pin level. All the critical paths are traversed from small to large according to the slope value, and for instances on the same critical path, the traversal processing is carried out from low to high according to the criticality level of the instances.

S402: bounding box;

when critical paths and non-critical paths are included in a net (network) driven by a pin (pin) in a single instance or group (a group formed by multiple instances), a bounding box is used to measure whether netlist connection can be changed by the embodiment, and the critical paths are reduced. The size of the bounding box is determined by the positions of all the loaders (end point instances) on the critical net (meaning the same as the critical path) driven by the instance or group. The size of the bounding box is judged by introducing a threshold value to analyze: when the bounding box is larger than the threshold, it indicates that the distribution range of all loaders on the cognitive net driven by the instance or group is larger, and then the optimization processing of the scheme is performed.

S403: replicating the instance;

according to the size of a bounding box, multiple copies of instance driving the critical nets are made and reinserted into the design netlist, and different loads on the critical nets are driven by different copies according to timing requirements. In practical applications, not all the groups on the critical path can be copied, in this embodiment, only the group with the proper size is copied, and the group with the too large size is not suitable for being copied.

In the process of copying the instance and updating the design netlist, an interface for rewiring is reserved in advance, and the purpose of improving the time sequence is achieved by changing the connection relation of certain specific instances of the design netlist.

S404: dividing regions;

the bounding box is divided into regions, the size of the divided region is a constant value, and theoretically, the divided region is not more than 1/2 of the bounding box, but the value is finally determined by analyzing a large number of designs. The divided areas can be called cells (sub-boxes), each cell is fixed in size, and the location coordinates on the cognitive net can be used to index into which cell ranges the instances are located, as shown in fig. 6.

In fig. 6, the thickened traces are critical traces, the area larger than the distribution range of the loaders of instance a is a bounding box, and the shaded square is the area dividing the bounding box. The copied instance needs to find a position which can enable the time sequence to reach the optimal time sequence within the range of the divided area. The Cell box cannot be too small theoretically, so that the situation that the duplicate instance cannot be placed due to the fact that the planned area is too crowded is avoided. In some cases, adjacent cell boxes may be merged, and the instance is copied to find more candidate locations.

S405: placement of duplicate instances;

the location of the copied instance is limited to the divided area cell, and the placement process is similar to the process of placing the instance in the detailed layout, as shown in FIG. 7: a solid node is a new instance (i.e., a replicated instance) by replicating instance a and placing it properly. The addition of the new instance changes the routing condition between the netlists, and compared with the netlist shown in FIG. 6, routing between the instances is more direct and shorter, so that critical paths existing in the original netlist are effectively eliminated.

S406: timing judgment standards;

after the duplicate instance is added to the netlist and placed in the best position, it is determined whether the timing has improved. If the timing is not improved after processing, the results need to be backed off.

The method and the device have the advantages that the original design netlist is changed, the layout result is optimized, the post-stage wiring processing is facilitated, the time sequence of the final design can be effectively improved, and the functional requirements and the time sequence requirements of a user on the design are met.

The third embodiment:

as shown in fig. 8, the layout optimization method provided in this embodiment includes the following steps:

s801: collecting the instances;

and traversing the design netlist, and collecting instance with the slack value smaller than worst slack value and margin into a container. Wherein, worst slot is determined by the original design netlist, and margin is a constant value.

S802: sequencing by using instances;

the ordering rule is as follows:

1. and sequencing the instances according to the gradual increase of the slack value, aiming at arranging the instances on the same critical path adjacently and preferentially processing the critical path with the smaller slack value.

2. And for instance on the same key path, sequencing according to the level of critical pins of the instance from low to high, aiming at preferentially processing instances with lower pin level and improving optimization efficiency.

S808: traversing instances;

after sorting the instances of the container, traversing the instances according to the traversing direction shown in fig. 9.

S804: acquiring a bounding box;

the Bounding box is determined by the loaders locations on all the critical nets driven by instance. The specific operation is as follows:

1. judging whether the loader on the critical net driven by the instance has been processed or not;

2. respectively calculating the Euclidean distance between each loader and the driver, and if the distance value is less than 4, the loader does not process the Euclidean distance;

3. then calculating and then counting the number of loaders to be processed. The processing of this scheme is performed only when the number is more than 1.

Through traversing the loaders, the floorplan coordinates (x, y) are obtained, and then a bounding box is obtained through Add operation of BBox class.

S805: acquiring a cell box;

in order to keep the adjacent loaders in the same Cell box as much as possible, reduce the number of copies required, and prevent overcrowding in the box, the size of the Cell box is specified as 1/4 or 1/9 of the bounding box. A plurality of equivalent cell boxes are obtained by dividing the bounding box, and (x _ min, x _ max, y _ min, y _ max) and index information of each cell box are recorded. As shown in fig. 10, a, b and c are critical loads, assuming that the width and height of each cell box are width and height, respectively, and the coordinates of the critical loads to be processed are (x, y), the index of the cell box where the node is located is (x/width, y/height). According to the method, which cell boxes the critical loaders are respectively located in can be calculated, the cell boxes and the critical loaders located in the box form a mapping relation, and meanwhile, the driver pins of the original instance a and the critical loaders pins of each cell box form a mapping relation.

S806: replicating instance;

traversing each cell box with critical loaders, each box will be allocated a duplicate instance, and this duplicate instance will serve as a new driver to drive all critical loaders in the same cell box. The copied instance is inserted into the existing netlist without changing the original logic and is placed first. The specific operation is as follows:

as shown in FIG. 11, if two copies of instance a are currently copied, namely instance a 'and a ", and inserted into the netlist, instance c and instance d are driven by a'; a "drives instance e. The above examples are critical insts, which are connected by critical pins.

If instance a' is inserted and placed:

1. drivers for original instance a are obtained by collecting input pins for instance a itself.

2. Connecting drivers and instance a' of original instance a.

3. Disconnect instances c and d from a and create a new net to connect a' with instances c and d.

4. Place a' in a legal location.

A new netlist is obtained as shown in fig. 12.

And in the processing process, the copied new instance is stored in a container, so that the post-processing is facilitated.

S807: placing the replicated instances;

the procedure of placing the duplicate instance is similar to the detailed layout, and mainly comprises:

(1) only selecting the coordinate average value of critical loaders in the same cell box as a candidate seed;

(2) the copy instance placeable area is limited within the cell box;

(3) in the cell box range, the copy instance is tried on and around the candidate seed;

(4) based on the time sequence analysis, copying the instance will find the best placement position in time sequence. However, if the cell box placement space is too crowded, the instance on the non-critical path on the candidate location needs to be pushed away, and the instance is copied for placement.

(5) And placing the distances of the squeezed non-critical paths on the premise of ensuring that the slack value of the distances cannot be worsened at present.

As shown in fig. 13, in the Cell box, the empty nodes are both critical loaders (key end points), the solid nodes are candidate seeds, and the shaded nodes represent non-critical loaders (non-key end points). Replicating instances will spread out from the candidate seed looking for placement locations. When the position at the blue node must be selected, the non-critical loader is moved to another position.

S808: analyzing the time sequence;

the time sequence analysis is the only standard for verifying the processing effect of the embodiment. Timing analysis is embodied in three aspects:

1. in the process of placing the copied instance, in order to facilitate time sequence analysis, the original instance is mainly placed in a trial mode, when the position with the best time sequence is found, the copied instance is placed on the position, and the original instance is restored to the original position. The time series analysis was as follows:

for the designed netlist shown in fig. 14, if the instance a of fig. 14 is subjected to replication processing, where a and b are in the critical path, a new netlist shown in fig. 15 is obtained, and in fig. 15, the instance a is tried on the a' position, and then analysis is performed;

and connecting the external delay value and the internal delay value of the instance in three segments to obtain a new slack value of the instance.

2. If the process fails, the current results need to be rolled back.

3. And after all the key paths are processed, performing overall time sequence analysis to judge whether the result is improved.

S809: result rollback;

the resulting rollback operation is primarily to remove duplicate instances from the existing netlist. The rollback operation is as follows:

1. each duplicate instance is traversed and disconnected from other instances of the netlist.

2. All critical loaders are restored to the original connection.

In summary, the implementation of the embodiment of the present invention has at least the following advantages:

As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of a hardware embodiment, a software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, optical storage, and the like) having computer-usable program code embodied therein.

The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

The above embodiments are only examples of the present invention, and are not intended to limit the present invention in any way, and any simple modification, equivalent change, combination or modification made by the technical essence of the present invention to the above embodiments still fall within the protection scope of the technical solution of the present invention.

Claims

1. A layout optimization method, comprising:

analyzing the netlist of the design to be optimized to obtain a critical path;

copying the example to be copied and inserting the copied example into a corresponding insertion position to generate an optimized design netlist;

the calculating the insertion position of the instance to be copied according to a preset algorithm comprises:

determining a boundary box according to the terminal point example driven by the example to be copied;

dividing the boundary box, and determining sub-boxes, wherein the size of each sub-box is fixed;

and taking the preset position of the terminal instance in the sub-box as the insertion position of the to-be-copied instance.

2. The layout optimization method of claim 1, wherein the analyzing the to-be-optimized design netlist to obtain the critical path comprises:

determining a worst relaxation value according to the delay value of the netlist to be optimized;

and taking the path with the routing delay larger than the screening threshold value as the critical path.

3. The layout optimization method of claim 1, wherein the inserting the copied instances into the corresponding inserting positions after copying, and generating the optimized design netlist comprises:

copying the example to be copied to generate a copied example;

inserting the replicated instance into a corresponding insertion location;

acquiring a driving example of the example to be copied;

a connection driver instance, a replication instance, and an endpoint instance.

4. The layout optimization method according to any one of claims 1 to 3, further comprising:

performing overall time sequence analysis on the netlist of the design to be optimized, and outputting a time sequence analysis result before optimization;

judging whether the optimized time sequence analysis result is superior to the time sequence analysis result before optimization;

if so, outputting the optimized design netlist;

5. A layout optimization apparatus comprising:

the optimization module is used for copying the example to be copied and inserting the copied example into a corresponding insertion position to generate an optimized design netlist;

the calculation module is configured to:

6. The layout optimization apparatus of claim 5, wherein the acquisition module is to:

7. The layout optimization apparatus of claim 5, wherein the optimization module is to:

copying the example to be copied to generate a copied example;

inserting the replicated instance into a corresponding insertion location;

acquiring a driving example of the example to be copied;

a connection driver instance, a replication instance, and an endpoint instance.

8. The layout optimization apparatus of any one of claims 5 to 7, wherein the optimization module is further to:

if so, outputting the optimized design netlist;

9. A terminal, comprising: a processor, a memory and a layout optimization program stored on the memory and executable on the processor, the layout optimization program when executed by the processor implementing the steps of the layout optimization method according to any one of claims 1 to 4.

10. A computer-readable storage medium, having stored thereon a layout optimization program that, when executed, performs the steps of the layout optimization method of any one of claims 1 to 4.