CN109491949B - Zynq-based dynamic reconfigurable framework and method - Google Patents

Zynq-based dynamic reconfigurable framework and method Download PDF

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CN109491949B
CN109491949B CN201811427524.3A CN201811427524A CN109491949B CN 109491949 B CN109491949 B CN 109491949B CN 201811427524 A CN201811427524 A CN 201811427524A CN 109491949 B CN109491949 B CN 109491949B
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zynq
interface
external equipment
embedded system
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CN109491949A (en
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张展
左德承
刘宏伟
董剑
薛利兴
冯懿
尚江卫
曹瑞
温东新
罗丹彦
舒燕君
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Harbin Institute of Technology
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    • G06—COMPUTING; CALCULATING OR COUNTING
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    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
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    • G06F13/4068—Electrical coupling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
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Abstract

A Zynq-based dynamic reconfigurable framework and a Zynq-based dynamic reconfigurable method relate to the technical field of embedded system application. The invention aims to solve the problems that the existing embedded system has constraints on volume and power consumption and is not rich in hardware resources. The invention is based on Zynq and can provide the functions of computing task reconstruction and I/O interface reconstruction. The function of the dynamic area applies a local dynamic reconfigurable technology, the task calculation function and the I/O interface logic matched with the access equipment are reconfigured according to the requirement, and the resource utilization rate of the FPGA is improved. Finally, the purposes of improving the efficiency of the system computing task, providing more types of I/O interfaces and improving the expandability of the system are achieved.

Description

Zynq-based dynamic reconfigurable framework and method
Technical Field
The invention belongs to the technical field of embedded system application.
Background
In recent years, with the development of low power consumption devices, embedded systems have become hot spots for applications and research. As the application environment becomes more complex, people put higher demands on the system, and the system is expected to process the computing task more efficiently and have more flexible hardware configuration mode and peripheral interface. However, embedded systems are often not rich enough in hardware resources and have clear constraints on size and power consumption.
Disclosure of Invention
The invention provides a dynamic reconfigurable frame and a method based on Zynq, aiming at solving the problems that the existing embedded system has constraints on volume and power consumption and is not rich in hardware resources.
The Zynq-based dynamic reconfigurable framework comprises Zynq and an I/O conversion board, wherein the Zynq is in data communication with an embedded system through a PCIe bus, the Zynq is connected with external equipment through the I/O conversion board,
zynq comprises an I/O interface logic reconstruction unit and a calculation task reconstruction unit,
the I/O interface logic reconfiguration unit comprises the following modules:
a module for detecting a currently accessed I/O converter board type using the Zynq processor system,
a module for obtaining external device information by referring to the stored information of the I/O conversion board,
a module for reconfiguring the dynamic reconfigurable area of the I/O interface in Zynq according to the external device information, so that the I/O interface logic of Zynq is matched with the external device to complete the I/O interface logic reconfiguration;
the calculation task reconstruction unit comprises the following modules:
and the module is used for reconfiguring the Zynq calculation task area according to the task requirement of the embedded system and finishing the logic reconstruction of the calculation task area.
The I/O interface logic reconfiguration unit further comprises means for issuing a prepare communication notification to the embedded system.
The I/O conversion board comprises a memory, a conversion chip and an in-place signal detection module; the conversion chip is used for converting the external equipment information into signals suitable for being processed by programmable logic in Zynq, the bit signal detection module is used for detecting in-place signals, the in-place signals are used for judging whether the external equipment is accessed to an I/O interface of Zynq currently, and the memory is used for storing the type of the I/O conversion board and the external equipment information.
The Zynq-based dynamic reconfigurable method comprises an I/O interface logic reconfiguration part and a calculation task reconfiguration part,
the I/O interface logic reconfiguration portion includes the steps of:
the external equipment is connected to the I/O interface of Zynq through the I/O conversion board,
the processor system utilizing Zynq detects the type of I/O switch board currently accessed,
obtains the external device information by referring to the stored information of the I/O conversion board,
the Zynq reconfigures the dynamic reconfigurable area of the I/O interface according to the external equipment information, so that the I/O interface logic of the Zynq is matched with the external equipment to complete I/O interface logic reconfiguration;
the calculation task reconstruction part comprises the following steps:
zynq establishes data communication with the embedded system through the PCIe bus,
and the embedded system reconfigures the Zynq calculation task area according to task needs to complete the logic reconfiguration of the calculation task area.
After the I/O interface logic reconfiguration is completed, Zynq sends a communication preparation notice to the embedded system.
The I/O conversion board is used for converting external equipment information into signals suitable for being processed by programmable logic in Zynq, detecting in-place signals and storing the type of the I/O conversion board and the external equipment information, and the in-place signals are used for judging whether external equipment is accessed to an I/O interface of Zynq currently.
The Zynq-based dynamic reconfigurable framework and the Zynq-based dynamic reconfigurable method are designed by combining the dynamic reconfigurable technology of an FPGA (Field Programmable Gate Array), the functions of computing task reconfiguration and I/O interface reconfiguration can be provided, and PL in Zynq can provide FPGA hardware realization of computing tasks for an embedded system, so that the processing of computing tasks is accelerated, the efficiency of the system is improved, and the overall power consumption is reduced. Hardware implementation of the computing task can assist the embedded system to process the task, so that computing resources are provided, and meanwhile, the burden of the embedded system is relieved. The function of the dynamic area applies a local dynamic reconfigurable technology, the task calculation function and the I/O interface logic matched with the access equipment are reconfigured according to the requirement, and the resource utilization rate of the FPGA is improved. Finally, the purposes of improving the efficiency of the system computing task, providing more types of I/O interfaces and improving the expandability of the system are achieved.
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Fig. 1 is a schematic structural diagram of a dynamic reconfigurable framework based on Zynq according to a first embodiment;
FIG. 2 is a flow chart of I/O interface reconfiguration;
FIG. 3 is a schematic diagram of a dynamic area structure of an I/O interface;
FIG. 4 is a schematic structural diagram of an I/O interface converter board;
FIG. 5 is a schematic view of the connection structure of the I/O interface and Zynq;
FIG. 6 is a diagram illustrating a dynamic region structure of a computing task;
FIG. 7 is a schematic diagram of I/O interface reconfiguration logic;
FIG. 8 is a flowchart of an I/O dynamic reconfigurable interface section according to a second embodiment;
fig. 9 is a data transmission flowchart.
Detailed Description
The first embodiment is as follows: as shown in fig. 1, the dynamic reconfigurable frame based on Zynq mainly includes a memory, a power supply, a memory card, an I/O board (i.e., an I/O conversion board), and a Zynq chip, where Zynq performs data communication with an embedded system through a PCIe bus, and Zynq establishes connection with an external device through the I/O conversion board.
Zynq comprises an I/O interface logic reconstruction unit and a calculation task reconstruction unit,
the I/O interface logic reconfiguration unit comprises the following modules:
the device comprises a module for detecting the type of the currently accessed I/O conversion board by utilizing the Zynq processor system, a module for obtaining external equipment information by inquiring the storage information of the I/O conversion board, a module for reconfiguring the dynamic reconfigurable area of the I/O interface in the Zynq according to the external equipment information to ensure that the logic of the I/O interface of the Zynq is matched with the external equipment to complete the logic reconfiguration of the I/O interface, and a module for sending a communication preparation notice to the embedded system
The calculation task reconstruction unit comprises the following modules:
and the module is used for reconfiguring the Zynq calculation task area according to the task requirement of the embedded system and finishing the logic reconstruction of the calculation task area.
The I/O conversion board comprises a memory, a conversion chip and an in-place signal detection module; the conversion chip is used for converting the external equipment information into signals suitable for being processed by programmable logic in Zynq, the bit signal detection module is used for detecting in-place signals, the in-place signals are used for judging whether the external equipment is accessed to an I/O interface of Zynq currently, and the memory is used for storing the type of the I/O conversion board and the external equipment information.
Zynq is a heterogeneous multiprocessor system structure which is provided by Xilinx (Seign) company and adopts ARM + FPGA, takes an ARM processor as a core, has the programmability of the FPGA, and has the high performance and low power consumption of ASIC. The Zynq chip structure is composed of two parts, one is a Processor System (PS), and the other is Programmable Logic (PL). An ARM processor is arranged in the PS part, and can run a linux operating system and a bare computer program without the operating system; PL is FPGA programmable logic, which enables custom hardware design as needed. An Advanced eXtensible Interface (AXI) connection mode of an industrial standard is used between the ARM and the FPGA in the Zynq, so that the Zynq internal communication has the characteristics of high bandwidth and low delay.
(1) And (4) designing internal interconnection.
In the Zynq dynamic reconfigurable system, all modules are connected through AXI interconnection IP cores, a data communication interface from a plurality of AXI master devices to a plurality of AXI slave devices can be provided, and the AXI interconnection IP cores are adopted in a hardware platform, so that the connection among all modules is easier, the module structure is clear, and the hardware design and implementation are easy. Each master device can freely control each slave device in an address access mode. The AXI interconnection IP core is used for connecting the internal modules, and at most 16 master devices and 16 slave devices can be supported. Each device has an exclusive data transmission signal inside the IP core, so that each master device and each slave device can ensure that each device has an exclusive bandwidth in the actual data transmission process. Therefore, high-speed data transmission rate can be ensured, and the flexibility of connection among various devices is improved. In the dynamic reconfigurable system, each master device mounted on the same AXI interconnect IP core can control other slave devices.
Two sub-protocols in the AXI protocol are used in the dynamic reconfigurable framework, namely an AXI4 interface protocol and an AXI4-Lite interface protocol. The AXI4 interface protocol is the highest performance data transmission protocol, supports the highest 256-bit data transmission, and is generally used in application scenarios requiring high-speed data transmission, such as the access of a main device to a memory. The AXI4-Lite interface protocol is a simplified version of the AXI interface protocol, does not support transmission of a large amount of data, is only suitable for single communication in a register mapping mode, and is generally applied to register access and data transmission of low-speed equipment due to low data transmission efficiency.
(2) PCIe data transfer design.
The dynamic reconfigurable framework is connected with the embedded system in a PCIe bus mode, and compared with other communication modes, the PCIe bus has the following characteristics:
(2.1) PCIe uses differential signaling for serial transmission, i.e. one PCIe lane needs 2 pairs of differential signals, one pair for receiving data and one pair for sending data.
And (2.2) PCIe utilizes point-to-point serial connection, and the data transmission rate of four channels can reach 2 GB/s.
(3) Data communication between PS and PL.
In the Zyqn chip, data interaction between the ARM and the FPGA is also accomplished through the AXI interface [30,41 ]. ARM can communicate data with PL through AXI _ HP (high Performance), AXI _ GP (general purpose), AXI _ ACP (accumulator coherence port), and the three ways have different application environments and transmission rates. The AXI _ HP provides a high-speed communication link for the ARM to access an external storage device, supports a 64-bit data width, and performs data caching by the FIFP having a read buffer and a write buffer. The data transmission process can be completed by the DMA controller independently without using a processor. The data width of the AXI _ GP interface is 32 bits, and is only suitable for application scenarios with lower speed, such as register configuration of modules in FPGA by ARM. The AXI _ ACP interface provides a low-delay data communication mode for the ARM and the FPGA, and the FPGA can access the Cache of the ARM part through the interface.
Specifically, in this embodiment, a dual bus structure is used inside the Zynq, an AXI4-Lite bus is used to configure registers of the modules, an AXIMemery Map bus is used to transmit a large amount of data, a PS portion in a hardware platform is used to perform dynamic reconfigurable configuration of an I/O interface, when an external device accesses the dynamic reconfigurable interface, the PS portion detects the type of the currently accessed I/O conversion board, obtains device information by querying storage on the I/O conversion board, and reconfigures a dynamic reconfigurable area of the I/O interface according to the device information. In the process of data transmission, data is stored in the memory, and finally the embedded system can acquire the data from the memory.
There are many studies on I/O interface reconfiguration, and generally, an I/O interface reconfiguration design with a wide application range and strong expandability needs to include three steps of external identification, register query and configuration, and data transmission, as shown in fig. 2.
The embedded system can transmit data with a plurality of external devices through a dynamic reconfigurable interface. Considering that external devices usually have standard communication interfaces, it is not realistic to use an interface compatible without any conversion. In the embodiment, an I/O board module is independently designed between the dynamic reconfiguration interface and the external device, so that the standard external device interface can be converted to the reconfigurable device. The I/O reconfiguration area has an AXI-Lite interface and an AXI interface and device connection signals for register control, data transfer, and communication with external devices, respectively, as shown in fig. 3.
Because different I/O devices have different electrical standards and interfaces and the number of signal lines is different, an I/O interface conversion board needs to be designed separately for each device to be compatible with the I/O dynamic reconfigurable interface of the dynamic reconfigurable system. Meanwhile, a special chip is integrated in the I/O interface conversion board for signal conversion, so that data transmission signals in the data lines are converted into signals which can be processed by the FPGA.
Fig. 4 shows an I/O interface conversion board in this embodiment. The I/O conversion board plays a role of connecting external equipment and Zynq in the whole framework of the I/O dynamic reconfigurable interface. The conversion chip is used for converting signals of external equipment into signals suitable for being processed by the FPGA, Zynq can know whether the external equipment is currently connected with the dynamic reconfiguration interface or not by detecting the in-place signals and the I/O conversion plate, and the type information of the I/O conversion plate and the external equipment interface is stored in the storage.
The dynamic identification of the I/O interface requires the co-participation of the in-place signal and the storage on the I/O conversion board. When accessing the dynamic reconfigurable interface of Zynq, Zynq can automatically detect whether the I/O interface conversion board is in place or not so as to determine whether to perform an operation of reading the storage of the I/O board, and the hardware design is as shown in fig. 5.
EEPROM is a non-volatile memory applicable to computers, representing electrically programmable read only memory, which can be applied to electronic devices storing small amounts of data, allowing erasure and rewriting of a single byte. In the scheme of dynamic identification of the I/O interface in this chapter, an EEPROM is used as storage on an I/O conversion board, information of the I/O conversion board is stored inside the EEPROM, and after an in-place signal is detected by Zynq, Zynq can acquire device information stored therein through an IIC interface.
When the I/O board is used for the first time, the EEPROM does not store equipment information matched with the I/O equipment, and the equipment information needs to be configured.
The dynamic reconfigurable interface is a data transmission interface of an I/O interface conversion plate and a Zynq dynamic reconfigurable frame, and the I/O interface conversion plate is used as an intermediate component for connecting the dynamic reconfigurable frame and external equipment, thereby playing a role of converting a standard interface into a reconfigurable interface. Here, it is necessary to design according to different I/O devices.
An example is given below. Assuming that the dynamic reconfigurable interface of the system is compatible with three communication modes of RS232, RS485 and CAN and a VGA camera, the signal distribution of the dynamic reconfigurable interface is as shown in Table 1.
TABLE 1 dynamic reconfigurable interface Allocation Table
Figure BDA0001881978080000061
For the reconfiguration of the computing task, the embedded system determines whether the reconfiguration is needed or not by inquiring which computing task logic is used in the current computing task area. After the reconfiguration of the computing task area is completed, the embedded system processes the computing task in a PCIe bus mode. In the Zynq dynamic reconfigurable framework, internal design is needed to support the data communication of computing tasks and expansion interfaces.
Specifically, the dynamic reconfiguration of the computing task is a way of analyzing the application scene and the characteristics of the embedded system, and finally, breaking the limitation of the computing capability of the embedded system, providing additional computing capability for the embedded system by combining a heterogeneous multiprocessor system structure and a dynamic reconfiguration technology of the FPGA, and efficiently utilizing limited FPGA hardware resources. The dynamically reconfigurable framework provides additional computing resources for the embedded system.
In a dynamic reconfigurable framework, each module generally needs two communication modes, one is that a master device configures and controls a register of the module through AXI-Lite, and the other is that the module transmits data to a memory. Therefore, considering the universality of the computing tasks and the requirement of uniform external interfaces in the dynamic area of each computing task, the dynamic area of the computing task externally provides two interfaces, namely AXI and AXI-Lite, and the master device can perform control and data transmission on the computing task area through the two interfaces, as shown in fig. 6.
The second embodiment is as follows: the dynamic reconfigurable method based on Zynq in the embodiment comprises an I/O interface logic reconfiguration part and a calculation task reconfiguration part,
the I/O interface logic reconfiguration portion includes the steps of:
the external equipment is connected to the I/O interface of Zynq through the I/O conversion board,
the processor system utilizing Zynq detects the type of I/O switch board currently accessed,
obtains the external device information by referring to the stored information of the I/O conversion board,
and Zynq reconfigures the dynamic reconfigurable area of the I/O interface according to the external equipment information, so that the I/O interface logic of Zynq is matched with the external equipment to complete the I/O interface logic reconfiguration, and Zynq sends a communication preparation notice to the embedded system.
The calculation task reconstruction part comprises the following steps:
zynq establishes data communication with the embedded system through the PCIe bus,
and the embedded system reconfigures the Zynq calculation task area according to task needs to complete the logic reconfiguration of the calculation task area.
The embodiment can store the information of the equipment in the I/O conversion plate, and identify the access equipment by reading the content stored on the I/O conversion plate, so that the access equipment has better expandability for different I/O equipment, and a fixed number of signal lines are used no matter how many types of I/O equipment exist. Obviously, the dynamic reconfiguration process of the whole I/O interface needs to work from hardware to a driver and then to a software in a multi-level manner. Firstly, the processors PS and PL of the embedded system processors ARM and Zynq are correctly divided into tasks, as shown in Table 2.
TABLE 2 task partition Table for each processor
Figure BDA0001881978080000071
The PS in Zynq has an independent ARM processor, which is the advantage of Zynq relative to FPGA, so that only Zynq can complete the dynamic identification of the I/O interface in the dynamic identification scheme of the I/O interface, and after the I/O interface is reconstructed, the embedded system can complete data communication through a Zynq dynamic reconfigurable framework.
Zynq can identify the I/O interface based on the device being accessed to decide when and what logic to reconstruct. The embodiment needs four parts, namely an equipment layer, an I/O interface conversion board, Zynq and an embedded system, as shown in FIG. 7. In fig. 7, the design of the I/O interface conversion board is an important part in the I/O interface dynamic reconfiguration method, and since the external device generally has a standard data transmission interface, and the dynamic reconfigurable target in this embodiment is a dynamic reconfigurable expansion interface, the standard interface of the external device needs to be converted into a general dynamic reconfigurable interface, and at the same time, the standard interface of the external device needs to have on-board storage for storing information matched with the device, so as to facilitate the dynamic reconfiguration of the I/O device. The purpose of the in-place signal is to make Zynq recognize whether the I/O interface conversion board is connected with the dynamic reconfigurable interface.
The dynamic reconfiguration of the I/O interface based on storage needs the cooperative work of software and hardware parts, has higher expandability compared with the prior mode of identification of a plurality of signal lines, and only needs to design a corresponding I/O conversion board and FPGA internal communication logic when other equipment needs to be compatible with the dynamic reconfigurable interface. After Zynq completes all work related to reconfiguration, when the device and the I/O board are accessed to the dynamic reconfiguration interface, I/O interface reconfiguration is triggered, and the specific flow is as follows:
(1) the equipment and the I/O interface are accessed to a dynamic reconfiguration interface;
(2) zynq detects an in-place signal, reads the equipment information stored in the I/O conversion board, and reconstructs the dynamic area of the I/O interface logic according to the information;
(3) after the I/O interface logic reconstruction is completed, the embedded system is informed that the I/O interface is ready;
(4) the embedded system communicates with the external device.
In this embodiment, the unique advantage of the I/O dynamic reconfigurable interface portion is that the Zynq PS is used to reconfigure the I/O interface dynamic area, identify from the external device, read the I/O converter board device information, and query to the PS for the matched I/O interface dynamic area logic and configuration register are independently completed by Zynq, so that no embedded system is required to participate in the I/O interface reconfiguration process, as shown in fig. 8.
According to the Zynq-based dynamic reconfigurable method, data communication is carried out with an embedded system through a PCIe bus, all modules on an FPGA in a Zynq reconfigurable framework can be controlled by the embedded system through PCIe, therefore, the embedded system can complete data transmission from the embedded system to external equipment accessed with a Zynq reconfigurable interface through operation of an I/O interface module in the FPGA, and the data transmission flow is shown in fig. 9.
PL in Zynq can provide FPGA hardware realization of a calculation task for an embedded system, so that processing of the calculation task is accelerated, efficiency of the system is improved, and overall power consumption is reduced. The dynamic reconfiguration region of the calculation task in the reconfiguration process can adopt a traditional RTL design method, and the hardware design of the FPGA can be realized after design, synthesis, layout and wiring; HLS high-level synthesis design methods can also be adopted. The computing tasks performed by Zynq are provided for the embedded system, so the choice of computing task is controlled by the embedded system. The reconstruction process is as follows:
(1) PS runs linux system and initializes local reconfiguration controller
(2) After the embedded system loads the PCIe drive, the local reconfiguration controller can be controlled by the PCIe bus to reconfigure the calculation task area according to the calculation task requirement.
(3) After the reconfiguration of the computing task is completed, data required by computing can be acquired through the PCIe bus.
(4) And after the calculation is finished, the embedded system acquires a corresponding result from the Zynq memory through the PCIe bus.

Claims (4)

1. The Zynq-based dynamic reconfigurable framework is characterized by comprising Zynq and an I/O conversion board, wherein the Zynq is in data communication with an embedded system through a PCIe bus, the Zynq is connected with external equipment through the I/O conversion board,
zynq comprises an I/O interface logic reconstruction unit and a calculation task reconstruction unit,
the I/O interface logic reconfiguration unit comprises the following modules:
a module for detecting a currently accessed I/O converter board type using the Zynq processor system,
a module for obtaining external device information by referring to the stored information of the I/O conversion board,
a module for reconfiguring the dynamic reconfigurable area of the I/O interface in Zynq according to the external device information, so that the I/O interface logic of Zynq is matched with the external device to complete the I/O interface logic reconfiguration;
the calculation task reconstruction unit comprises the following modules:
a module for reconfiguring Zynq calculation task area according to task requirement of embedded system to complete logic reconstruction of calculation task area;
the I/O conversion board comprises a memory, a conversion chip and an in-place signal detection module;
the conversion chip is used for converting the external equipment information into signals suitable for being processed by the programmable logic in Zynq,
the bit signal detection module is used for detecting an in-place signal, the in-place signal is used for judging whether external equipment is accessed to an I/O interface of Zynq at present,
the memory is used for storing I/O conversion board type and external equipment information.
2. The Zynq-based dynamic reconfigurable framework of claim 1, wherein the I/O interface logic reconfiguration unit further comprises means for issuing a prepare communication notification to the embedded system.
3. The dynamic reconfigurable method based on Zynq is characterized by comprising an I/O interface logic reconfigurable part and a calculation task reconfigurable part,
the I/O interface logic reconfiguration portion includes the steps of:
the external equipment is connected to the I/O interface of Zynq through the I/O conversion board,
the processor system utilizing Zynq detects the type of I/O switch board currently accessed,
obtains the external device information by referring to the stored information of the I/O conversion board,
the Zynq reconfigures the dynamic reconfigurable area of the I/O interface according to the external equipment information, so that the I/O interface logic of the Zynq is matched with the external equipment to complete I/O interface logic reconfiguration;
the calculation task reconstruction part comprises the following steps:
zynq establishes data communication with the embedded system through the PCIe bus,
the embedded system reconfigures the Zynq calculation task area according to task needs to complete the logic reconfiguration of the calculation task area;
the I/O conversion board is used for converting external equipment information into a signal suitable for being processed by programmable logic in Zynq, detecting a bit signal, storing the type of the I/O conversion board and the external equipment information,
the bit signal is used for judging whether external equipment is accessed to the Zynq I/O interface currently.
4. The Zynq-based dynamic reconfigurable method according to claim 3, characterized in that Zynq sends out a prepare communication notification to the embedded system after I/O interface logic reconfiguration is completed.
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