CN109491949A - Dynamic reconfigurable frame and method based on Zynq - Google Patents
Dynamic reconfigurable frame and method based on Zynq Download PDFInfo
- Publication number
- CN109491949A CN109491949A CN201811427524.3A CN201811427524A CN109491949A CN 109491949 A CN109491949 A CN 109491949A CN 201811427524 A CN201811427524 A CN 201811427524A CN 109491949 A CN109491949 A CN 109491949A
- Authority
- CN
- China
- Prior art keywords
- zynq
- interface
- external equipment
- dynamic reconfigurable
- calculating task
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
- G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Software Systems (AREA)
- Computer Hardware Design (AREA)
- Logic Circuits (AREA)
- Stored Programmes (AREA)
Abstract
Dynamic reconfigurable frame and method based on Zynq, are related to embedded system applied technical field.The present invention is to solve existing embedded system to volume and power consumption and have constraint, the not abundant problem of hardware resource.The present invention is capable of providing calculating task reconstruct and I/O interface reconfigurations function based on Zynq.The functional application of dynamic area local dynamic reconfigurable technology, calculating task function and is reconfigured with the matched I/O interface logic of access device on demand, improves the resource utilization of FPGA.It is finally reached and improves the efficiency of system-computed task, the purpose of a greater variety of I/O interfaces, the scalability for improving system is provided.
Description
Technical field
The invention belongs to embedded system applied technical fields.
Background technique
In recent years, with the development of low energy-consumption electronic device, embedded system has become the hot spot of application and research.With answering
It is become increasingly complex with environment, more stringent requirements are proposed to system by people, it is desirable to which system more efficiently handles calculating task, has
More flexible hardware configuration mode and Peripheral Interface.But the usual hardware resource of embedded system is not abundant enough, and to volume and
Power consumption has specific constraint.
Summary of the invention
The present invention is to solve existing embedded system to volume and power consumption and have constraint, and hardware resource is not abundant to ask
Topic, now provides dynamic reconfigurable frame and method based on Zynq.
Dynamic reconfigurable frame based on Zynq, including Zynq and I/O change-over panel, Zynq by PCIe bus with it is embedded
System carries out data communication, and Zynq establishes connection by I/O change-over panel and external equipment,
In Zynq include I/O interface logic reconfiguration unit and calculating task reconfiguration unit,
I/O interface logic reconfiguration unit comprises the following modules:
The module of the I/O being currently accessed conversion board type is detected for the processor system using Zynq,
For passing through the module of the storage information acquisition external equipment information of inquiry I/O change-over panel,
For being reconfigured according to dynamic reconfigurable region of the external equipment information to I/O interface in Zynq, so that
I/O interface logic and the external equipment of Zynq matches, and completes the module of I/O interface logic reconstruct；
Calculating task reconfiguration unit comprises the following modules:
It needs to reconfigure the calculating task region of Zynq for the task according to embedded system, completes to calculate
The module of mission area logical reconstruction.
Above-mentioned I/O interface logic reconfiguration unit further includes for issuing the module for preparing communication notifications to embedded system.
Above-mentioned I/O change-over panel includes memory, conversion chip and signal detection module in place；Conversion chip is used for will be external
Facility information is converted to the signal that programmable logic is handled in suitable Zynq, and position signal detection module is used to detect signal in place,
The signal in place is used for the I/O interface it is judged whether or not external equipment access Zynq, and memory is for storing I/O conversion
Board type and external equipment information.
Dynamic reconfigurable method based on Zynq, including I/O interface logic reconstruct part and calculating task reconstruct part,
I/O interface logic reconstructing part point the following steps are included:
External equipment is accessed to the I/O interface of Zynq by I/O change-over panel,
Board type is converted using the I/O that the processor system detection of Zynq is currently accessed,
By inquiring the storage information acquisition external equipment information of I/O change-over panel,
Zynq is reconfigured according to dynamic reconfigurable region of the external equipment information to I/O interface, so that Zynq
I/O interface logic matches with external equipment, completes the reconstruct of I/O interface logic；
Calculating task reconstructing part point the following steps are included:
Zynq is established into data communication by PCIe bus and embedded system,
Embedded system needs to reconfigure the calculating task region of Zynq according to task, completes calculating task area
Domain logical reconstruction.
After above-mentioned I/O interface logic reconstruct is completed, Zynq is issued to embedded system prepares communication notifications.
I/O change-over panel described above is used to being converted to external equipment information into the letter that programmable logic is handled in suitable Zynq
Number, for detecting signal in place, for storing I/O conversion board type and external equipment information, signal in place is current for judging
Whether the I/O interface of external equipment access Zynq is had.
The present invention is based on Zynq, in conjunction with FPGA (Field-Programmable Gate Array, field-programmable
Gate array) Dynamic Reconfigurable Technique devise a kind of dynamic reconfigurable frame and method based on Zynq, be capable of providing calculating
Task reconfiguration and I/O interface reconfigurations function, the PL in Zynq can provide the FPGA hardware reality of calculating task for embedded system
It is existing, to accelerate the processing of calculating task, the efficiency for improving system, reduce overall power.The hardware realization of calculating task can
It assists embedded system to carry out task processing, not only provides computing resource, while also mitigating the burden of embedded system.Dynamically
The functional application in region local dynamic reconfigurable technology, calculating task function and with access device matched I/O interface logic
It is reconfigured on demand, improves the resource utilization of FPGA.It is finally reached and improves the efficiency of system-computed task, provides more
The I/O interface of type, improve system scalability purpose.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of the dynamic reconfigurable frame based on Zynq described in specific embodiment one；
Fig. 2 is I/O interface reconfigurations flow chart；
Fig. 3 is I/O interface dynamic area structural schematic diagram；
Fig. 4 is the structural schematic diagram of I/O interface conversion plate；
Fig. 5 is I/O interface and Zynq attachment structure schematic diagram；
Fig. 6 is calculating task dynamic area structural schematic diagram；
Fig. 7 is I/O interface reconfigurations logical schematic；
Fig. 8 is the flow chart of I/O dynamic reconfigurable interface section in specific embodiment two；
Fig. 9 is data transmission stream journey figure.
Specific embodiment
Specific embodiment 1: the dynamic reconfigurable frame described in present embodiment based on Zynq, as shown in Figure 1, main
To be made of memory, power supply, storage card, I/O plate (i.e. I/O change-over panel) and Zynq chip, Zynq by PCIe bus with it is embedding
Embedded system carries out data communication, and Zynq establishes connection by I/O change-over panel and external equipment.
In Zynq include I/O interface logic reconfiguration unit and calculating task reconfiguration unit,
I/O interface logic reconfiguration unit comprises the following modules:
For the module for the I/O conversion board type that the processor system detection using Zynq is currently accessed, for by looking into
The module for asking the storage information acquisition external equipment information of I/O change-over panel, for being connect according to external equipment information to I/O in Zynq
The dynamic reconfigurable region of mouth is reconfigured, so that the I/O interface logic of Zynq matches with external equipment, completes I/O
The module of interface logic reconstruct, for issuing the module for preparing communication notifications to embedded system
Calculating task reconfiguration unit comprises the following modules:
It needs to reconfigure the calculating task region of Zynq for the task according to embedded system, completes to calculate
The module of mission area logical reconstruction.
I/O change-over panel includes memory, conversion chip and signal detection module in place；Conversion chip is used for external equipment
Information is converted to the signal that programmable logic is handled in suitable Zynq, and position signal detection module is described for detecting signal in place
Signal in place is used for the I/O interface it is judged whether or not external equipment access Zynq, and memory is for storing I/O change-over panel class
Type and external equipment information.
Wherein, Zynq is the heterogeneous multi-processor system knot using ARM+FPGA that Xilinx (match Sentos) company releases
Structure is provided simultaneously with the programmability of FPGA using arm processor as core, has the high-performance and low-power consumption of ASIC.Zynq chip
Structure is made of two parts, and a part is processor system (PS, Processing System), and another part is programmable patrols
It collects (PL, Programmable Logic).PS has arm processor in part, can either run linux operating system, can also be with
Run the bare machine program without operating system；PL is FPGA programmable logic, being capable of custom hardware design as needed.In Zynq
The Advanced extensible Interface (Advanced eXtensible Interface, AXI) of industrial standard is used between ARM and FPGA
Connection type, so that Zynq internal communication has both high bandwidth, the characteristics of low latency.
(1) interconnected designs.
In Zynq flow for dynamic reconfigurable system, modules interconnect IP kernel by AXI and are contacted, it is capable of providing multiple
Data communication interface of the AXI main equipment to multiple AXI from equipment can be made inside hardware platform using AXI interconnection IP kernel
Connection between modules is more easier, and modular structure is clear, is easy to hardware design and realization.Each main equipment can lead to
Cross address access mode freely control it is each from equipment.The connection between internal module is carried out with AXI interconnection IP kernel, at most may be used
To support 16 main equipments and 16 from equipment.Each equipment has the data transfer signal exclusively enjoyed inside IP kernel, so respectively
A master-slave equipment can guarantee each equipment unshared bandwidth during actual data transfer.It can not only ensure high speed in this way
Message transmission rate, also improve the flexibility contacted between various equipment.In the flow for dynamic reconfigurable system of this paper, carry
Each main equipment on same AXI interconnection IP kernel can control other from equipment.
Two kinds of sub-protocols in AXI protocol have been used in dynamic reconfigurable frame, are AXI4 interface protocol and AXI4- respectively
Lite interface protocol.AXI4 interface protocol is the Data Transport Protocol of peak performance, supports highest 256 data transmission, leads to
It is usually used in the application scenarios that main equipment access memory etc. needs high speed data transfer.AXI4-Lite interface protocol is AXI interface association
The simple version of view does not support the transmission of big data quantity, the single communication of register mappings mode is only applicable to, since its is lower
Data transmission efficiency, be usually applied to the data transmission of register access and low-speed device.
(2) PCIe data transmission design.
The dynamic reconfigurable frame of this paper is connect by PCIe bus mode with embedded system, relative to other communication parties
Formula, PCIe bus have the following characteristics that
(2.1) PCIe carries out serial transmission using differential signal, i.e. a channel PCIe needs 2 pairs of differential signals, a pair of
For receiving data, a pair is used to send data.
(2.2) PCIe uses point-to-point serial connection, and the message transmission rate of four-way is up to 2GB/s.
(3) data communication between PS and PL.
In Zyqn chip, the data interaction between ARM and FPGA is also to complete [30,41] by AXI interface.ARM can
To pass through AXI_HP (Hight Performance), AXI_GP (General Purpose), AXI_ACP (Accelerator
Coherency Port) and PL progress data communication, application environment and the transmission rate difference of these three modes.Wherein AXI_HP
The high speed communications link of access External memory equipment is provided for ARM, supports 64 bit data widths, buffers and writes containing reading simultaneously
The FIFP of buffering carries out data buffer storage.Processor can not be used in data transmission procedure, completed individually by dma controller.
The data width of AXI_GP interface is 32, is only applicable to the application scenarios compared with low rate, for example ARM posts module in FPGA
Storage configuration.AXI_ACP interface provides the data communication mode of low latency for ARM and FPGA, and FPGA can pass through this interface
Access the Cache of the part ARM.
Specifically, use dual-bus structure inside present embodiment Zynq, AXI4-Lite bus be used to modules into
Row register configuration, AXIMemery Map bus carry out big data quantity transmission, and it is dynamic to carry out I/O interface for the part PS in hardware platform
State reconfigurable configuration, when external equipment accesses dynamic reconfigurable interface, the part PS will detect that the I/O change-over panel being currently accessed
Type, and facility information is obtained by the storage on inquiry I/O change-over panel, according to facility information to the dynamic restructuring of I/O interface
Region is reconfigured.During data transmission, data will be saved in memory, and last embedded system can be from interior
Data are got in depositing.
Wherein, the research of I/O interface reconfigurations has had much at present, and usually, a use scope is extensive, scalability
Strong I/O interface reconfigurations design is needed comprising external identification, and register inquiry and configuration, data transmit these three steps, such as Fig. 2
It is shown.
Embedded system can be carried out data transmission by a dynamic reconfigurable interface with multiple external equipments.It considers
External equipment usually has the communication interface of standard, do not do it is any conversion and a use of interface compatibility is unrealistic.And
Present embodiment individually designed I/O plate module between dynamic restructuring interface and external equipment, can will standard it is outer
Portion's equipment interface is transformed into restructural equipment.There is I/O reconstruction region AXI-Lite interface letter is connected with equipment with AXI interface
Number, be respectively intended to make register control, data transmission and and external device communication, as shown in Figure 3.
Since different I/O equipment have different electrical standard and interface, and the quantity of signal wire is different, therefore, for
Every kind of equipment requires an individually designed I/O interface conversion plate and connects to be compatible with the I/O dynamic reconfigurable of flow for dynamic reconfigurable system
Mouthful.Meanwhile being internally integrated dedicated chip and carry out signal conversion in I/O interface conversion plate, so as to will be in data line
Data transfer signal be converted to the signal that FPGA is capable of handling.
I/O interface conversion plate is as shown in Figure 4 in present embodiment.I/O change-over panel is in entire I/O dynamic reconfigurable interface
Play the role of connection external equipment and Zynq in frame.Conversion chip thereon is to convert the signal of external equipment
For the signal for being suitble to FPGA processing, Zynq can learn currently whether have external equipment and I/O to convert by detecting signal in place
Plate accesses dynamic restructuring interface, and the type information of I/O change-over panel and external apparatus interface is stored in storage.
I/O interface Dynamic Recognition needs the common participation of signal and storage in place on I/O change-over panel.When moving for access Zynq
When the restructural interface of state, Zynq can automatically detect whether I/O interface conversion plate is in place, to decide whether to be read out
The operation of I/O plate storage, hardware design are as shown in Figure 5.
EEPROM is a kind of nonvolatile memory that can be applied to computer, electric programmable read-only memory in representative,
The electronic equipment that can be applied to storage low volume data, allows the erasing and rewriting of single byte.In the I/O interface dynamic of this chapter
In identifying schemes, use EEPROM as the storage on I/O change-over panel, the storage inside information of I/O interface conversion plate, when
After signal in place is detected by Zynq, Zynq can get the facility information wherein stored by IIC interface.
When using I/O plate for the first time, there is no the facility information that storage matches with I/O equipment in EEPROM, need pair
It is configured, can by data transfer signal and dynamic using the AXI-IIC core provided in Vivado tool in present embodiment
After signal binding in reconstruct interface for accessing EEPROM, so that it may carry out data for the first time to EEPROM by Zynq
Configuration.
Dynamic reconfigurable interface is the data transmission interface of I/O interface conversion plate Yu Zynq dynamic reconfigurable frame, and I/O connects
The intermediate member that mouth change-over panel is connect as dynamic reconfigurable frame with external equipment, plays and is converted to standard interface and can weigh
The effect of structure interface.Herein, it needs to be designed according to different I/O equipment.
Below for example.Assuming that tri- kinds of communication modes of system dynamic reconfigurable interface compatibility RS232, RS485, CAN and
VGA camera, dynamic reconfigurable interface signal distribution such as table 1.
1 dynamic reconfigurable interface assignment table of table
Reconstruct for calculating task, is determined by embedded system, by inquiring which kind of current calculating task region uses
Calculating task logic, to determine whether needing to reconfigure.Calculating task region reconfigure completion after, embedded system is logical
PCIe bus mode is crossed to carry out calculating task processing.In Zynq dynamic reconfigurable frame, calculating task and extension are supported
The data communication of interface needs internal be designed.
Specifically, the dynamic reconfigurable of calculating task is by the application scenarios of embedded system and itself feature point
Analysis, final purpose is to break the limitation of the computing capability of embedded system, in conjunction with heterogeneous multi-processor architecture and FPGA
Dynamic Reconfigurable Technique provide additional computing power for embedded system, and efficiently utilize limited FPGA hardware resource one
Kind mode.Dynamic reconfigurable frame provides additional computational resources for embedded system.
In dynamic reconfigurable frame, modules usually require two kinds of communication modes, and one is main equipments to pass through
AXI-Lite is configured and is controlled to the register of module, and another kind is that module transmits the data of memory.Accordingly, it is considered to
Unified external interface is needed in dynamic area to the versatility of calculating task and each calculating task, calculating task is moved
State region externally provides AXI and AXI-Lite two kinds of interfaces, main equipment can by both interfaces to calculating task region into
Row control and data transmission, as shown in Figure 6.
Specific embodiment 2: the dynamic reconfigurable method described in present embodiment based on Zynq, including I/O interface are patrolled
It collects reconstruct part and calculating task reconstructs part,
I/O interface logic reconstructing part point the following steps are included:
External equipment is accessed to the I/O interface of Zynq by I/O change-over panel,
Board type is converted using the I/O that the processor system detection of Zynq is currently accessed,
By inquiring the storage information acquisition external equipment information of I/O change-over panel,
Zynq is reconfigured according to dynamic reconfigurable region of the external equipment information to I/O interface, so that Zynq
I/O interface logic matches with external equipment, completes the reconstruct of I/O interface logic, and Zynq is issued to embedded system prepares communication
Notice.
Calculating task reconstructing part point the following steps are included:
Zynq is established into data communication by PCIe bus and embedded system,
Embedded system needs to reconfigure the calculating task region of Zynq according to task, completes calculating task area
Domain logical reconstruction.
The information of equipment can be stored in I/O change-over panel by present embodiment, pass through what is stored on reading I/O change-over panel
Content identifies access device so that there is better scalability to different I/O equipment, no matter how many type I/O equipment
Use the signal wire of fixed quantity.It is apparent that the dynamic restructuring requirements of process of entire I/O interface is from hardware to driving, then arrive
Software cooperates at many levels.The processor PS and PL for first having to handle embedded system device ARM, Zynq are correctly appointed
Business divides, as shown in table 2.
The task of each processor of table 2 divides table
PS in Zynq has independent arm processor, and this point is advantage of the Zynq relative to FPGA, therefore in I/O
Only Zynq can complete the Dynamic Recognition of I/O interface in the Dynamic Recognition scheme of interface, after the completion of I/O interface reconfigurations,
Embedded system can complete data communication by Zynq dynamic reconfigurable frame.
Zynq can identify I/O interface according to the equipment of access to decide when to reconstruct, which type of is reconstructed and is patrolled
Volume.Present embodiment needs mechanical floor, I/O interface conversion plate, Zynq, four part of embedded system, as shown in Figure 7.In Fig. 7,
The design of I/O interface conversion plate is the pith in I/O interface dynamic reconfigurable method, since external equipment usually has mark
Quasi- data transmission interface, and the target of dynamic reconfigurable is a dynamic reconfigurable expansion interface in present embodiment, therefore,
It needs to be converted to the standard interface of external equipment into general dynamic reconfigurable interface, while also to have on plate and store, be used to
Storage and the matched information of equipment, in order to I/O equipment dynamic restructuring.The purpose of signal in place is to allow Zynq to identify I/O
Whether interface conversion plate accesses dynamic reconfigurable interface.
I/O interface dynamic reconfigurable based on storage needs software and hardware part to cooperate, relative to more of front signal
Line is known has higher scalability otherwise, when there is other equipment to need compatible dynamic reconfigurable interface, it is only necessary to
Design corresponding I/O change-over panel and FPGA Intercommunication Logic.After Zynq completes all work relevant to reconstruct, work as equipment
When accessing dynamic restructuring interface with I/O plate, it will triggering I/O interface reconfigurations, detailed process are as follows:
(1) equipment and I/O interface access dynamic restructuring interface；
(2) Zynq detects signal in place, the facility information stored in I/O change-over panel is read, according to information to I/O interface
The dynamic area of logic is reconstructed；
(3) it is ready to notify that embedded system I/O interface is ready for after the completion for the reconstruct of I/O interface logic；
(4) embedded system is communicated with external equipment.
In present embodiment, the unique advantage of I/O dynamic reconfigurable interface section is using the PS of Zynq come to I/O interface
Dynamic area is reconfigured, and is identified from external equipment, and I/O change-over panel facility information is read, and the I/O to match to PS inquiry connects
Mouth dynamic area logic and configuration register are all by Zynq come complete independently, so not needing during I/O interface reconfigurations embedding
Embedded system is participated in, as shown in Figure 8.
Dynamic reconfigurable method based on Zynq carries out data communication by PCIe bus and embedded system, and Zynq can
All modules in reconstruct frame on FPGA can be controlled by embedded system by PCIe, therefore, embedded system
System passes through the operation to I/O interface module in FPGA, so that it may complete embedded system to the outer of the access restructural interface of Zynq
The data of portion's equipment are transmitted, and data transmission stream journey is as shown in Figure 9.
The FPGA hardware that PL in Zynq can provide calculating task for embedded system is realized, to accelerate calculating task
Processing, improve system efficiency, reduce overall power.Calculating task dynamic restructuring region in restructuring procedure can both use
The hardware design of FPGA may be implemented in traditional RTL design method after design, synthesis, placement-and-routing；It can also use
The design method of HLS High Level Synthesis.Calculating task performed by Zynq is provided for embedded system, so calculating task
Selection controlled by embedded system.Restructuring procedure is as follows:
(1) PS runs Linux system, and reconfigures controller to part and initialize
(2) it can be needed locally to be reconfigured by PCIe bus marco according to calculating task after embedded system load PCIe driving
Controller is set to reconfigure calculating task region.
(3) after calculating task reconfigures completion, data needed for calculating can be obtained by PCIe bus.
(4) after calculating, embedded system obtains corresponding result by PCIe bus from Zynq memory.
Claims (6)
1. the dynamic reconfigurable frame based on Zynq, which is characterized in that including Zynq and I/O change-over panel, Zynq is total by PCIe
Line and embedded system carry out data communication, and Zynq establishes connection by I/O change-over panel and external equipment,
In Zynq include I/O interface logic reconfiguration unit and calculating task reconfiguration unit,
I/O interface logic reconfiguration unit comprises the following modules:
The module of the I/O being currently accessed conversion board type is detected for the processor system using Zynq,
For passing through the module of the storage information acquisition external equipment information of inquiry I/O change-over panel,
For being reconfigured according to dynamic reconfigurable region of the external equipment information to I/O interface in Zynq, so that Zynq
I/O interface logic match with external equipment, complete I/O interface logic reconstruct module；
Calculating task reconfiguration unit comprises the following modules:
It needs to reconfigure the calculating task region of Zynq for the task according to embedded system, completes calculating task
The module of area logic reconstruct.
2. the dynamic reconfigurable frame according to claim 1 based on Zynq, which is characterized in that the reconstruct of I/O interface logic
Unit further includes for issuing the module for preparing communication notifications to embedded system.
3. the dynamic reconfigurable frame according to claim 1 or 2 based on Zynq, which is characterized in that I/O change-over panel includes
Memory, conversion chip and signal detection module in place；
Conversion chip is used to being converted to external equipment information into the signal that programmable logic is handled in suitable Zynq,
Position signal detection module is for detecting signal in place, and the signal in place is used for it is judged whether or not external equipment accesses
The I/O interface of Zynq,
Memory is for storing I/O conversion board type and external equipment information.
4. the dynamic reconfigurable method based on Zynq, which is characterized in that including I/O interface logic reconstruct part and calculating task weight
Structure part,
I/O interface logic reconstructing part point the following steps are included:
External equipment is accessed to the I/O interface of Zynq by I/O change-over panel,
Board type is converted using the I/O that the processor system detection of Zynq is currently accessed,
By inquiring the storage information acquisition external equipment information of I/O change-over panel,
Zynq is reconfigured according to dynamic reconfigurable region of the external equipment information to I/O interface, so that the I/O of Zynq connects
Mouth logical AND external equipment matches, and completes the reconstruct of I/O interface logic；
Calculating task reconstructing part point the following steps are included:
Zynq is established into data communication by PCIe bus and embedded system,
Embedded system needs to reconfigure the calculating task region of Zynq according to task, completes calculating task region and patrols
Collect reconstruct.
5. the dynamic reconfigurable method according to claim 4 based on Zynq, which is characterized in that the reconstruct of I/O interface logic
After completion, Zynq is issued to embedded system prepares communication notifications.
6. the dynamic reconfigurable method according to claim 4 or 5 based on Zynq, which is characterized in that the I/O change-over panel
For external equipment information to be converted to signal that programmable logic in suitable Zynq handles, is used to detect signal in place, is used for
I/O conversion board type and external equipment information are stored,
Signal in place is used for the I/O interface it is judged whether or not external equipment access Zynq.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811427524.3A CN109491949B (en) | 2018-11-27 | 2018-11-27 | Zynq-based dynamic reconfigurable framework and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811427524.3A CN109491949B (en) | 2018-11-27 | 2018-11-27 | Zynq-based dynamic reconfigurable framework and method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109491949A true CN109491949A (en) | 2019-03-19 |
| CN109491949B CN109491949B (en) | 2022-06-07 |
Family
ID=65697827
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811427524.3A Active CN109491949B (en) | 2018-11-27 | 2018-11-27 | Zynq-based dynamic reconfigurable framework and method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109491949B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110069030A (en) * | 2019-04-16 | 2019-07-30 | 湖南必然网络科技有限公司 | A kind of unmanned aerial vehicle (UAV) control core buckle |
| CN112433982A (en) * | 2020-11-27 | 2021-03-02 | 天津七所精密机电技术有限公司 | FPGA dynamic reconstruction method for ship public computing service terminal |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103744356A (en) * | 2014-01-17 | 2014-04-23 | 重庆大学 | Intelligent dynamically-configurable controller of tool based on DSP (Digital Signal Processor)/FPGA (Field Programmable Gate Array) and control method |
| CN104536755A (en) * | 2014-12-29 | 2015-04-22 | 深圳市国微电子有限公司 | Reconstruction method and device for programmable logic device |
| US20160161466A1 (en) * | 2013-08-30 | 2016-06-09 | Magnomics S.A. | Scalable and high throughput biosensing platform |
| CN106645914A (en) * | 2017-01-03 | 2017-05-10 | 哈尔滨工业大学 | Ground test device of satellite information processing platform and control method of ground test device |
| CN107479831A (en) * | 2017-08-11 | 2017-12-15 | 浙江工业大学 | A kind of OCT volume data method for carrying based on Zynq platforms |
-
2018
- 2018-11-27 CN CN201811427524.3A patent/CN109491949B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20160161466A1 (en) * | 2013-08-30 | 2016-06-09 | Magnomics S.A. | Scalable and high throughput biosensing platform |
| CN103744356A (en) * | 2014-01-17 | 2014-04-23 | 重庆大学 | Intelligent dynamically-configurable controller of tool based on DSP (Digital Signal Processor)/FPGA (Field Programmable Gate Array) and control method |
| CN104536755A (en) * | 2014-12-29 | 2015-04-22 | 深圳市国微电子有限公司 | Reconstruction method and device for programmable logic device |
| CN106645914A (en) * | 2017-01-03 | 2017-05-10 | 哈尔滨工业大学 | Ground test device of satellite information processing platform and control method of ground test device |
| CN107479831A (en) * | 2017-08-11 | 2017-12-15 | 浙江工业大学 | A kind of OCT volume data method for carrying based on Zynq platforms |
Non-Patent Citations (2)
| Title |
|---|
| 徐健等: "基于FPGA的动态部分可重构智能I/O接口设计与实现", 《计算机工程》 * |
| 柴镇: ""FPGA可重构计算的规模可伸缩性研究及实现"", <中国优秀硕士学位论文全文数据库 信息科技辑> * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110069030A (en) * | 2019-04-16 | 2019-07-30 | 湖南必然网络科技有限公司 | A kind of unmanned aerial vehicle (UAV) control core buckle |
| CN112433982A (en) * | 2020-11-27 | 2021-03-02 | 天津七所精密机电技术有限公司 | FPGA dynamic reconstruction method for ship public computing service terminal |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109491949B (en) | 2022-06-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP2506150A1 (en) | Method and system for entirety mutual access in multi-processor | |
| CN108121672B (en) | Storage array control method and device based on NandFlash storage multichannel | |
| CN104252435B (en) | Varistructure intelligence interface and its collocation method based on dynamic reconfigurable FPGA | |
| CN201294545Y (en) | Multi-protocol data acquisition gateway | |
| CN101626351A (en) | Multiprotocol data acquisition gateway | |
| CN111901164B (en) | Adaptive control method, device, equipment and system of OCP NIC network card | |
| CN102388357B (en) | Method and system for accessing memory device | |
| CN111090603B (en) | LVDS-to-USB 3.0 adapter | |
| CN101937412A (en) | System on chip and access method thereof | |
| CN209168746U (en) | A kind of Common Flash Memory test macro based on FPGA | |
| CN102378133A (en) | System and method for processing multimedia information of sensor network based on OMAP (Open Multimedia Application Platform) | |
| CN110806997B (en) | System on chip and memory | |
| CN1687902A (en) | Embedded real-time simulation platform | |
| CN107562672A (en) | A kind of system and method for improving vector network analyzer message transmission rate | |
| CN109981431A (en) | A kind of CAN controller data storage circuitry and date storage method | |
| CN109491949A (en) | Dynamic reconfigurable frame and method based on Zynq | |
| CN116719755B (en) | Method, device and equipment for multi-application memory access | |
| CN101136754A (en) | Data transmission control system of ethernet chip | |
| CN109411007A (en) | A kind of Common Flash Memory test macro based on FPGA | |
| CN111581152A (en) | Reconfigurable hardware acceleration SOC chip system | |
| CN108920193B (en) | SDIO communication interface implementation method and device between FPGA and CPU | |
| CN112035398B (en) | System-on-chip (SoC) and data processing method suitable for SoC | |
| CN114138297A (en) | ZYNQ-based FPGA radar data debugging system and debugging method | |
| CN103984663B (en) | A kind of multiformity electronic equipment on satellite of parallel system | |
| CN109407574A (en) | Output-controlling device and its method may be selected in a kind of multibus |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |