CN109379177A - A kind of homomorphism cryptogram computation acceleration logic system and implementation method - Google Patents
A kind of homomorphism cryptogram computation acceleration logic system and implementation method Download PDFInfo
- Publication number
- CN109379177A CN109379177A CN201811599757.1A CN201811599757A CN109379177A CN 109379177 A CN109379177 A CN 109379177A CN 201811599757 A CN201811599757 A CN 201811599757A CN 109379177 A CN109379177 A CN 109379177A
- Authority
- CN
- China
- Prior art keywords
- ciphertext
- logic module
- input
- relevant operation
- cache
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/008—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols involving homomorphic encryption
Landscapes
- Engineering & Computer Science (AREA)
- Computer Security & Cryptography (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Financial Or Insurance-Related Operations Such As Payment And Settlement (AREA)
- Storage Device Security (AREA)
Abstract
The present invention discloses a kind of homomorphism cryptogram computation acceleration logic system and implementation method, is related to cloud computing security fields；Increase homomorphism calculating logic module using to the inside FPGA, the cryptogram computation logic module of homomorphism calculating logic inside modules carries out relevant operation according to ciphertext public key to ciphertext, cooperate with homomorphic decryption logic module to ciphertext noise reduction again, it repeats the above process, until completing relevant operation to the ciphertext that host is sent, in data exchange process, caching can also be set and meet high speed data transfer, homomorphic cryptography flow chart of data processing is not accelerated merely with homomorphic cryptography technology, homomorphism ciphertext operation efficiency is effectively promoted, and can solve the safety problem of cloud environment privacy of user.
Description
Technical field
The present invention discloses a kind of homomorphism cryptogram computation acceleration logic system and implementation method, is related to cloud computing security fields.
Background technique
In recent years, the safety accident under cloud computing environment happens occasionally, and the data-privacy problem of cloud environment causes people
Great attention security study analysis shows: the data in cloud are easily leaked, and the weakness of cloud computing is concentrated mainly on data protection
And Identity Management.At present, people only store data into the countermeasure of the data-privacy safety problem in cloud environment
It is encrypted before Cloud Server in advance, when use is decrypted by user again.Common data-privacy protection technique has: being used for
Distinguish the proxy re-encryption technology and attribute encryption technology of data consumer's identity, the access control for resource authorization access profile
Technology processed can search for encryption technology etc. for carrying out retrieval access to ciphertext data.These technologies are protected using traditional encryption
Shield can only meet the function of encryption storage, lack directly calculated ciphertext, more easily secret protection means.
The present invention provides a kind of homomorphism cryptogram computation acceleration logic system and implementation method, realizes homomorphism cryptogram computation hardware
Acceleration logic, entire that framework is accelerated to carry out homomorphic cryptography flow chart of data processing, buffer setting meets high speed data transfer, effectively mentions
Rise homomorphism ciphertext operation efficiency.
Summary of the invention
The present invention is directed to problem of the prior art, provides a kind of homomorphism cryptogram computation acceleration logic system and implementation method,
Have the characteristics that it is versatile, be easy to implement, have broad application prospects.
Concrete scheme proposed by the present invention is:
It include homomorphism calculating logic module inside a kind of homomorphism cryptogram computation acceleration logic system, including FPGA, FPGA,
Homomorphism calculating logic module include memory, control logic module, cache logic module, cryptogram computation logic module,
Homomorphic decryption logic module,
Homomorphism calculating logic module carries out data interaction by FPGA interface and host:
Host by ciphertext, ciphertext public key and the memory for being sent to homomorphism calculating logic module to the relevant operation of ciphertext,
Control logic module controls the data interaction between cryptogram computation process and module according to host command, first will be close
Text and is input to cache logic module to the relevant operation of ciphertext at ciphertext public key from memory,
Cryptogram computation logic module obtains ciphertext, ciphertext public key and the relevant operation to ciphertext of cache logic module, according to
Relevant operation processing is carried out to ciphertext according to ciphertext public key, ciphertext is sent back to ciphertext noise reduction after processing by homomorphic decryption logic module again
Cryptogram computation logic module, repetitive cycling is until cryptogram computation logic completes the relevant operation of ciphertext, the output of cache logic module
Complete the ciphertext of relevant operation.
Cache logic module includes that input-buffer logic module, output cache logic module and data are handed in the system
Cache logic module is changed,
Ciphertext, ciphertext public key and input-buffer logic module is input to from memory to the relevant operation of ciphertext,
The ciphertext for completing relevant operation is exported by output cache logic module,
Cryptogram computation logic module and homomorphic decryption logic module pass through the progress data friendship of data exchange cache logic module
It changes.
Input-buffer logic module includes ciphertext input-buffer, operation input caching and EvKey input in the system
Caching, ciphertext are input to ciphertext input-buffer, are input to operation input caching to the relevant operation of ciphertext, ciphertext public key is input to
EvKey input-buffer.
Data exchange cache logic module includes that homomorphic decryption caching and fresh ciphertext cache in the system,
Cryptogram computation logic module will carry out relevant operation treated ciphertext and cache by homomorphic decryption to be sent to homomorphism
Decryption logic module,
Homomorphic decryption logic module sends ciphertext after noise reduction back to cryptogram computation logic module by fresh ciphertext caching.
It includes cryptogram computation result cache that cache logic module is exported in the system, and the ciphertext for completing relevant operation is logical
Cross the caching output of ciphertext calculated result.
A kind of homomorphism cryptogram computation acceleration logic implementation method increases homomorphism calculating logic module to the inside FPGA,
Wherein homomorphism calculating logic module includes memory, control logic module, cache logic module, cryptogram computation logic mould
Block, homomorphic decryption logic module,
Homomorphism calculating logic module carries out data interaction by FPGA interface and host:
Host by ciphertext, ciphertext public key and the memory for being sent to homomorphism calculating logic module to the relevant operation of ciphertext,
Control logic module controls the data interaction between cryptogram computation process and module according to host command, first will be close
Text and is input to cache logic module to the relevant operation of ciphertext at ciphertext public key from memory,
Cryptogram computation logic module obtains ciphertext, ciphertext public key and the relevant operation to ciphertext of cache logic module, according to
Relevant operation processing is carried out to ciphertext according to ciphertext public key, ciphertext is sent back to ciphertext noise reduction after processing by homomorphic decryption logic module again
Cryptogram computation logic module, repetitive cycling is until cryptogram computation logic completes the relevant operation of ciphertext, the output of cache logic module
Complete the ciphertext of relevant operation.
Cache logic module includes input-buffer logic module, output cache logic module and number in the implementation method
According to cache exchanging logic module,
Ciphertext and input-buffer logic module is input to the relevant operation of ciphertext,
The ciphertext for completing relevant operation is exported by output cache logic module,
Cryptogram computation logic module and homomorphic decryption logic module pass through the progress data friendship of data exchange cache logic module
It changes.
Input-buffer logic module includes ciphertext input-buffer, operation input caching and EvKey in the implementation method
Input-buffer, ciphertext are input to ciphertext input-buffer, are input to operation input caching to the relevant operation of ciphertext, ciphertext public key is defeated
Enter to EvKey input-buffer.
Data exchange cache logic module includes that homomorphic decryption caching and fresh ciphertext cache in the implementation method,
Cryptogram computation logic module will carry out relevant operation treated ciphertext and cache by homomorphic decryption to be sent to homomorphism
Decryption logic module,
Homomorphic decryption logic module sends ciphertext after noise reduction back to cryptogram computation logic module by fresh ciphertext caching.
The specific steps that homomorphism cryptogram computation acceleration logic is realized in the implementation method are as follows:
Step 1: host by calculative ciphertext, ciphertext public key and is sent into the relevant operation of ciphertext by FPGA interface
The memory of homomorphism calculating logic module,
Step 2: ciphertext is sent into ciphertext input-buffer according to host command by control logic module, and ciphertext public key is sent into
EvKey input-buffer is sent into operation input caching to the relevant operation of ciphertext,
Step 3: cryptogram computation logic module is cached from ciphertext input-buffer, EvKey input-buffer and operation input respectively
Middle acquisition ciphertext, ciphertext public key and the relevant operation to ciphertext carry out relevant operation processing to ciphertext according to ciphertext public key, will locate
Ciphertext is sent to homomorphic decryption logic module by homomorphic decryption caching after reason,
Step 4: homomorphic decryption logic module to cached after ciphertext noise reduction after processing by fresh ciphertext ciphertext sent back to it is close
Literary calculating logic module,
Step 5: repetitive cycling step 3 and step 4, until cryptogram computation logic completes the relevant operation of ciphertext, caching is patrolled
Collect the ciphertext that relevant operation is completed in module output.
Usefulness of the present invention is:
The present invention, which is utilized, increases homomorphism calculating logic module, the ciphertext meter of homomorphism calculating logic inside modules to the inside FPGA
It calculates logic module and relevant operation is carried out according to ciphertext public key to ciphertext, then cooperate with homomorphic decryption logic module to ciphertext noise reduction, weight
The multiple above process, until in data exchange process, it is full that caching can also be arranged to the ciphertext completion relevant operation that host is sent
Sufficient high speed data transfer does not accelerate homomorphic cryptography flow chart of data processing merely with homomorphic cryptography technology, effectively promotes homomorphism ciphertext
Operation efficiency, and can solve the safety problem of cloud environment privacy of user.
Detailed description of the invention
Fig. 1 is present system module interaction schematic diagram；
Fig. 2 the method for the present invention flow diagram.
Specific embodiment
It includes that homomorphism calculates that the present invention, which is provided inside a kind of homomorphism cryptogram computation acceleration logic system, including FPGA, FPGA,
Logic module,
Homomorphism calculating logic module include memory, control logic module, cache logic module, cryptogram computation logic module,
Homomorphic decryption logic module,
Homomorphism calculating logic module carries out data interaction by FPGA interface and host:
Host by ciphertext, ciphertext public key and the memory for being sent to homomorphism calculating logic module to the relevant operation of ciphertext,
Control logic module controls the data interaction between cryptogram computation process and module according to host command, first will be close
Text and is input to cache logic module to the relevant operation of ciphertext at ciphertext public key from memory,
Cryptogram computation logic module obtains ciphertext, ciphertext public key and the relevant operation to ciphertext of cache logic module, according to
Relevant operation processing is carried out to ciphertext according to ciphertext public key, ciphertext is sent back to ciphertext noise reduction after processing by homomorphic decryption logic module again
Cryptogram computation logic module, repetitive cycling is until cryptogram computation logic completes the relevant operation of ciphertext, the output of cache logic module
Complete the ciphertext of relevant operation.
A kind of homomorphism cryptogram computation acceleration logic implementation method corresponding with above system is provided simultaneously, to the inside FPGA
Increase homomorphism calculating logic module,
Wherein homomorphism calculating logic module includes memory, control logic module, cache logic module, cryptogram computation logic mould
Block, homomorphic decryption logic module,
Homomorphism calculating logic module carries out data interaction by FPGA interface and host:
Host by ciphertext, ciphertext public key and the memory for being sent to homomorphism calculating logic module to the relevant operation of ciphertext,
Control logic module controls the data interaction between cryptogram computation process and module according to host command, first will be close
Text and is input to cache logic module to the relevant operation of ciphertext at ciphertext public key from memory,
Cryptogram computation logic module obtains ciphertext, ciphertext public key and the relevant operation to ciphertext of cache logic module, according to
Relevant operation processing is carried out to ciphertext according to ciphertext public key, ciphertext is sent back to ciphertext noise reduction after processing by homomorphic decryption logic module again
Cryptogram computation logic module, repetitive cycling is until cryptogram computation logic completes the relevant operation of ciphertext, the output of cache logic module
Complete the ciphertext of relevant operation.
The present invention will be further explained below with reference to the attached drawings and specific examples, so that those skilled in the art can be with
It more fully understands the present invention and can be practiced, but illustrated embodiment is not as a limitation of the invention.
Using the method for the present invention or system, host is by the PCIE interface of FPGA by calculative ciphertext, relevant operation
The memory of homomorphism calculating logic module is sent into Evkey, Evkey full name is evaluate key, i.e., is used in full homomorphic algorithm
The key of evaluate algorithm, concrete form is related with full homomorphism scheme selection, and current full homomorphism scheme is bootstrapple
Or key exchange obtains the modes such as full homomorphism, it is ciphertext public key that evkey, which is in the present invention, also referred to as cryptogram computation public key,
Control logic module is patrolled ciphertext, relevant operation and Evkey feeding input-buffer by reading host control instruction
Volume；
Cryptogram computation logic module operates ciphertext according to Evkey, and every time after operation, the result with noise is put
Enter homomorphic decryption logic module；Homomorphic decryption logic carries out noise, and the fresh ciphertext after noise will be gone to send cryptogram computation back to
Logic module；Repetitive cycling exports caching output until the ciphertext completed required relevant operation, and will complete relevant operation is sent into,
Entire calculation process is completed,
It is interconnected between PCIE interface and the Memory Controller Hub of homomorphism calculating logic module memory by DMA channel, reduces master
Machine expense.
By taking user's concrete operations as an example: the data of user are that A has attribute a, B to have attribute b, C to have attribute c；
If user needs cloud to be a liter sorting operation F to ABC, and cloud is not intended to know ABC and its attribute, then need to lead to
Crossing after local cipher algorithm encrypts ABC becomes: X has attribute x, Y to have attribute y, Z to have attribute z；By X (x), Y (y), Z (z), behaviour
Make F, cryptogram computation public key EvKey is sent to cloud,
Cloud server is that XYZ, F, EvKey are sent into homomorphism by PCIE and calculated as the host referred in the present invention
The memory of logic module, later by control logic module by reading cloud server control instruction, by X (x), Y (y), Z
(z) it is sent into ciphertext input-buffer, operation F is sent into operation input caching, EvKey is sent into Evkey input-buffer；
Cryptogram computation logic module operates the XYZ F for carrying out xyz by Evkey, such as is adjusted to xzy+ δ, δ for the first time
For additional noise, the data after needing to operate later are sent into homomorphic decryption caching, are re-fed into homomorphic decryption logic module, into
Xzy is returned to fresh ciphertext and cached, sends cryptogram computation logic module back to by row denoising δ, continues to operate F, until final result,
Zyx is exported to cryptogram computation result cache, is sent into memory by control logic module, then passed through by cloud server
PCIE is read, and is sent to user；
Z (z), Y (y), X (x) decrypts as C (c), B (b), A (a) by itself decipherment algorithm by user, and cba is as liter
The result of sorting operation F.
Do not accelerate homomorphic cryptography flow chart of data processing merely with homomorphic cryptography technology using the present invention, it is close effectively to promote homomorphism
Literary operation efficiency, and can solve the safety problem of cloud environment privacy of user.
Embodiment described above is only to absolutely prove preferred embodiment that is of the invention and being lifted, protection model of the invention
It encloses without being limited thereto.Those skilled in the art's made equivalent substitute or transformation on the basis of the present invention, in the present invention
Protection scope within.Protection scope of the present invention is subject to claims.
Claims (10)
1. a kind of homomorphism cryptogram computation acceleration logic system, it is characterized in that
It include homomorphism calculating logic module inside FPGA including FPGA,
Homomorphism calculating logic module includes memory, control logic module, cache logic module, cryptogram computation logic module, homomorphism
Decryption logic module,
Homomorphism calculating logic module carries out data interaction by FPGA interface and host:
Host by ciphertext, ciphertext public key and the memory for being sent to homomorphism calculating logic module to the relevant operation of ciphertext,
Control logic module controls the data interaction between cryptogram computation process and module according to host command, first by ciphertext, close
Literary public key and cache logic module is input to from memory to the relevant operation of ciphertext,
Cryptogram computation logic module obtains ciphertext, ciphertext public key and the relevant operation to ciphertext of cache logic module, according to close
Literary public key carries out relevant operation processing to ciphertext, and homomorphic decryption logic module sends ciphertext back to ciphertext again to ciphertext noise reduction after processing
Calculating logic module, repetitive cycling until cryptogram computation logic completes the relevant operation of ciphertext, complete by the output of cache logic module
The ciphertext of relevant operation.
2. system according to claim 1, it is characterized in that cache logic module includes input-buffer logic module, exports and delay
Logic module and data exchange cache logic module are deposited,
Ciphertext, ciphertext public key and input-buffer logic module is input to from memory to the relevant operation of ciphertext,
The ciphertext for completing relevant operation is exported by output cache logic module,
Cryptogram computation logic module and homomorphic decryption logic module pass through data exchange cache logic module progress data exchange.
3. system according to claim 2, it is characterized in that input-buffer logic module includes that ciphertext input-buffer, operation are defeated
Enter caching and EvKey input-buffer, ciphertext is input to ciphertext input-buffer, and it is slow to be input to operation input to the relevant operation of ciphertext
It deposits, ciphertext public key is input to EvKey input-buffer.
4. system according to claim 2 or 3, it is characterized in that data exchange cache logic module includes homomorphic decryption caching
It is cached with fresh ciphertext,
Cryptogram computation logic module will carry out relevant operation treated ciphertext and cache by homomorphic decryption to be sent to homomorphic decryption
Logic module,
Homomorphic decryption logic module sends ciphertext after noise reduction back to cryptogram computation logic module by fresh ciphertext caching.
5. system according to claim 4, it is characterized in that output cache logic module includes cryptogram computation result cache, it is complete
It is exported at the ciphertext of relevant operation by cryptogram computation result cache.
6. a kind of homomorphism cryptogram computation acceleration logic implementation method, it is characterized in that increasing homomorphism calculating logic mould to the inside FPGA
Block,
Wherein homomorphism calculating logic module include memory, control logic module, cache logic module, cryptogram computation logic module,
Homomorphic decryption logic module,
Homomorphism calculating logic module carries out data interaction by FPGA interface and host:
Host by ciphertext, ciphertext public key and the memory for being sent to homomorphism calculating logic module to the relevant operation of ciphertext,
Control logic module controls the data interaction between cryptogram computation process and module according to host command, first by ciphertext, close
Literary public key and cache logic module is input to from memory to the relevant operation of ciphertext,
Cryptogram computation logic module obtains ciphertext, ciphertext public key and the relevant operation to ciphertext of cache logic module, according to close
Literary public key carries out relevant operation processing to ciphertext, and homomorphic decryption logic module sends ciphertext back to ciphertext again to ciphertext noise reduction after processing
Calculating logic module, repetitive cycling until cryptogram computation logic completes the relevant operation of ciphertext, complete by the output of cache logic module
The ciphertext of relevant operation.
7. implementation method according to claim 6, it is characterized in that cache logic module include input-buffer logic module, it is defeated
Cache logic module and data exchange cache logic module out,
Ciphertext and input-buffer logic module is input to the relevant operation of ciphertext,
The ciphertext for completing relevant operation is exported by output cache logic module,
Cryptogram computation logic module and homomorphic decryption logic module pass through data exchange cache logic module progress data exchange.
8. implementation method according to claim 7, it is characterized in that input-buffer logic module includes ciphertext input-buffer, behaviour
Make input-buffer and EvKey input-buffer, ciphertext is input to ciphertext input-buffer, and it is defeated to be input to operation to the relevant operation of ciphertext
Enter caching, ciphertext public key is input to EvKey input-buffer.
9. implementation method according to claim 7 or 8, it is characterized in that data exchange cache logic module includes homomorphic decryption
Caching and fresh ciphertext caching,
Cryptogram computation logic module will carry out relevant operation treated ciphertext and cache by homomorphic decryption to be sent to homomorphic decryption
Logic module,
Homomorphic decryption logic module sends ciphertext after noise reduction back to cryptogram computation logic module by fresh ciphertext caching.
10. implementation method according to claim 9, it is characterized in that the specific steps that homomorphism cryptogram computation acceleration logic is realized
Are as follows:
Step 1: host by calculative ciphertext, ciphertext public key and is sent into homomorphism to the relevant operation of ciphertext by FPGA interface
The memory of calculating logic module,
Step 2: ciphertext is sent into ciphertext input-buffer according to host command by control logic module, and it is defeated that ciphertext public key is sent into EvKey
Enter caching, operation input caching be sent into the relevant operation of ciphertext,
Step 3: cryptogram computation logic module is obtained from ciphertext input-buffer, EvKey input-buffer and operation input caching respectively
Ciphertext, ciphertext public key and the relevant operation to ciphertext are obtained, relevant operation processing is carried out to ciphertext according to ciphertext public key, after processing
Ciphertext is sent to homomorphic decryption logic module by homomorphic decryption caching,
Step 4: homomorphic decryption logic module sends ciphertext back to ciphertext meter by fresh ciphertext caching to after ciphertext noise reduction after processing
Logic module is calculated,
Step 5: repetitive cycling step 3 and step 4, until cryptogram computation logic completes the relevant operation of ciphertext, cache logic mould
The ciphertext of relevant operation is completed in block output.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811599757.1A CN109379177A (en) | 2018-12-26 | 2018-12-26 | A kind of homomorphism cryptogram computation acceleration logic system and implementation method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811599757.1A CN109379177A (en) | 2018-12-26 | 2018-12-26 | A kind of homomorphism cryptogram computation acceleration logic system and implementation method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109379177A true CN109379177A (en) | 2019-02-22 |
Family
ID=65371681
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811599757.1A Pending CN109379177A (en) | 2018-12-26 | 2018-12-26 | A kind of homomorphism cryptogram computation acceleration logic system and implementation method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109379177A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111563267A (en) * | 2020-05-08 | 2020-08-21 | 京东数字科技控股有限公司 | Method and device for processing federal characteristic engineering data |
| CN111832050A (en) * | 2020-07-10 | 2020-10-27 | 深圳致星科技有限公司 | Paillier encryption scheme based on FPGA chip implementation for federal learning |
| CN112035866A (en) * | 2020-11-04 | 2020-12-04 | 湖北芯擎科技有限公司 | Data encryption and decryption method, device, equipment and computer readable storage medium |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103269267A (en) * | 2013-04-19 | 2013-08-28 | 深圳市全同态科技有限公司 | Fully homomorphic encryption device |
| CN106452765A (en) * | 2016-12-16 | 2017-02-22 | 中国科学院深圳先进技术研究院 | Hardware Trojan defense method and device based on fully homomorphic encryption algorithm |
| CN106953722A (en) * | 2017-05-09 | 2017-07-14 | 深圳市全同态科技有限公司 | Ciphertext query method and system for full homomorphic encryption |
| CN107294698A (en) * | 2017-07-25 | 2017-10-24 | 西安电子科技大学 | The full homomorphic cryptography method that single ciphertext homomorphism is calculated |
-
2018
- 2018-12-26 CN CN201811599757.1A patent/CN109379177A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103269267A (en) * | 2013-04-19 | 2013-08-28 | 深圳市全同态科技有限公司 | Fully homomorphic encryption device |
| CN106452765A (en) * | 2016-12-16 | 2017-02-22 | 中国科学院深圳先进技术研究院 | Hardware Trojan defense method and device based on fully homomorphic encryption algorithm |
| CN106953722A (en) * | 2017-05-09 | 2017-07-14 | 深圳市全同态科技有限公司 | Ciphertext query method and system for full homomorphic encryption |
| CN107294698A (en) * | 2017-07-25 | 2017-10-24 | 西安电子科技大学 | The full homomorphic cryptography method that single ciphertext homomorphism is calculated |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111563267A (en) * | 2020-05-08 | 2020-08-21 | 京东数字科技控股有限公司 | Method and device for processing federal characteristic engineering data |
| CN111563267B (en) * | 2020-05-08 | 2024-04-05 | 京东科技控股股份有限公司 | Method and apparatus for federal feature engineering data processing |
| CN111832050A (en) * | 2020-07-10 | 2020-10-27 | 深圳致星科技有限公司 | Paillier encryption scheme based on FPGA chip implementation for federal learning |
| CN111832050B (en) * | 2020-07-10 | 2021-03-26 | 深圳致星科技有限公司 | Paillier encryption scheme based on FPGA chip implementation for federal learning |
| CN112035866A (en) * | 2020-11-04 | 2020-12-04 | 湖北芯擎科技有限公司 | Data encryption and decryption method, device, equipment and computer readable storage medium |
| CN112035866B (en) * | 2020-11-04 | 2021-07-23 | 湖北芯擎科技有限公司 | Data encryption method, device, equipment and computer readable storage medium |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Yun-Peng et al. | Digital image encryption algorithm based on chaos and improved DES | |
| EP3667535B1 (en) | Storage data encryption and decryption device and method | |
| CN109379177A (en) | A kind of homomorphism cryptogram computation acceleration logic system and implementation method | |
| CN101043326B (en) | Dynamic information encrypting system and method | |
| CN107528690A (en) | A kind of symmetrical encryption and decryption method and systems of SM4 for accelerating platform based on isomery | |
| CN102737270B (en) | A kind of bank intelligent card chip secure coprocessor based on domestic algorithm | |
| CN107491317A (en) | A kind of symmetrical encryption and decryption method and systems of AES for accelerating platform based on isomery | |
| CN105376057B (en) | A kind of method of the extensive system of linear equations of cloud outsourcing solution | |
| CN110348230A (en) | A kind of project management method and system | |
| CN104967693A (en) | Document similarity calculation method facing cloud storage based on fully homomorphic password technology | |
| CN106788963A (en) | A kind of full homomorphic cryptography method of identity-based on improved lattice | |
| CN105100248A (en) | Cloud storage security realization method based on data encryption and access control | |
| CN103780608A (en) | SM4-algorithm control method based on programmable gate array chip | |
| CN103336920A (en) | Security system for wireless sensor network SOC | |
| CN103269267B (en) | Fully homomorphic encryption device | |
| Shuai et al. | Research of cipher chip core for sensor data encryption | |
| CN109495430A (en) | It is a kind of based on let out sequence encryption decipherment algorithm | |
| CN105933332B (en) | Transformer remote monitoring system with special encryption and decryption chip and working method thereof | |
| CN112994887B (en) | Communication encryption method and system suitable for power Internet of things terminal | |
| Kumar et al. | Secure fog computing system using emoticon technique | |
| CN113254981A (en) | Post-quantum-safe outsourcing privacy data publishing method and system | |
| CN105025032A (en) | Customer management server with encrypted authentication function | |
| Sravya et al. | The Ideal Block Ciphers-Correlation of AES and PRESENT in Cryptography | |
| CN104468535A (en) | Ciphertext storage and connecting query system and method suitable for cloud environment | |
| CN103618599B (en) | Data set encryption pre-treating method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20190222 |