CN102737270B - A kind of bank intelligent card chip secure coprocessor based on domestic algorithm - Google Patents
A kind of bank intelligent card chip secure coprocessor based on domestic algorithm Download PDFInfo
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Abstract
The present invention discloses a kind of bank intelligent card chip secure coprocessor based on domestic algorithm, it comprises: a storage unit, one control module, one SM1 algoritic module, one SM2 algoritic module, one SM3 algoritic module and a mould take advantage of module, wherein, described storage unit is used for described SM1 algoritic module, SM2 algoritic module and SM3 algoritic module and mould take advantage of module enable, control and data input and output, described SM1 algoritic module, SM2 algoritic module, after SM3 algoritic module and mould take advantage of one of them functional module of module enable, data and address output end are as the input end of described control module, according to address, by the output terminal of described control module, data are write the designated address space of described storage unit.The present invention can complete the comprehensive hardware solidification of state close SM1, SM2, SM3 and subfunction, and the method combined than software approach and soft or hard has more fast and the feature of higher security.
Description
Technical field
The present invention relates to field of information security technology, particularly be a kind of security coprocessor of the bank intelligent card chip based on domestic algorithm SM1, SM2 and SM3 algorithm.
Background technology
At present, domestic bank card mainly uses magnetic stripe card, but there is obvious deficiency: information storage is little, magnetic stripe easily reads and forge, confidentiality is poor, the data on magnetic stripe is easily stolen by offender, copy puppet emits the cost of card lower simultaneously, cause the various crime case relating to magnetic stripe card security frequently to occur, the safety problem of bank card causes holder to worry day by day.
State's close SM1SM2SM3 algorithm is that national Password Management office is for ensureing national information safety, the algorithm of the independent research of release.State's close SM1 algorithm is a kind of symmetry algorithm worked out by national Password Management office.State's close SM2 algorithm is a public key algorithm based on discrete logarithm elliptic curve disclosed in national Password Management office, comprise two element field and prime field, and with 256 or the lower bit wide of 192bit two kinds, realize digital signature/authentication, key agreement, the function of data encryption/decryption.Algorithm itself has that security is high, size of key is little, good etc. the advantage of dirigibility.State's close SM3 algorithm is a hash algorithm that national Password Management office releases, and Hash Value length is 256 bits.
Therefore, how to create a kind of security coprocessor using the IC bank card chip of the autonomous algorithm of China and industry security standards, be the research direction place of those skilled in the art.
Summary of the invention
An object of the present invention is to provide a kind of bank intelligent card chip secure coprocessor based on domestic algorithm, it is on the basis based on close SM1, SM2 and SM3 algorithm of state, multiplexing by storage unit and functional module, reach 1 card two algorithm, realize 1 people to support the two of terminal traffic both at home and abroad 1 card, meet the electronic wallet/electronic passbook of bank intelligent card, the function of debit/credit.
Another object of the present invention is to provide a kind of bank intelligent card chip secure coprocessor based on domestic algorithm, its be by address bus, data bus and control signal and CPU mutual, utilize state's close SM1, SM2, SM3 hardware circuit IP kernel, the mould of the large several RSA of 1024bit is provided to take advantage of hardware accelerator interface, complete the electronic wallet/electronic passbook to bank card, debit/credit application needed for information security function, meet the dual safety requirement of terminal traffic both at home and abroad, and meet other hardware requirements of national financial integrated circuit (IC) calliper model regulation.
In order to achieve the above object, the invention provides a kind of bank intelligent card chip secure coprocessor based on domestic algorithm, it is characterized in that, it comprises: a storage unit, a control module, a SM1 algoritic module, a SM2 algoritic module, a SM3 algoritic module and a mould take advantage of module, wherein
Described storage unit be used for described SM1 algoritic module, SM2 algoritic module and SM3 algoritic module and mould take advantage of module enable, control and data input and output, after described SM1 algoritic module, SM2 algoritic module, SM3 algoritic module and mould take advantage of one of them functional module of module enable, data and address output end are as the input end of described control module, according to address, by the output terminal of described control module, data are write the designated address space of described storage unit
Described SM1 algoritic module has hardware circuit IP kernel, for providing key distribution, the key encryption and decryption security function of 128bit.
Described SM2 algoritic module has hardware circuit IP kernel, for providing the digital signature/authentication of the public key system of 256bit or 192bit two kinds of bit wides, two element fields or prime fields two kinds of algorithms, key agreement, the security function of data encryption.
Described SM3 algoritic module has hardware circuit IP kernel, and it is the submodule of described SM2 algoritic module, for providing HASH algorithm, is less than 2 to length L
64the message of bit, exports 256bit Hash Value;
Described mould takes advantage of module to have hardware circuit IP kernel, and it is the submodule of described SM2 algoritic module, and the mould that also can be used for the large several RSA Algorithm of 1024bit takes advantage of hardware accelerator function.
Preferably in embodiment, be provided with control word register in described storage unit, the control word in described control register comprises control bit and the SM2 algoritic module parameter of above-mentioned each module.
Preferably in embodiment, described SM2 algoritic module provides the mould of the large several RSA of 1024bit to take advantage of hardware accelerator interface.
Preferably in embodiment, described SM3 algoritic module, mould take advantage of module and SM2 algoritic module to share the input end be connected with described storage unit, share the data output end with described control module.
Preferably in embodiment, described SM3 module is the submodule of described SM2 algorithm unit, and its output terminal returns to described SM2 algoritic module, or directly returns to described storage unit, for CPU (central processing unit) reads.
Preferably in embodiment, described mould takes advantage of module to be the submodule of described SM2 algorithm unit, and its output terminal returns to described SM2 algoritic module, or directly returns to described storage unit, is that CPU (central processing unit) reads.
Compared with prior art, beneficial effect of the present invention is:
The present invention is to provide the hardware implementations of close SM1, SM2, SM3 algorithm of a kind of state, complete the application of state close SM1, SM2 and SM3 algorithm in bank card of new generation, it is the security coprocessor of the IC bank card chip using the autonomous algorithm of China and industry security standards completely, can complete the comprehensive hardware solidification of state close SM1, SM2, SM3 and subfunction, the method combined than software approach and soft or hard has more fast and the feature of higher security; Need the characteristic used both at home and abroad for bank intelligent card, SM2 provides the mould of the large several RSA Algorithm of 1024bit to take advantage of interface, meets the hsrdware requirements of the information security algorithm of International Banks smart card; The present invention is the double-point information safety requirements that 1 card/people completes terminal traffic both at home and abroad, and provide hardware possibility, the promotion and application for state close SM1, SM2, SM3 algorithm have very large value.CPU, by data bus, to the mutual write/read data of storage unit, can complete SM1 key distribution, SM1 key encryption and decryption, SM2 digital signature/authentication, SM2 key agreement, SM2 data encryption/decryption, the enable control of the several functions that SM3 message hash and 1024bit mould are taken advantage of.Wherein SM2 module can the selection of 2 yuan of territories or prime field elliptic curve in Galois field, completes the selection of 256 and 192 two kind of bit wide.
Accompanying drawing explanation
Fig. 1 is CPU (central processing unit) of the present invention and the mutual schematic diagram of security coprocessor;
Fig. 2 is security coprocessor detailed architecture figure of the present invention;
Fig. 3 is that security coprocessor memory space address of the present invention distributes schematic diagram;
Fig. 4 is security coprocessor control word data structure schematic diagram of the present invention.
Description of reference numerals: 1-coprocessor; 11-storage unit; 12-control module; 13-SM1 algoritic module; 14-SM2 algoritic module; 15-SM3 algoritic module; 16-mould takes advantage of module (MMUL module); 2-CPU (central processing unit).
Embodiment
Below in conjunction with accompanying drawing, to above-mentioned being described in more detail with other technical characteristic and advantage of the present invention.
The present invention is the security algorithm coprocessor of the bank intelligent card chip based on domestic commercial algorithm SM1, SM2 and SM3 algorithm of national Password Management office release.It is based on the close algorithm of state, meets bank intelligent card pboc2.0 specification, meets the double-point information security algorithm demand of terminal traffic both at home and abroad in the mode of the hardware co-processor of single deck tape-recorder two algorithm.
Consulting Fig. 1 and Fig. 2, is CPU (central processing unit) of the present invention and the mutual schematic diagram of coprocessor and coprocessor composition frame chart; Coprocessor 1 of the present invention passes through address bus, data bus and control signal and CPU (central processing unit) 2 (CPU, CentralProcessingUnit) is mutual, for alleviating the Processing tasks of CPU (central processing unit) 2, improves the speed of system.
Described coprocessor 1 comprises storage unit 11, control module 12, SM1 algoritic module 13, SM2 algoritic module 14, SM3 algoritic module 15, mould and takes advantage of module (MMUL module) 16.
Described storage unit 11 is as the interface of CPU (central processing unit) 2 with coprocessor 1 internal arithmetic unit, control word register 111 is provided with in it, for to described SM1 algoritic module 13, SM2 algoritic module 14 and SM3 algoritic module 15 and mould take advantage of module 16 enable, control and data input and output, when the 32bit control word in control word register 111 is supplied to described SM1 algoritic module 13, SM2 algoritic module 14 and SM3 algoritic module 15, mould takes advantage of one of them functional module enable signal of module 16 to be 1, described SM1 algoritic module 13, SM2 algoritic module 14 and SM3 algoritic module 15, after mould takes advantage of module 16 enable, data and address output end are as the input end of described control module, according to address, by the output terminal of control module 12, data are write the designated address space of described storage unit 11.
Above-mentioned SM1 algoritic module 13 has hardware circuit IP kernel, for providing key distribution, the key encryption and decryption security function of 128bit; The security mechanism of the electronic wallet/electronic passbook that specific implementation country financial integrated circuit (IC) calliper model PBOC2.0 standard specifies comprises: key dispersion, safe packet encryption and decryption, safe packet MAC calculate and transaction MAC/TAC/GMAC/GTAC calculating, realize the function that single deck tape-recorder meets terminal traffic demand both at home and abroad.
Described SM2 algoritic module 14 has hardware circuit IP kernel, for providing the digital signature/authentication of the public key system of 256bit or 192bit two kinds of bit wides, two element fields or prime fields two kinds of algorithms, key agreement, the security function of data encryption; It has simultaneously 2 yuan of territories or p unit territory, 256 or 192bit 4 kinds of Selecting parameter, complete the security mechanism of digital signature/authentication in the application of bank card debit/credit, key agreement or data encryption/decryption function.
Described SM3 algoritic module 15 has hardware circuit IP kernel, and it is the submodule of described SM2 algoritic module 14, for providing HASH algorithm, is less than 2 to length L
64the message of bit, exports 256bit Hash Value.
Described mould takes advantage of module 16 to have hardware circuit IP kernel, and it is the submodule of described SM2 algoritic module 14, and the mould that also can be used for the large several RSA Algorithm of 1024bit takes advantage of hardware accelerator function.Described SM2 algorithm 14 provides the mould of the large several RSA of 1024bit to take advantage of hardware accelerator interface, completes and realizes the large several RSA Algorithm of 1024bit in the mode of soft or hard combination, realize single deck tape-recorder two algorithm, meet the demand of the International Terminal business of 1 card/people.
Bank intelligent card chip secure coprocessor 1 of the present invention, the function that its synchronization completes SM1 algoritic module 13, SM2 algoritic module 14 and SM3 algoritic module 15, mould takes advantage of module 16, above-mentioned SM1 algoritic module 13, SM2 algoritic module 14, SM3 algoritic module 15 and mould take advantage of each Algorithm IP of module 16 to read in respective input parameter and data by storage unit 11, export respective result.Described CPU (central processing unit) 2 is called by read/write memory cell 11 and is controlled each algoritic module IP kernel, and reads the Output rusults of each algoritic module IP kernel.Control word in the control register of storage unit 11 comprises control bit and the SM2 algoritic module parameter of above-mentioned each algoritic module.
Continue to consult shown in Fig. 2, SM3 algoritic module 15 of the present invention and mould take advantage of module 16 to be the submodule of SM2 algoritic module 14.The output terminal of SM3IP core, as the submodule of SM2IP core, returns to SM2IP core, and in addition, the output terminal of SM3IP core directly returns to storage unit 11, for CPU (central processing unit) 2 reads, completes 256bit message hash security mechanism; Mould takes advantage of the output terminal of module 16, as the submodule of SM2IP core, return to SM2IP core, in addition, mould takes advantage of the output terminal of module 16 directly to return to storage unit 11, for CPU (central processing unit) 2 reads, SM2IP core provides mould to take advantage of the interface of hardware accelerator, complete and realize the large several RSA Algorithm of 1024bit in the mode of soft or hard combination, realize single deck tape-recorder two algorithm, meet the demand of the International Terminal business of 1 card/people.
For SM3 algoritic module 15 and mould in the present invention take advantage of module 16 as the submodule of SM2 algoritic module 14,3 modules share the input end be connected with storage unit 11, share the data output end with control module 12; When SM2 algoritic module 13 is enable, its fan-in factor according to then from SM2 inside, otherwise, its fan-in factor according to the control word from storage unit 11, the output terminal of its output terminal inner and SM2 algoritic module 13 of Direct driver SM2 algoritic module 13 simultaneously.
Consult Fig. 2, Fig. 3, described storage unit 6 is the storage space that described SM1, SM2, SM3 and MMUL functional module shares (1+8*13) * 32bit, addressing space XX08H-XX77H; 32bit control word on the XX08H of its address is supplied to described SM1 algoritic module 13, SM2 algoritic module 14, SM3 algoritic module 15 and mould and takes advantage of one of them functional module enable signal of module 16 to be 1.After described SM1, SM2, SM3 and MMUL functional module is enable, data and address output end are as the input end of described control module 12, and according to address, the fan-out factor of control module 12 is according to the designated address space of the described storage unit 11 of write.
Consult Fig. 3, Fig. 4, the control word register on the XX08H address of described storage unit 11, enctrl [1:0] equals 2 ' b00, then SM1 algoritic module 13 is enable; Equal 2 ' b01, then SM2 algoritic module 14 is enable; Equal 2 ' b10, then SM3 algoritic module 15 is enable; Equal 2 ' b11, then mould takes advantage of module 16 enable; Smctrl [1:0], when SM1 is enable, equals 2 ' b10, then performs key distribution; Equal 2 ' b11, then perform key encryption and decryption.When SM2 algoritic module 14 is enable, equal 2 ' b01, then combine digital signature/authentication; Equal 2 ' b10, then perform key agreement; Equal 2 ' b11, then perform data encrypting and deciphering.When SM3 algoritic module 15 is enable, equal 2 ' b00, then message is continued; Equal 2 ' b11, then last 256,*13 mono-group of message.Encryption and decryption control bit dectrl, equals 1 ' b0, then each module performs corresponding cryptographic calculation; Equal 1 ' b1, perform decrypt operation.25 to 7bit position is the special control bit of SM2 algoritic module, is followed successively by from low to high: Galois field control bit gfctrl, and equaling 1 ' b0 is prime field; Equaling 1 ' b1 is two element field.Bit wide control bit fxctrl, equals 1 ' b0, then perform 192bit data; Equal 1 ' b1, then perform 256bit data.8bit data length klen, the ID length entl of 8bit, h.31 3bit complementary divisor is SM2 algoritic module two element field point most significant digit exclusive data position to 26bit position, and position is followed successively by from low to high: gf2xr and gf2yr of some R, gf2xp and gf2yp of some P, gf2xg and gf2yg of some G.
In sum, the present invention is to provide the hardware implementations of close SM1, SM2, SM3 algorithm of a kind of state, complete the application of state close SM1, SM2 and SM3 algorithm in bank card of new generation, it is the security coprocessor of the IC bank card chip using the autonomous algorithm of China and industry security standards completely, can complete the comprehensive hardware solidification of state close SM1, SM2, SM3 and subfunction, the method combined than software approach and soft or hard has more fast and the feature of higher security; Need the characteristic used both at home and abroad for bank intelligent card, SM2 provides the mould of the large several RSA Algorithm of 1024bit to take advantage of interface, meets the hsrdware requirements of the information security algorithm of International Banks smart card; The present invention is the double-point information safety requirements that 1 card/people completes terminal traffic both at home and abroad, and provide hardware possibility, the promotion and application for state close SM1, SM2, SM3 algorithm have very large value.CPU, by data bus, to the mutual write/read data of storage unit, can complete SM1 key distribution, SM1 key encryption and decryption, SM2 digital signature/authentication, SM2 key agreement, SM2 data encryption/decryption, the enable control of the several functions that SM3 message hash and 1024bit mould are taken advantage of.Wherein, SM2 module can the selection of 2 yuan of territories or prime field elliptic curve in Galois field, completes the selection of 256 and 192 two kind of bit wide.
More than illustrate just illustrative for the purpose of the present invention, and nonrestrictive, and those of ordinary skill in the art understand; when not departing from the spirit and scope that following claims limit, many amendments can be made, change; or equivalence, but all will fall within the scope of protection of the present invention.
Claims (3)
1. based on a bank intelligent card chip secure coprocessor for domestic algorithm, it is characterized in that, it comprises: a storage unit, a control module, a SM1 algoritic module, a SM2 algoritic module, a SM3 algoritic module and a mould take advantage of module, wherein,
Described storage unit is used for described SM1 algoritic module, SM2 algoritic module and SM3 algoritic module and mould take advantage of module enable, control and data input and output, described SM1 algoritic module, SM2 algoritic module, after SM3 algoritic module and mould take advantage of one of them functional module of module enable, data and address output end are as the input end of described control module, according to address, by the output terminal of described control module, data are write the designated address space of described storage unit, control word register is provided with in described storage unit, control word in described control register comprises above-mentioned SM1 algoritic module, SM2 algoritic module, SM3 algoritic module and mould take advantage of control bit and the SM2 algoritic module parameter of module,
Described SM1 algoritic module has hardware circuit IP kernel, for providing key distribution, the key encryption and decryption security function of 128bit,
Described SM2 algoritic module has hardware circuit IP kernel, for providing the digital signature/authentication of the public key system of 256bit or 192bit two kinds of bit wides, two element fields or prime fields two kinds of algorithms, key agreement, the security function of data encryption,
Described SM3 module is the submodule of described SM2 algorithm unit, its output terminal returns to described SM2 algoritic module, or directly return to described storage unit, for CPU (central processing unit) reads, described SM3 algoritic module has hardware circuit IP kernel, it is the submodule of described SM2 algoritic module, for providing HASH algorithm, is less than 2 to length L
64the message of bit, exports 256bit Hash Value,
Described mould takes advantage of module to be the submodule of described SM2 algorithm unit, its output terminal returns to described SM2 algoritic module, or directly return to described storage unit, for CPU (central processing unit) reads, described mould takes advantage of module to have hardware circuit IP kernel, it is the submodule of described SM2 algoritic module, and the mould also for completing the large several RSA Algorithm of 1024bit takes advantage of hardware accelerator function.
2. the bank intelligent card chip secure coprocessor based on domestic algorithm according to claim 1, is characterized in that, described SM2 algoritic module provides the mould of the large several RSA of 1024bit to take advantage of hardware accelerator interface.
3. the bank intelligent card chip secure coprocessor based on domestic algorithm according to claim 1, it is characterized in that, described SM3 algoritic module, mould take advantage of module and SM2 algoritic module to share the input end be connected with described storage unit, share the data output end with described control module.
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| CN103049710B (en) * | 2012-12-13 | 2017-02-08 | 国家广播电影电视总局广播科学研究院 | Field-programmable gate array (FPGA) chip for SM2 digital signature verification algorithm |
| CN103793199B (en) * | 2014-01-24 | 2016-09-07 | 天津大学 | A kind of fast rsa password coprocessor supporting dual domain |
| CN104602015A (en) * | 2014-12-31 | 2015-05-06 | 西安蒜泥电子科技有限责任公司 | Real-time video monitoring encryption and authentication method |
| CN105391736A (en) * | 2015-12-11 | 2016-03-09 | 捷德（中国）信息科技有限公司 | Transaction dynamic data authentication method and system |
| CN107124277B (en) * | 2016-02-25 | 2023-08-11 | 上海航天智能装备有限公司 | Hard copy control system based on national commercial cryptographic algorithm |
| CN107767141A (en) * | 2016-08-15 | 2018-03-06 | 张健 | A kind of System and method for based on cell phone application inquiry commodity true and false |
| CN108322308B (en) * | 2017-12-14 | 2021-01-12 | 天津津航计算技术研究所 | Hardware implementation system of digital signature algorithm for identity authentication |
| CN113892103A (en) * | 2020-04-16 | 2022-01-04 | 华为技术有限公司 | Apparatus and method for performing encryption/decryption processing |
| CN112818415A (en) * | 2020-12-31 | 2021-05-18 | 杭州趣链科技有限公司 | Cryptographic calculation method, system and medium based on APSoC |
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