CN109347474B - Signal time sequence configuration method and device, computer equipment and storage medium - Google Patents
Signal time sequence configuration method and device, computer equipment and storage medium Download PDFInfo
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- CN109347474B CN109347474B CN201811137392.0A CN201811137392A CN109347474B CN 109347474 B CN109347474 B CN 109347474B CN 201811137392 A CN201811137392 A CN 201811137392A CN 109347474 B CN109347474 B CN 109347474B
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- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
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Abstract
The invention relates to a signal time sequence configuration method, a device, a computer device and a storage medium, wherein the method comprises the steps of defining a group of instructions; storing the instructions in the memory addresses in sequence; when the interface circuit is used, instructions are sequentially acquired from the specified memory addresses according to the state of the interface circuit; and driving the interface circuit to execute corresponding operation according to the instruction. The invention forms the level state of the interface signal into a string of numerical values by defining the instruction, and stores the numerical values in the memory address in the form of the instruction according to different states.
Description
Technical Field
The present invention relates to an interface circuit, and more particularly, to a signal timing configuration method, apparatus, computer device, and storage medium.
Background
The operation of the interface is performed according to a signal with a certain timing sequence, taking the interface timing sequence of the NAND Flash controller circuit and the NAND PHY circuit in the chip as an example, the signal timing requirement of the NAND PHY interface command sending stage is, as shown in fig. 1, to achieve this requirement, normally five counters 0 to 4 are provided in the circuit, and the threshold value for each counter to count is preset, several interface signals of the interface are sequentially set to cebar, cle, ale, webar, rebar, sdr _ cycle, rddate _ en, wrdata _ valid, and wrdqs _ en, the cebar interface signal is pulled down at time t0, the cle interface signal is pulled up, the wrdata _ valid interface signal is output, the wrdata _ valid interface signal is pulled up, the wrdqs _ en interface signal is pulled down, the counter0 is started, when the counter0 counts to the preset threshold value, at this time, the counter is pulled down at the time 1, the counter1 is started, when the counter1 counts to a predetermined threshold, which is just t2, the webbar interface signal is pulled high, and the counter2 is started, and so on, thereby implementing the predetermined signal timing sequence shown in fig. 1.
However, the current arrangement of the interface signal timing is limited and lacks flexibility, for example, at time t0, the cebar interface signal is pulled down by hardware fixation, the cle interface signal is pulled up, the wrdatatavalid interface signal is pulled up, and the wrdqs _ en interface signal is pulled down, but if the NAND PHY protocol is upgraded, these interface signals need to be changed at different times, the hardware circuit cannot be realized, and for example, the counter0 realizes counting from time t0 to time t1, but if the NAND PHY protocol is upgraded, the interval Δ t1 from time t0 to time t1 becomes very large, and the bit width of the timer 0 of the hardware circuit is not enough, so that such timing requirement cannot be realized.
Therefore, it is necessary to design a new method to achieve the flexibility and configurability of the interface signal timing.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides a signal time sequence configuration method, a signal time sequence configuration device, computer equipment and a storage medium.
In order to achieve the purpose, the invention adopts the following technical scheme: the signal time sequence configuration method comprises the following steps:
defining a set of instructions;
storing the instructions in memory addresses in sequence;
when the interface circuit is used, instructions are sequentially acquired from the specified memory addresses according to the state of the interface circuit;
and driving the interface circuit to execute corresponding operation according to the instruction.
The further technical scheme is as follows: the defining a set of instructions includes:
defining all operation instructions of each state in the interface circuit;
defining a waiting instruction;
an operation end instruction is defined.
The further technical scheme is as follows: all the operation instructions defining each state in the interface circuit comprise:
acquiring the expected value of all interface signals in each clock period of each state in the interface circuit from the interface circuit protocol document;
and sequentially forming a string of numerical values of each state of the interface circuit according to all expected values of the same state in the same clock cycle so as to obtain all operation instructions of each state in the interface circuit.
The further technical scheme is as follows: the sequentially storing the instructions in the memory addresses includes:
sequencing the instructions of all states in the interface circuit according to the clock period;
and sequentially storing the sequenced instructions in the corresponding memory addresses.
The further technical scheme is as follows: when the interface circuit is used, the instructions are sequentially acquired from the specified memory address according to the state of the interface circuit, and the interface circuit comprises the following steps:
when in use, the current state of the interface circuit is obtained;
and sequentially acquiring the instructions in the corresponding memory addresses from the current state of the interface circuit.
The further technical scheme is as follows: the driving of the interface circuit according to the instruction to execute the corresponding operation comprises:
setting each interface signal of the interface circuit in turn according to the instruction obtained from the memory address;
judging whether the current instruction is an operation ending instruction or not;
if so, switching the state of the interface circuit, and when returning to the use, sequentially acquiring instructions from the specified memory address according to the state of the interface circuit;
if not, returning to the step of setting each interface signal of the interface circuit in sequence according to the instruction obtained from the memory address.
The further technical scheme is as follows: before the defining a set of instructions, the method further comprises:
an interface signal connected to the preceding stage circuit is set.
The invention also provides a signal timing configuration device, comprising:
an instruction definition unit for defining a set of instructions;
the storage unit is used for sequentially storing the instructions in the memory addresses;
the acquisition unit is used for sequentially acquiring instructions from the specified memory addresses according to the state of the interface circuit when in use;
and the execution unit is used for driving the interface circuit to execute corresponding operation according to the instruction.
The invention also provides computer equipment which comprises a memory and a processor, wherein the memory is stored with a computer program, and the processor realizes the method when executing the computer program.
The invention also provides a storage medium storing a computer program which, when executed by a processor, is operable to carry out the method as described above.
Compared with the prior art, the invention has the beneficial effects that: the invention forms the level state of the interface signal into a string of numerical values by defining the instruction, and stores the numerical values in the memory address according to different states in the form of the instruction, when in use, the instruction is sequentially taken out from the corresponding memory address according to different states, the interface signal is driven to carry out high-low level output according to the numerical value of the instruction, when the taken-out instruction is an operation ending instruction, the instruction is stopped being taken out from the memory address, and the state of the interface circuit is switched to read the instruction of the next state, and the interface signal time sequence of the interface circuit can be changed by modifying the numerical value of the instruction stored in the memory address, thereby realizing the flexibility and configurability of the interface signal time sequence.
The invention is further described below with reference to the accompanying drawings and specific embodiments.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the description below are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a signal timing diagram illustrating a command transmission phase of a NAND PHY interface of the prior art;
fig. 2 is a schematic flow chart illustrating a signal timing configuration method according to an embodiment of the present invention;
fig. 3 is a schematic interface signal diagram of a signal timing configuration method according to an embodiment of the present invention;
FIG. 4 is a schematic diagram illustrating a signal timing comparison of data writing status of a signal timing configuration method according to an embodiment of the present invention;
FIG. 5 is a signal timing diagram illustrating a data write status of a signal timing configuration method according to an embodiment of the present invention;
FIG. 6 is a diagram illustrating the definition and storage of instructions provided by an embodiment of the present invention;
FIG. 7 is a diagram illustrating a relationship between signal timing and commands according to an embodiment of the present invention;
fig. 8 is a schematic diagram illustrating interface state skipping of a signal timing configuration method according to an embodiment of the present invention;
FIG. 9 is a schematic diagram of a signal timing diagram of a command transmitting status according to a signal timing configuration method provided in an embodiment of the invention;
fig. 10 is a schematic diagram of a signal timing diagram of an address sending status according to an embodiment of the present invention;
fig. 11 is a flowchart illustrating a signal timing configuration method according to another embodiment of the invention;
FIG. 12 is a block diagram of a signal timing configuration apparatus according to an embodiment of the present invention;
fig. 13 is a schematic block diagram of a computer device provided in an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, belong to the protection scope of the present invention.
It will be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It is also to be understood that the terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in this specification and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should be further understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.
The embodiment of the invention provides a schematic flow chart of a signal time sequence configuration method. The signal time sequence configuration method is applied to a server. The server may be a server in a distributed service platform, and a user may modify and reset an instruction stored in a memory of the server, so that an interface signal of the interface circuit is changed according to the instruction.
It should be noted that only one server is illustrated in fig. 2, and in the actual operation process, a plurality of servers may be simultaneously operated
Fig. 2 is a flowchart illustrating a signal timing configuration method according to an embodiment of the present invention. As shown in fig. 2, the method includes the following steps S110 to S140.
S110, defining a group of instructions.
In this embodiment, the instruction refers to a string of values stored in a memory, the bit width of the memory is 11 bits, the instruction with the bit width of 11 bits is stored, and each address stores one instruction.
Specifically, assuming that there are N interface signals in the set, the memory bit width is (N +1), and each bit of the lower N bits in the bit width of (N +1) bits stores exactly one expected value of the interface signal.
The memory depth corresponds to a time axis, after the interface circuit is triggered to start, the 1 st clock cycle takes out the numerical values of (N +1) bits in the address0 of the memory and outputs the numerical values of the lower N bits to the interface, the 2 nd clock cycle takes out the numerical values of the (N +1) bits in the address of the memory address1 and outputs the numerical values of the lower N bits to an interface signal of the interface circuit, and so on, so that a predetermined signal sequence is output.
Specifically, the step may be defined manually by a development engineer according to the interface protocol document, or may be defined automatically.
In an embodiment, the step S110 may include steps S111 to S113.
And S111, defining all operation instructions of each state in the interface circuit.
The operation instruction is an instruction for driving an interface signal in the interface circuit to carry out level switching according to the value of the interface signal; the operation command outputs the values Bit 9-Bit 0 with lower 10 bits to the corresponding interface signals, Bit 9-Bit 0 represent the expected values of the interface signals cebar-wrdqs _ en, and when the operation command is output, the interface signals correspondingly switch the levels of the interface signals according to the values specified by the operation. Specifically, the format of the operation command is that the highest bit is 0, and the rest is determined according to the actual levels of all the signal interfaces, wherein the high level is 1, and the low level is 0.
In one embodiment, the step S111 may include steps S1111 to S1112.
S1111, acquiring expected values of all interface signals in each clock cycle of each state in the interface circuit.
As shown in fig. 7, the corresponding values of each operation instruction are different, and therefore, it is necessary to obtain the expected values of all the interface signals in each clock cycle of each state in the interface circuit, and the values composed of the expected values are used as the operation instructions.
S1112, sequentially forming a string of values for each state of the interface circuit according to all expected values of the same state in the same clock cycle, so as to obtain all operation instructions of each state in the interface circuit.
Specifically, a series of values is formed according to the sequence of each interface signal according to all expected values in the same clock cycle of the same state, and the clock cycle for switching the expected values of each state in the interface circuit obtains the values in the above manner to form all operation instructions of each state in the interface circuit.
For example, the value of 0_0001110001 is composed of all the expected values at time t 0; all expected values at time t1 make up a value of 0_ 0001100001.
And S112, defining a waiting instruction.
In this embodiment, the wait for designation means that each interface signal of the current interface circuit keeps the previous level unchanged until a new instruction enters; the wait instruction waits for the clock cycles specified by the 10-Bit values Bit 9-Bit 0, during which the interface signal values are not changed, the format of the wait instruction is that the most significant Bit is 1 and the rest are not all 0.
And S113, defining an operation ending instruction.
In this embodiment, the operation ending instruction refers to an instruction that the operation ends and the interface circuit switches to the next state, specifically, the format of the operation ending instruction is that the highest order bit is 1, and the rest are all 0. If the interface circuit fetches the operation ending instruction from the memory address, the interface circuit stops continuously reading the instruction in the memory address, the interface circuit is triggered to end the state, the next state is entered, and the interface signal is kept unchanged.
The interface circuit will fetch instructions sequentially from a specified entry address (e.g., addr (m +0)), and fetch one instruction per clock cycle (except for the wait instruction), so that the sequential operation instructions and wait instructions can constitute the timing requirements of all cebar-wrdqs _ en interface signals. The waiting time of the waiting instruction can be set according to the actual situation, and the waiting time of waiting for how many clock cycles to fetch the instruction again after the waiting instruction is fetched is set according to the actual situation.
The change of the interface signal is controlled by an operation instruction, the holding of the interface signal is realized by a wait instruction, and the above instruction is defined as shown in fig. 6, and represents cebar, cle, ale, webar, rebar, srr _ cycle, rddate _ en, wrdata _ valid, and wrdqs _ en in sequence from 9 bits to 0 bits.
And S120, sequentially storing the instructions in the memory addresses.
In this embodiment, the instructions are sequentially stored in the memory addresses according to the sequence described in fig. 6, when the interface circuit starts to work, the corresponding instructions are taken out from the specified memory addresses, so that the setting of the interface signal can be realized, and if the level of the interface signal needs to be modified according to the actual situation, only the instructions stored in the memory addresses need to be modified; the flexibility and configurability of the interface signal timing sequence are high, so that the interface circuit can obtain the instruction from the memory address.
In one embodiment, the step S120 may include steps S121 to S122.
S121, sequencing the instructions of all states in the interface circuit according to a clock cycle;
and S122, sequentially storing the sequenced instructions in the corresponding memory addresses.
In this embodiment, the instructions are constructed in advance, and when the chip performs the initialization process in cold boot, the instructions are stored to the specified memory address under the guidance of the firmware, as shown in fig. 5, the first instruction is an addr (m +0) address where the operation instruction (0_0001110001) is stored in the memory, and the following instructions are stored in sequence. After initialization, all the required instructions are stored in the memory, as shown in fig. 6.
And S130, when the interface circuit is used, sequentially acquiring instructions from the specified memory address according to the state of the interface circuit.
In practical use, the corresponding instruction is obtained from the appointed memory address according to each state of the interface circuit, specifically, if the interface protocol is complex and has a plurality of groups of different time sequences, a plurality of state machine states are designed, after each state machine is started, the interface circuit fetches the instruction from the corresponding memory entry address, sends out a signal time sequence, stops fetching the instruction when the operation end instruction is fetched, and triggers the state machine to jump to the next state, so that the interface circuit fetches the instruction from the memory entry address corresponding to the new state and sends out a new signal time sequence, thereby realizing a more complex multi-time sequence interface.
In an embodiment, the step S130 may include steps S131 to S132.
S131, acquiring the current state of the interface circuit when in use;
as shown in fig. 10, the working process in the NAND PHY interface protocol includes eight stages, which can be summarized into three timing states, namely a command sending state, an address sending state, and a data writing state; the timing diagrams of the signals corresponding to each state are different, and therefore, it is necessary to fetch instructions from different addresses in the memory for different states.
S132, sequentially acquiring the instructions in the corresponding memory addresses from the current state of the interface circuit.
As shown in fig. 5, 9, and 10, signal timings of three states, i.e., a data write state, a command transmission state, and an address transmission state, are shown. For example, referring to fig. 5 in combination with fig. 7, when the interface circuit is activated to perform a data writing state, instructions are sequentially fetched from an addr (m +0) address of the memory, a first operation instruction (0_0001110001) is fetched in a first clock cycle, and cebar-wrdqs _ en interface signals are set to values required by the instructions, that is, 0001110001; taking out a waiting instruction (1_0000000010) in the next clock cycle, and waiting for 2 clock cycles according to the instruction requirement; then, an operation instruction (0_0001100001) is fetched in the next clock cycle, and cebar-wrdqs _ en interface signals are set to be values required by the instruction, namely 0001100001; by analogy, outputting a specified signal sequence; and stopping fetching the instruction until an operation ending instruction (1_0000000000) is met, and triggering the state machine to switch the state of the interface circuit to the next state so as to read the instruction in the next state.
When the interface circuit starts a working process, the circuit state machine jumps from an IDLE state to a CMD _ PHASE state, the circuit performs value taking from addr0 of a memory in the state, sends out an interface timing sequence of a set command sending state, stops when an operation ending instruction is met, and triggers the CMD _ PHASE state to end; then the circuit state machine jumps to an ADDR _ PHASE state, the circuit takes a value from ADDR (n +0) of a memory to execute in the state, an interface time sequence of a set address sending state is sent, the operation is stopped when an operation ending instruction is met, and the ADDR _ PHASE state is triggered to end; the interface circuit state machine jumps to the next ADDR _ PHASE state and so on. In summary, a complex signal sequence can be constructed by combining a state machine with an instruction sequence corresponding to each state. Therefore, the level of each interface signal can be specified only by adjusting the value of the operation instruction; the interval time between signals can be controlled by adjusting the value of the waiting instruction, and a plurality of waiting instructions can be continuously set until the time interval requirement is met due to the fact that one waiting instruction is not enough. In summary, any required signal timing can be constructed by three types of instructions.
And S140, driving the interface circuit to execute corresponding operation according to the instruction.
In this embodiment, the value of the command represents the level state of all interface signals in the interface circuit.
In an embodiment, the step S140 may include steps S141 to S143.
S141, sequentially setting each interface signal of the interface circuit according to the instruction obtained from the memory address;
s142, judging whether the current instruction is an operation ending instruction or not;
s143, if yes, switching the state of the interface circuit, and returning to the step S130;
if not, the process returns to step S141.
The interface circuit is triggered to automatically output a series of expected values of each signal stored in the memory in turn to the circuit interface. Because the value in the memory is configurable, the flexible configuration of the interface signal time sequence is realized.
Assuming that the set of interface signals has N, the memory bit width is (N +1), and each bit of the lower N bits in the (N +1) bit width just stores the expected value of one interface signal; the memory depth corresponds to a time axis, after the interface circuit is triggered to start, the 1 st clock cycle takes out (N +1) bit values in the memory address0 and outputs the lower N bit values to the interface, the 2 nd clock cycle takes out (N +1) bit values in the memory address1 and outputs the lower N bit values to the interface, and so on, thus outputting a set signal sequence.
If the state of the interface signal will remain unchanged for a certain time, a wait instruction is defined for this situation, when the highest bit in the (N +1) bit width data in the memory is 1, the lower N bits are the number of clock cycles to wait (which cannot be equal to 0), after the interface circuit fetches such an instruction from the memory, the highest bit is found to be 1, the value of the lower N bits will not be output to the interface, but the interface signal is allowed to keep the previous value, wait for the specified clock cycle, and then fetch a new instruction until the next memory address. If the highest bit in the (N +1) bit width data in the memory is 1 and the rest is all 0, defining the highest bit as an operation ending instruction, ending the group of operations, and if a hardware circuit acquires the ending instruction, not continuing to take the numerical value of a memory address; if the interface protocol is complex and has a plurality of groups of different time sequences, a plurality of state machine states are designed, after each state machine is started, the interface circuit takes values from the corresponding memory entry address, sends a signal time sequence, stops taking values when an ending instruction is obtained, and triggers the main state machine to jump to the next state, so that the hardware circuit takes values from the memory entry address corresponding to the new state and sends a new signal time sequence, and therefore the more complex multi-time sequence interface is realized. The time sequence of the interface signal can be flexibly configured, once the interface protocol is upgraded, a circuit does not need to be modified, only the numerical value stored in the memory needs to be modified by software, the hardware development cost is saved, the time for the product to appear on the market is shortened, and the same hardware can support a new protocol after the software is upgraded. The method provides the maximum flexibility for the interface signals, the time sequence change of each signal can be controlled independently, and the flexible and adjustable effect is realized by modifying numerical values under the condition of not changing a circuit.
The signal time sequence configuration method comprises the steps of defining an instruction, forming a series of numerical values by the level state of an interface signal, storing the series of numerical values in a memory address in the form of the instruction according to different states, sequentially taking out the instruction from the corresponding memory address according to different states when the signal is used, driving the interface signal to output high and low levels according to the numerical values of the instruction, stopping taking the instruction from the memory address when the instruction is taken out as an operation ending instruction, switching the state of an interface circuit to read the instruction of the next state, changing the interface signal time sequence of the interface circuit by modifying the numerical values of the instruction stored in the memory address, and realizing the flexibility and configurability of the interface signal time sequence.
Fig. 11 is a flowchart illustrating a signal timing configuration method according to another embodiment of the present invention. As shown in fig. 11, the signal timing configuration method of the present embodiment includes steps S210 to S250. Steps S220 to S250 are similar to steps S110 to S140 in the above embodiments, and are not described herein again. The added step S210 in the present embodiment is explained in detail below.
And S210, setting an interface signal connected with the front stage circuit.
Specifically, a research and development engineer sets an interface signal connected to a preceding stage circuit when designing the circuit. As shown in fig. 3, the wrdata signal is of a bus type and its value is not a fixed value, but is supplied by the previous stage circuit module via the wrdata _ pre interface signal, each time differently. Therefore, an interface signal wrdata _ pop _ internal needs to be introduced to solve the wrdata bus signal problem. In view of the particularity of wrdata, a wrdata _ pop _ internal interface signal is introduced. This signal is not output to the interface but is connected to the preceding circuit block, and when it is 1, the interface circuit latches wrdatapre given from the preceding circuit block to the wrdataoutput, while the preceding circuit block will output the next wrdatapre. As shown in fig. 4 below, this signal is always one clock tick ahead of the wrdata _ valid signal.
Fig. 12 is a schematic block diagram of a signal timing configuration apparatus 300 according to an embodiment of the present invention. As shown in fig. 12, the present invention further provides a signal timing configuration apparatus 300 corresponding to the above signal timing configuration method. The signal timing configuration apparatus 300 includes a unit for performing the signal timing configuration method, and the apparatus may be configured in a server or a chip.
Specifically, referring to fig. 12, the signal timing configuration apparatus 300 includes:
an instruction definition unit 301 for defining a set of instructions;
a storage unit 302, configured to store the instructions in the memory addresses in sequence;
an obtaining unit 303, configured to sequentially obtain instructions from a specified memory address according to a state of an interface circuit when the interface circuit is in use;
and the execution unit 304 is configured to drive the interface circuit to execute a corresponding operation according to the instruction.
In one embodiment, the instruction definition unit 301 includes:
an operation instruction definition subunit, configured to define all operation instructions of each state in the interface circuit;
the waiting instruction definition subunit is used for defining a waiting instruction;
the operation ending instruction defines a subunit for defining an operation ending instruction.
In one embodiment, the operation instruction defining the subunit includes:
the expected value acquisition subunit is used for acquiring the expected values of all interface signals in each clock cycle of each state in the interface circuit;
and the numerical value forming subunit is used for sequentially forming a string of numerical values for each state of the interface circuit according to all expected values in the same clock cycle of the same state so as to obtain all operation instructions of each state in the interface circuit.
In an embodiment, the memory unit 302 includes:
the sequencing subunit is used for sequencing the instructions of all the states in the interface circuit according to a clock cycle;
and the storage subunit is used for sequentially storing the sequenced instructions in the corresponding memory addresses.
In an embodiment, the obtaining unit 303 includes:
the state acquisition subunit is used for acquiring the current state of the interface circuit when in use;
and the instruction calling subunit is used for sequentially acquiring the instructions in the corresponding memory addresses from the current state of the interface circuit.
In one embodiment, the execution unit 304 includes:
the signal setting subunit is used for sequentially setting each interface signal of the interface circuit according to the instruction obtained from the memory address;
the judging subunit is used for judging whether the current instruction is an operation ending instruction or not;
and the state switching subunit is used for switching the state of the interface circuit if the state switching subunit is in the positive state.
In one embodiment, the apparatus further comprises:
and the setting unit is used for setting an interface signal connected with the preceding stage circuit.
It should be noted that, as can be clearly understood by those skilled in the art, the specific implementation processes of the signal timing configuration apparatus 300 and each unit may refer to the corresponding descriptions in the foregoing method embodiments, and for convenience and brevity of description, no further description is provided herein.
The signal timing configuration apparatus 300 can be implemented in the form of a computer program that can be run on a computer device as shown in fig. 13.
Referring to fig. 13, fig. 13 is a schematic block diagram of a computer device according to an embodiment of the present application. The computer device 500 is a server, and the server may be an independent server or a server cluster composed of a plurality of servers.
Referring to fig. 13, the computer device 500 includes a processor 502, memory, and a network interface 505 connected by a system bus 501, where the memory may include a non-volatile storage medium 503 and an internal memory 504.
The non-volatile storage medium 503 may store an operating system 5031 and a computer program 5032. The computer programs 5032 include program instructions that, when executed, cause the processor 502 to perform a signal timing configuration method.
The processor 502 is used to provide computing and control capabilities to support the operation of the overall computer device 500.
The internal memory 504 provides an environment for the operation of the computer program 5032 in the non-volatile storage medium 503, and when the computer program 5032 is executed by the processor 502, the processor 502 can execute a signal timing configuration method.
The network interface 505 is used for network communication with other devices. Those skilled in the art will appreciate that the architecture shown in fig. 13 is merely a block diagram of some of the structures associated with the disclosed aspects and is not intended to limit the computing device 500 to which the disclosed aspects may be applied, as a particular computing device 500 may include more or less components than those shown, or may combine certain components, or have a different arrangement of components.
Wherein the processor 502 is configured to run the computer program 5032 stored in the memory to implement the following steps:
defining a set of instructions;
storing the instructions in the memory addresses in sequence;
when the interface circuit is used, instructions are sequentially acquired from the specified memory addresses according to the state of the interface circuit;
and driving the interface circuit to execute corresponding operation according to the instruction.
In an embodiment, when the processor 502 implements the step of defining a set of instructions, the following steps are specifically implemented:
defining all operation instructions of each state in the interface circuit;
defining a waiting instruction;
an operation end instruction is defined.
In an embodiment, when the processor 502 implements all the operation instruction steps for defining each state in the interface circuit, the following steps are implemented:
acquiring expected values of all interface signals of each clock period of each state in an interface circuit;
and sequentially forming a string of numerical values of each state of the interface circuit according to all expected values of the same state in the same clock cycle to obtain all operation instructions of each state in the interface circuit.
In an embodiment, when the processor 502 implements the step of sequentially storing the instructions in the memory addresses, the following steps are specifically implemented:
sequencing the instructions of all states in the interface circuit according to a clock cycle;
and sequentially storing the sequenced instructions in the corresponding memory addresses.
In an embodiment, when the processor 502 implements the above-described use, when sequentially obtaining instruction steps from a specified memory address according to the state of the interface circuit, the following steps are specifically implemented:
when in use, the current state of the interface circuit is obtained;
and sequentially acquiring the instructions in the corresponding memory addresses from the current state of the interface circuit.
In an embodiment, when implementing the step of driving the interface circuit to execute the corresponding operation according to the instruction, the processor 502 specifically implements the following steps:
setting each interface signal of the interface circuit in turn according to the instruction obtained from the memory address;
judging whether the current instruction is an operation ending instruction or not;
if so, switching the state of the interface circuit, and sequentially acquiring instructions from the specified new memory address according to the new state of the interface circuit;
if not, returning to the step of setting each interface signal of the interface circuit in sequence according to the instruction obtained from the memory address.
In one embodiment, before implementing the step of defining a set of instructions, the processor 502 further implements the steps of:
an interface signal connected to the preceding stage circuit is set.
It should be understood that, in the embodiment of the present Application, the Processor 502 may be a Central Processing Unit (CPU), and the Processor 502 may also be other general-purpose processors, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field-Programmable Gate arrays (FPGAs) or other Programmable logic devices, discrete Gate or transistor logic devices, discrete hardware components, and the like. Wherein a general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
It will be understood by those skilled in the art that all or part of the flow of the method implementing the above embodiments may be implemented by a computer program instructing associated hardware. The computer program includes program instructions, and the computer program may be stored in a storage medium, which is a computer-readable storage medium. The program instructions are executed by at least one processor in the computer system to implement the flow steps of the embodiments of the method described above.
Accordingly, the present invention also provides a storage medium. The storage medium may be a computer-readable storage medium. The storage medium stores a computer program, wherein the computer program, when executed by a processor, causes the processor to perform the steps of:
defining a set of instructions;
storing the instructions in memory addresses in sequence;
when the interface circuit is used, instructions are sequentially acquired from the specified memory addresses according to the state of the interface circuit;
and driving the interface circuit to execute corresponding operation according to the instruction.
In an embodiment, when the step of defining the set of instructions is implemented by the processor executing the computer program, the following steps are specifically implemented:
defining all operation instructions of each state in the interface circuit;
defining a waiting instruction;
an operation end instruction is defined.
In an embodiment, when the processor executes the computer program to implement all the operation instruction steps for defining each state in the interface circuit, the following steps are specifically implemented:
acquiring the expected values of all interface signals in each clock period of each state in an interface circuit;
and sequentially forming a string of numerical values of each state of the interface circuit according to all expected values of the same state in the same clock cycle to obtain all operation instructions of each state in the interface circuit.
In an embodiment, when the processor executes the computer program to implement the step of sequentially storing the instructions in the memory addresses, the following steps are specifically implemented:
sequencing the instructions of all states in the interface circuit according to a clock cycle;
and sequentially storing the sequenced instructions in the corresponding memory addresses.
In an embodiment, when the processor executes the computer program to implement the use, and when the processor sequentially obtains the instruction steps from the specified memory address according to the state of the interface circuit, the following steps are specifically implemented:
when in use, the current state of the interface circuit is obtained;
and sequentially acquiring the instructions in the corresponding memory addresses from the current state of the interface circuit.
In an embodiment, when the processor executes the computer program to implement the step of driving the interface circuit to execute the corresponding operation according to the instruction, the following steps are specifically implemented:
setting each interface signal of the interface circuit in turn according to the instruction obtained from the memory address;
judging whether the current instruction is an operation ending instruction or not;
if so, switching the state of the interface circuit, and when returning to the use, sequentially acquiring instructions from the specified memory address according to the state of the interface circuit;
if not, returning to the step of setting each interface signal of the interface circuit in sequence according to the instruction obtained from the memory address.
In one embodiment, the processor, before executing the computer program to implement the step of defining a set of instructions, further implements the steps of:
an interface signal connected to the preceding stage circuit is set.
The storage medium may be a usb disk, a removable hard disk, a Read-Only Memory (ROM), a magnetic disk or an optical disk, and various computer readable storage media that can store program codes.
Those of ordinary skill in the art will appreciate that the various illustrative components and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the components and steps of the various examples have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the technical solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
In the several embodiments provided in the present invention, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative. For example, the division of each unit is only one logic function division, and there may be another division manner in actual implementation. For example, multiple elements or components may be combined or may be integrated into another system, or some features may be omitted, or not implemented.
The steps in the method of the embodiment of the invention can be sequentially adjusted, combined and deleted according to actual needs. The units in the device of the embodiment of the invention can be combined, divided and deleted according to actual needs. In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.
The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a storage medium. Based on such understanding, the technical solution of the present invention essentially or partly contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a terminal, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention.
While the invention has been described with reference to specific embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (9)
1. The signal timing configuration method is characterized by comprising the following steps:
defining a set of instructions;
storing the instructions in memory addresses in sequence;
when the interface circuit is used, instructions are sequentially acquired from the specified memory addresses according to the state of the interface circuit;
driving the interface circuit to execute corresponding operation according to the instruction;
the driving of the interface circuit according to the instruction to execute the corresponding operation comprises:
setting each interface signal of the interface circuit in turn according to the instruction obtained from the memory address;
judging whether the current instruction is an operation ending instruction or not;
if so, switching the state of the interface circuit, and when returning to the use, sequentially acquiring instructions from the specified memory address according to the state of the interface circuit;
if not, returning to set each interface signal of the interface circuit in sequence according to the instruction obtained from the memory address;
assuming that the set of interface signals has N, the memory bit width is (N +1), and each bit of the lower N bits in the (N +1) bit width just stores the expected value of one interface signal; the memory depth corresponds to a time axis, after the interface circuit is triggered and started, the 1 st clock cycle takes out (N +1) bit values in the memory address0 and outputs the lower N bit values to the interface, the 2 nd clock cycle takes out (N +1) bit values in the memory address1 and outputs the lower N bit values to the interface, and the rest is done so as to output a set signal sequence;
if the state of the interface signal is not changed and lasts for a certain time, a waiting instruction is defined for the situation, when the highest bit in (N +1) bit width data in the memory is 1, the lower N bits are the number of waiting clock cycles and cannot be equal to 0, after the interface circuit takes out the instruction from the memory, the highest bit is 1, the numerical value of the lower N bits cannot be output to the interface, but the interface signal keeps the former value, waits for the appointed clock cycle, and then the new instruction is taken out at the next memory address; if the highest bit in the (N +1) bit width data in the memory is 1 and the rest are all 0, defining the highest bit as an operation ending instruction, ending the group of operations, and if the hardware circuit fetches the ending instruction, not continuously taking down the numerical value of a memory address; if the interface protocol is complex and has a plurality of groups of different time sequences, a plurality of state machine states are designed, after each state machine is started, the interface circuit takes values from the corresponding memory entry address, sends a signal time sequence, stops taking values when an ending instruction is obtained, and triggers the main state machine to jump to the next state.
2. The method of claim 1, wherein the defining a set of instructions comprises:
defining all operation instructions of each state in the interface circuit;
defining a waiting instruction;
an operation end instruction is defined.
3. The signal timing configuration method of claim 2, wherein the defining all operational instructions for each state in the interface circuit comprises:
acquiring the expected value of all interface signals in each clock period of each state in the interface circuit from the interface circuit protocol document;
and sequentially forming a string of numerical values of each state of the interface circuit according to all expected values of the same state in the same clock cycle so as to obtain all operation instructions of each state in the interface circuit.
4. The method of claim 3, wherein the sequentially storing the instructions in the memory addresses comprises:
sequencing the instructions of all states in the interface circuit according to a clock cycle;
and sequentially storing the sequenced instructions in the corresponding memory addresses.
5. The method according to claim 4, wherein the sequentially obtaining instructions from the designated memory address according to the state of the interface circuit during the use comprises:
when in use, the current state of the interface circuit is obtained;
and sequentially acquiring the instructions in the corresponding memory addresses from the current state of the interface circuit.
6. The method of any of claims 1 to 5, wherein the defining a set of instructions is preceded by:
an interface signal connected to the preceding stage circuit is set.
7. A signal timing configuration apparatus, comprising:
an instruction definition unit for defining a set of instructions;
the storage unit is used for sequentially storing the instructions in the memory addresses;
the acquisition unit is used for sequentially acquiring instructions from the specified memory addresses according to the state of the interface circuit when in use;
the execution unit is used for driving the interface circuit to execute corresponding operation according to the instruction;
the execution unit includes:
the signal setting subunit is used for sequentially setting each interface signal of the interface circuit according to the instruction obtained from the memory address;
the judging subunit is used for judging whether the current instruction is an operation ending instruction or not;
the state switching subunit is used for switching the state of the interface circuit if the state of the interface circuit is the same as the state of the interface circuit;
assuming that the set of interface signals has N, the memory bit width is (N +1), and each bit of the lower N bits in the (N +1) bit width just stores the expected value of one interface signal; the memory depth corresponds to a time axis, after the interface circuit is triggered and started, the 1 st clock cycle takes out (N +1) bit values in the memory address0 and outputs the lower N bit values to the interface, the 2 nd clock cycle takes out (N +1) bit values in the memory address1 and outputs the lower N bit values to the interface, and the rest is done so as to output a set signal sequence;
if the state of the interface signal is not changed and lasts for a certain time, a waiting instruction is defined for the situation, when the highest bit in (N +1) bit width data in the memory is 1, the lower N bits are the number of waiting clock cycles and cannot be equal to 0, after the interface circuit takes out the instruction from the memory, the highest bit is 1, the numerical value of the lower N bits cannot be output to the interface, but the interface signal keeps the former value, waits for the appointed clock cycle, and then the new instruction is taken out at the next memory address; if the highest bit in the (N +1) bit width data in the memory is 1 and the rest is all 0, defining the highest bit as an operation ending instruction, ending the group of operations, and if a hardware circuit acquires the ending instruction, not continuing to take the numerical value of a memory address; if the interface protocol is complex and has a plurality of groups of different time sequences, a plurality of state machine states are designed, after each state machine is started, the interface circuit takes values from the corresponding memory entry address, sends a signal time sequence, stops taking values when an ending instruction is obtained, and triggers the main state machine to jump to the next state.
8. A computer device, characterized in that the computer device comprises a memory, on which a computer program is stored, and a processor, which when executing the computer program implements the method according to any of claims 1 to 6.
9. A storage medium, characterized in that the storage medium stores a computer program which, when executed by a processor, implements the method according to any one of claims 1 to 6.
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