CN109347474A - Signal sequence configuration method, device, computer equipment and storage medium - Google Patents
Signal sequence configuration method, device, computer equipment and storage medium Download PDFInfo
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- CN109347474A CN109347474A CN201811137392.0A CN201811137392A CN109347474A CN 109347474 A CN109347474 A CN 109347474A CN 201811137392 A CN201811137392 A CN 201811137392A CN 109347474 A CN109347474 A CN 109347474A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/017509—Interface arrangements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
- H03K23/40—Gating or clocking signals applied to all stages, i.e. synchronous counters
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Abstract
The present invention relates to signal sequence configuration method, device, computer equipment and storage medium, this method includes defining one group of instruction；Instruction is successively stored in memory address；In use, according to interface circuit state out of specified memory address successively acquisition instruction；Corresponding operation is executed according to order-driven interface circuit.The present invention passes through definition instruction, the level state of interface signal is formed into a string of numerical value, it is stored in memory address in the form of instruction according to different states, in use, successively taking out instruction out of corresponding memory address according to different states, driving interface signal carries out low and high level output according to the numerical value of instruction, the numerical value for the instruction being stored in memory address is modified, to change the interface signal timing of interface circuit, realizes the flexible and configurability of interface signal timing.
Description
Technical field
The present invention relates to interface circuits, more specifically refer to signal sequence configuration method, device, computer equipment and deposit
Storage media.
Background technique
The work of interface is executed according to the signal of certain timing, with NAND Flash controller circuitry in chip with
For NAND PHY circuit interface sequence, the signal sequence requirement of NAND phy interface order transmission phase, as shown in Figure 1, being
Reach this requirement, it will usually which five counter counter0~counter4 are set in circuit, and pre-set
The full threshold value of individual count device meter, by several interface signals of the interface be successively set as cebar, cle, ale, webar,
Rebar, sdr_cycle, rddate_en, wrdata, wrdata_valid and wrdqs_en, at the t0 moment by cebar interface
Signal drags down, and cle interface signal is drawn high, and exports wrdata interface signal, and wrdata_valid interface signal is drawn high, wrdqs_en
Interface signal drags down, and starts counter counter0, when counter counter0 count down to pre-set threshold value, at this time just
It is the t1 moment well, interface signal webar is dragged down, while starting counter counter1, when counter counter1 is count down to
Pre-set threshold value at this time precisely t2 moment, webar interface signal is drawn high, while starting counter counter2,
And so on, realize the set signal sequence of Fig. 1.
But the arrangement of current interface signal timing has certain limitation, lacks flexibility, such as in t0
It carves, hardware fixation drags down cebar interface signal, and cle interface signal is drawn high, and wrdata_valid interface signal is drawn high,
Wrdqs_en interface signal drags down, if but NAND PHY agreement upgrade, these interface signals need different moments change, then
Hardware circuit cannot achieve, in another example, counter counter0 realizes the t0 moment to the counting at t1 moment, if but NAND
The upgrading of PHY agreement, the interval of delta t 1 at t0 moment to t1 moment become very big, and the timer counter0 bit wide of hardware circuit is not
It is enough, then it cannot achieve such timing requirements.
Therefore, it is necessary to design a kind of new method, the flexible and configurability of interface signal timing is realized.
Summary of the invention
It is an object of the invention to overcome the deficiencies of existing technologies, signal sequence configuration method, device, computer are provided and set
Standby and storage medium.
To achieve the above object, the invention adopts the following technical scheme: signal sequence configuration method, comprising:
Define one group of instruction；
Instruction is successively stored in memory address；
In use, according to interface circuit state out of specified memory address successively acquisition instruction；
Corresponding operation is executed according to order-driven interface circuit.
Its further technical solution are as follows: one group of instruction of the definition, comprising:
All operational orders of each state in defining interface circuit；
Definition waits instruction；
Defining operation END instruction.
Its further technical solution are as follows: all operational orders of each state in the defining interface circuit, comprising:
From each clock cycle total interface signal for obtaining each state in interface circuit in interface circuit Protocol document
Desired value；
The each state of interface circuit is successively formed a string according to all desired values in the same state same clock cycle
Numerical value, to obtain all operational orders of each state in interface circuit.
Its further technical solution are as follows: described to be successively stored in instruction in memory address, comprising:
Instruction stateful in interface circuit is sorted according to the clock cycle；
Instruction after sequence is successively stored in corresponding memory address.
Its further technical solution are as follows: it is described in use, according to interface circuit state out of specified memory address successively
Acquisition instruction, comprising:
In use, obtaining the current state of interface circuit；
The state current from interface circuit successively obtains the instruction in corresponding memory address.
Its further technical solution are as follows: described that corresponding operation is executed according to order-driven interface circuit, comprising:
According to acquired instruction out of memory address, each interface signal of interface circuit is successively set；
Judge whether current instruction is operation END instruction；
If so, switching interface circuit state, and return described in use, according to interface circuit state from specified memory
Successively acquisition instruction in address；
If it is not, then returning to each interface letter for successively setting interface circuit according to acquired instruction out of memory address
Number.
Its further technical solution are as follows: before one group of instruction of the definition, further includes:
The interface signal connecting with front stage circuits is set.
The present invention also provides signal sequence configuration devices, comprising:
Instruction definition unit, for defining one group of instruction；
Storage unit is successively stored in memory address for that will instruct；
Acquiring unit, in use, according to interface circuit state out of specified memory address successively acquisition instruction；
Execution unit, for executing corresponding operation according to order-driven interface circuit.
The present invention also provides a kind of computer equipment, the computer equipment includes memory and processor, described to deposit
Computer program is stored on reservoir, the processor realizes above-mentioned method when executing the computer program.
The present invention also provides a kind of storage medium, the storage medium is stored with computer program, the computer journey
Sequence can realize above-mentioned method when being executed by processor.
Compared with the prior art, the invention has the advantages that: the present invention is by definition instruction, by the level of interface signal
State forms a string of numerical value, is stored in memory address in the form of instruction according to different states, in use, according to different
State, successively takes out instruction out of corresponding memory address, and driving interface signal is defeated according to the numerical value progress low and high level of instruction
Out, when taking-up is operation END instruction, stop the instruction fetch out of memory address, and the state of switching interface circuit, with into
The reading of the instruction of row NextState, the numerical value for the instruction that can be stored in memory address by modification, to change interface circuit
Interface signal timing, realize interface signal timing flexible and configurability.
The invention will be further described in the following with reference to the drawings and specific embodiments.
Detailed description of the invention
Technical solution in order to illustrate the embodiments of the present invention more clearly, below will be to needed in embodiment description
Attached drawing is briefly described, it should be apparent that, drawings in the following description are some embodiments of the invention, general for this field
For logical technical staff, without creative efforts, it is also possible to obtain other drawings based on these drawings.
Fig. 1 is the signal sequence schematic diagram of the NAND phy interface order transmission phase of the prior art；
Fig. 2 is the flow diagram of signal sequence configuration method provided in an embodiment of the present invention；
Fig. 3 is the interface signal schematic diagram of signal sequence configuration method provided in an embodiment of the present invention；
Fig. 4 is that the signal sequence comparison of the data write state of signal sequence configuration method provided in an embodiment of the present invention is shown
It is intended to；
Fig. 5 is the signal sequence signal of the data write state of signal sequence configuration method provided in an embodiment of the present invention
Figure；
Fig. 6 is definition and the storage schematic diagram of instruction provided in an embodiment of the present invention；
Fig. 7 is signal sequence provided in an embodiment of the present invention and instruction correspondence diagram；
Fig. 8 is that the Interface status of signal sequence configuration method provided in an embodiment of the present invention jumps schematic diagram；
Fig. 9 is the signal sequence signal of the order transmission state of signal sequence configuration method provided in an embodiment of the present invention
Figure；
Figure 10 is that the address of signal sequence configuration method provided in an embodiment of the present invention sends the signal sequence signal of state
Figure；
Figure 11 be another embodiment of the present invention provides signal sequence configuration method flow diagram；
Figure 12 is the schematic block diagram of signal sequence configuration device provided in an embodiment of the present invention；
Figure 13 is the schematic block diagram of computer equipment provided in an embodiment of the present invention.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are some of the embodiments of the present invention, instead of all the embodiments.Based on this hair
Embodiment in bright, every other implementation obtained by those of ordinary skill in the art without making creative efforts
Example, shall fall within the protection scope of the present invention.
It should be appreciated that ought use in this specification and in the appended claims, term " includes " and "comprising" instruction
Described feature, entirety, step, operation, the presence of element and/or component, but one or more of the other feature, whole is not precluded
Body, step, operation, the presence or addition of element, component and/or its set.
It is also understood that mesh of the term used in this description of the invention merely for the sake of description specific embodiment
And be not intended to limit the present invention.As description of the invention and it is used in the attached claims, unless on
Other situations are hereafter clearly indicated, otherwise " one " of singular, "one" and "the" are intended to include plural form.
It will be further appreciated that the term "and/or" used in description of the invention and the appended claims is
Refer to any combination and all possible combinations of one or more of associated item listed, and including these combinations.
The schematic flow chart of signal sequence configuration method provided in an embodiment of the present invention.The signal sequence configuration method is answered
For in server.The server can be a server in Distributed Services platform, and user can be to the server memory
The instruction of interior storage is modified and is reset, so that the interface signal of interface circuit is changed according to instruction.
It should be noted that only illustrating a server in Fig. 2, in the actual operation process, it can be more clothes
Business device is operated simultaneously
Fig. 2 is the flow diagram of signal sequence configuration method provided in an embodiment of the present invention.As shown in Fig. 2, this method
Include the following steps S110 to S140.
S110, one group of instruction is defined.
In the present embodiment, above-mentioned instruction refers to a string of numerical value being stored in memory, and the bit wide of memory is 11 ratios
Spy, storage bit wide are the instruction of 11 bits, and each address stores an instruction.
Specifically, it is assumed that this group interface signal has N number of, then memory bit wide is (N+1), in the bit wide of (N+1) a bit
Each bit of low N number of bit stores the desired value of an interface signal just.
Corresponding memory depth is time shaft, and for interface circuit after the starting that is triggered, the 1st clock cycle takes out memory
The numerical value of low N number of bit is output to interface, the 2nd clock cycle by the numerical value of (N+1) a bit in the address address0
The numerical value for taking out (N+1) a bit in the address memory address1, is output to connecing for interface circuit for low N number of bit value
In message number, and so on, thus output set signal sequence.
Specifically, which can be instructed by research and development engineer according to interface protocol document Manual definition, can also be automatic
Definition instruction.
In one embodiment, above-mentioned step S110 may include step S111~S113.
All operational orders of each state in S111, defining interface circuit.
Operational order refers to the instruction for carrying out level switching according to its numerical value for interface signal in driving interface circuit；It should
Its low 10 numerical value Bit9~Bit0 is output on corresponding interface signal by operational order, and Bit9~Bit0 is characterized and connect
The desired value of message cebar~wrdqs_en, when operational order output, the interface signal numerical value pair specified according to operation
The level of itself should be switched.Specifically, it is 0 that the format of operational order, which is highest order, remaining as the reality according to all signaling interfaces
Depending on the height of border level, high level is then 1, and low level is then 0.
In one embodiment, above-mentioned step S111 may include step S1111~S1112.
S1111, the desired value for obtaining each clock cycle total interface signal of each state in interface circuit.
As shown in fig. 7, the corresponding numerical value of each operational order is different, therefore, it is necessary to first obtain in interface circuit
The desired value of each clock cycle total interface signal of each state, the numerical value being made of the desired value, as operational order.
S1112, by each state of interface circuit according to the successively group of all desired values in the same state same clock cycle
At a string of numerical value, to obtain all operational orders of each state in interface circuit.
Specifically according to all desired values in the same state same clock cycle according to the sequence group of each interface signal
At a string of numerical value, number is obtained all in accordance with above-mentioned mode for the clock cycle of the desired value switching of state each in interface circuit
Value, to form all operational orders of each state in interface circuit.
For example, numerical value composed by t0 moment all desired values is 0_0001110001；T1 moment all desired values
Composed numerical value is 0_0001100001.
S112, definition wait instruction.
In the present embodiment, each interface signal to be specified for referring to current interface circuit is waited to keep a upper level constant,
Until there is new instruction to enter；Waiting instruction is the clock periodicity for waiting low 10 numerical value Bit9~Bit0 specified, phase
Interface signal value is constant, and it is 1 that the format for waiting instruction, which is highest order, remaining to be not all 0.
S113, defining operation END instruction.
In the present embodiment, which refers to operation end and interface circuit switches to the finger of NextState
It enables, specifically, it is 1 that the format for operating END instruction, which is highest order, remaining as full 0.If interface circuit is got out of memory address
END instruction is operated, then stops continuing to read the instruction in memory address, triggering interface circuit terminates this state, and entrance is next
State, interface signal remain unchanged.
Interface circuit will successively instruction fetch executes since specified entry address (such as addr (m+0)), each clock week
As soon as the phase takes an instruction execution (wait instruction except), continuous operational order and wait instruction can constitute all cebar~
The timing requirements of wrdqs_en interface signal.Waiting the waiting time of instruction can formulate according to the actual situation, and according to reality
The time instruction fetch again that how many a clock cycle are waited after waiting instructs is got in situation setting.
The variation of interface signal is controlled by operational order, and the holding of interface signal is by waiting instruction to realize, and above-mentioned finger
Enable definition as shown in fig. 6, from 9 bits to 0 bit successively represent cebar, cle, ale, webar, rebar, sdr_cycle,
Rddate_en, wrdata, wrdata_valid and wrdqs_en.
S120, instruction is successively stored in memory address.
In the present embodiment, it will instruct successively according in sequential storage to memory address described in Fig. 6, opened in interface circuit
When beginning work, corresponding instruction is taken out out of specified memory address, the setting of interface signal can be realized, if desired according to reality
When border situation modifies the level of interface signal, it is only necessary to the instruction that modification is stored in memory address；So that interface signal
The flexible and configurability of timing is high, in order to interface circuit can out of memory address acquisition instruction.
In one embodiment, above-mentioned step S120 may include 121~S122 of step S.
S121, instruction stateful in interface circuit is sorted according to the clock cycle；
S122, the instruction after sequence is successively stored in corresponding memory address.
In the present embodiment, instruction all constructs in advance, when chip is cold-started and executes initialization process, instructs in firmware
It is lower that specified memory address is arrived into instruction storage, as shown in figure 5, first instruction is operational order (0_0001110001) deposit
Address addr (m+0) of memory, subsequent instruction successively store backward.After initialization, institute has been got well with regard to storage inside memory
Instruction in need, as shown in Figure 6.
S130, in use, according to interface circuit state out of specified memory address successively acquisition instruction.
In actual use, its corresponding finger is obtained out of specified memory address according to each state of interface circuit
It enables, specifically, if interface protocol is more complicated, there is multiple groups difference timing, then design multiple state machine states, each state machine opens
After dynamic, interface circuit issues signal sequence from the instruction fetch of corresponding memory entry address, gets operation END instruction and then stops taking
Instruction, and triggering state machine jumps to next state, so that interface circuit takes from the corresponding memory entry address of new state again
Instruction, is issued new signal sequence, increasingly complex multiple timings interface is realized with this.
In one embodiment, above-mentioned step S130 may include having step S131~S132.
S131, in use, obtaining the current state of interface circuit；
As shown in Figure 10, the course of work in NAND phy interface agreement includes eight stages, this eight stages can be with
Three kinds of time sequence status are summarized as, are that order sends state, address sends state, data write state；Corresponding to each state
Signal timing diagram is different, it is therefore desirable to the different address instruction fetch out of memory against different states.
S132, instruction in corresponding memory address is successively obtained from the current state of interface circuit.
As shown in Fig. 5, Fig. 9, Figure 10, data write state, order transmission state, address transmission state three are respectively shown
The signal sequence of a state.For example, in conjunction with Fig. 7 for Fig. 5, when interface circuit starts, shape is written in execution data
When state, instruction is successively taken out from address addr (m+0) of memory, first clock cycle takes out first operational order (0_
0001110001), according to instruction by cebar~wrdqs_en interface signal be set as instruction require value, i.e., 0001110001；
Next clock cycle, which takes out, waits instruction (1_0000000010), requires to wait 2 clock cycle according to instruction；Next one
Clock cycle takes out operational order (0_0001100001), is set as referring to by cebar~wrdqs_en interface signal according to instruction
The value that order requires, i.e., 0001100001；And so on, export specified signal sequence；Until encountering operation END instruction (1_
0000000000) then stop instruction fetch, and the state of interface circuit is switched to NextState by triggering state machine, it is next to carry out
The reading of the instruction of state.
When interface circuit starts workflow, circuit state machine jumps to CMD_PHASE state from IDLE state, at this
Circuit is executed from the addr0 value of memory under state, issues the interface sequence of set order transmission state, encountering operation terminates
It instructs and then stops, and trigger CMD_PHASE state to terminate；Then circuit state machine jumps to ADDR_PHASE state, in the shape
Circuit is executed from addr (n+0) value of memory under state, issues the interface sequence that set address sends state, encounters operation knot
Shu Zhiling then stops, and triggers ADDR_PHASE state and terminate；Interface circuit state machine jumps to next ADDR_PHASE shape
State, and so on.To sum up, by a state machine, in conjunction with the corresponding instruction sequence of each state, so that it may construct complexity
Signal sequence.Therefore it may only be necessary to adjust the value of operational order, so that it may specify the level of each interface signal；Adjustment, which waits, to be referred to
The value of order, so that it may the interval time between signal is controlled, a plurality of waiting instruction not enough can be continuously arranged in a waiting instruction,
Until requirement until meeting time interval.In conclusion when arbitrary signal required for being constructed by three classes instruction
Sequence.
S140, corresponding operation is executed according to order-driven interface circuit.
In the present embodiment, the numerical value of instruction represents the level state of interface signal all in interface circuit.
In one embodiment, above-mentioned step S140 may include step S141~S143.
S141, according to acquired instruction out of memory address, successively set each interface signal of interface circuit；
S142, judge whether current instruction is operation END instruction；
S143, if so, switching interface circuit state, and return step S130；
If it is not, then return step S141.
After being triggered the desired value of a series of each signal in memory will be stored in advance successively automatically in interface circuit
It is output to circuit interface.Since the numerical value in memory is configurable, hereby be achieved that interface signal timing flexibly can configure.
It is assumed that this group interface signal has N number of, then memory bit wide is (N+1), low N number of bit in (N+1) a bit bit wide
Each bit store the desired value of an interface signal just；Corresponding memory depth is time shaft, and interface circuit is in quilt
After triggering starting, the 1st clock cycle takes out (N+1) a bit value in memory address0, and low N number of bit value is defeated
Interface is arrived out, and the 2nd clock cycle takes out (N+1) a bit value in memory address1, and low N number of bit value is exported
To interface, and so on, thus output set signal sequence.
If the state of interface signal can remain unchanged, certain time, in response to this, defines a waiting and refer to
It enables, when the highest order in memory in (N+1) bit bit wide data is 1, then low N number of bit is the number of clock cycles waited
(cannot be equal to 0), for interface circuit after taking out such instruction in memory, discovery highest bit is 1, then will not be by low N number of ratio
Special numerical value is output to interface, but interface signal is allowed to keep pervious value, waits the clock cycle to be specified, then just arrives next
A memory address takes new instruction.If highest order is 1 in (N+1) bit bit wide data in memory, remaining as full 0, then it is defined as
END instruction is operated, the operation of this group is terminated, hardware circuit gets END instruction, then will not continue to take next memory address
Numerical value；If interface protocol is more complicated, there is multiple groups difference timing, then designs multiple state machine states, after each state machine starting,
Interface circuit issues signal sequence, gets END instruction and then stop value, and trigger master from corresponding memory entry address value
State machine jumps to next state, so that hardware circuit issues new again from the corresponding memory entry address value of new state
Signal sequence realizes increasingly complex multiple timings interface with this.The timing of interface signal can with flexible configuration, once interface
Agreement upgrading, it is not necessary to modify circuits, as long as the numerical value being stored in memory using software modification, save hardware development at
This, shortens time to market (TTM), with a hardware, can support new agreement after upgrading software.It is provided most for interface signal
The timing variations of big flexibility, each signal can be controlled individually, real by modification numerical value in the case where not changing circuit
Now flexible adjustable effect.
Above-mentioned signal sequence configuration method is instructed by definition, and the level state of interface signal is formed a string of numerical value,
It is stored in memory address in the form of instruction according to different states, in use, according to different states, from corresponding memory
Instruction is successively taken out in address, driving interface signal carries out low and high level output according to the numerical value of instruction, when taking-up is operation
When END instruction, stop the instruction fetch out of memory address, and the state of switching interface circuit, to carry out the instruction of NextState
It reads, can be realized by modifying the numerical value for the instruction being stored in memory address with changing the interface signal timing of interface circuit
The flexible and configurability of interface signal timing.
Figure 11 be another embodiment of the present invention provides a kind of signal sequence configuration method flow diagram.Such as Figure 11 institute
Show, the signal sequence configuration method of the present embodiment includes step S210-S250.Wherein step S220-S250 and above-described embodiment
In step S110-S140 it is similar, details are not described herein.The following detailed description of in the present embodiment increase step S210.
The interface signal that S210, setting and front stage circuits connect.
Specifically, the interface signal connecting with front stage circuits is arranged when designing circuit by research and development engineer.As shown in figure 3,
Wrdata signal is bus type and its value is not fixed value, but passes through wrdata_pre interface by previous stage circuit module
Signal provides, every time different.Therefore, it is necessary to introduce an interface signal wrdata_pop_internal, to solve
Wrdata bus signals problem.In view of the particularity of wrdata, wrdata_pop_internal interface signal is introduced.The signal
It is not output to interface, but connects previous stage circuit module, when it is 1, interface circuit provides front stage circuits module
Wrdata_pre is latched into wrdata output, while front stage circuits module will export next wrdata_pre.Following Fig. 4 institute
Show, the signal is always in advance in one timeticks of wrdata_valid signal.
Figure 12 is a kind of schematic block diagram of signal sequence configuration device 300 provided in an embodiment of the present invention.Such as Figure 12 institute
Show, corresponds to the above signal sequence configuration method, the present invention also provides a kind of signal sequence configuration devices 300.The signal sequence
Configuration device 300 includes the unit for executing above-mentioned signal sequence configuration method, the device can be configured in server or
In person's chip.
Specifically, Figure 12 is please referred to, which includes:
Instruction definition unit 301, for defining one group of instruction；
Storage unit 302 is successively stored in memory address for that will instruct；
Acquiring unit 303, for referring in use, successively being obtained out of specified memory address according to interface circuit state
It enables；
Execution unit 304, for executing corresponding operation according to order-driven interface circuit.
In one embodiment, described instruction definition unit 301 includes:
Operational order defines subelement, all operational orders for each state in defining interface circuit；
Instruction definition subelement is waited, waits instruction for defining；
Operation END instruction defines subelement, is used for defining operation END instruction.
In one embodiment, the operational order defines subelement and includes:
Desired value obtains subelement, for obtaining each clock cycle total interface signal of each state in interface circuit
Desired value；
Numerical value forms subelement, for by each state of interface circuit according to all in the same state same clock cycle
Desired value successively forms a string of numerical value, to obtain all operational orders of each state in interface circuit.
In one embodiment, above-mentioned storage unit 302 includes:
Sorting subunit, for instruction stateful in interface circuit to be sorted according to the clock cycle；
Storing sub-units, for the instruction after sequence to be successively stored in corresponding memory address.
In one embodiment, the acquiring unit 303 includes:
State obtains subelement, in use, obtaining the current state of interface circuit；
Subelement is transferred in instruction, for successively obtaining the finger in corresponding memory address from the current state of interface circuit
It enables.
In one embodiment, the execution unit 304 includes:
Signal sets subelement, for successively setting the every of interface circuit according to acquired instruction out of memory address
A interface signal；
Judgment sub-unit, for judging whether current instruction is operation END instruction；
State switching subelement, for if so, switching interface circuit state.
In one embodiment, the present apparatus further include:
Setting unit, for the interface signal connecting with front stage circuits to be arranged.
It should be noted that it is apparent to those skilled in the art that, above-mentioned signal sequence configuration device
300 and each unit specific implementation process, can with reference to the corresponding description in preceding method embodiment, for convenience of description and
Succinctly, details are not described herein.
Above-mentioned signal sequence configuration device 300 can be implemented as a kind of form of computer program, which can
To be run in computer equipment as shown in fig. 13 that.
Figure 13 is please referred to, Figure 13 is a kind of schematic block diagram of computer equipment provided by the embodiments of the present application.The calculating
Machine equipment 500 is server, and server can be independent server, is also possible to the server set of multiple server compositions
Group.
Refering to fig. 13, which includes processor 502, memory and the net connected by system bus 501
Network interface 505, wherein memory may include non-volatile memory medium 503 and built-in storage 504.
The non-volatile memory medium 503 can storage program area 5031 and computer program 5032.The computer program
5032 include program instruction, which is performed, and processor 502 may make to execute a kind of signal sequence configuration method.
The processor 502 is for providing calculating and control ability, to support the operation of entire computer equipment 500.
The built-in storage 504 provides environment for the operation of the computer program 5032 in non-volatile memory medium 503, should
When computer program 5032 is executed by processor 502, processor 502 may make to execute a kind of signal sequence configuration method.
The network interface 505 is used to carry out network communication with other equipment.It will be understood by those skilled in the art that in Figure 13
The structure shown, only the block diagram of part-structure relevant to application scheme, does not constitute and is applied to application scheme
The restriction of computer equipment 500 thereon, specific computer equipment 500 may include more more or fewer than as shown in the figure
Component perhaps combines certain components or with different component layouts.
Wherein, the processor 502 is for running computer program 5032 stored in memory, to realize following step
It is rapid:
Define one group of instruction；
Instruction is successively stored in memory address；
In use, according to interface circuit state out of specified memory address successively acquisition instruction；
Corresponding operation is executed according to order-driven interface circuit.
In one embodiment, processor 502 is implemented as follows step when realizing one group of instruction step of the definition:
All operational orders of each state in defining interface circuit；
Definition waits instruction；
Defining operation END instruction.
In one embodiment, all operational orders of each state in realizing the defining interface circuit of processor 502
When step, it is implemented as follows step:
Obtain the desired value of each clock cycle total interface signal of each state in interface circuit；
The each state of interface circuit is successively formed a string according to all desired values in the same state same clock cycle
Numerical value, to obtain all operational orders of each state in interface circuit.
In one embodiment, processor 502 realize it is described will instruction be successively stored in step in memory address when, specifically
Realize following steps:
Instruction stateful in interface circuit is sorted according to the clock cycle；
Instruction after sequence is successively stored in corresponding memory address.
In one embodiment, processor 502 is described in use, from specified memory according to interface circuit state in realization
In location successively acquisition instruction step when, be implemented as follows step:
In use, obtaining the current state of interface circuit；
The state current from interface circuit successively obtains the instruction in corresponding memory address.
In one embodiment, processor 502 is described according to the corresponding operation step of order-driven interface circuit execution in realization
When rapid, it is implemented as follows step:
According to acquired instruction out of memory address, each interface signal of interface circuit is successively set；
Judge whether current instruction is operation END instruction；
If so, switching interface circuit state, and according to new interface circuit state out of specified new memory address according to
Secondary acquisition instruction；
If it is not, then returning to each interface letter for successively setting interface circuit according to acquired instruction out of memory address
Number.
In one embodiment, processor 502 before step, also realizes following step before realizing one group of instruction of the definition
It is rapid:
The interface signal connecting with front stage circuits is set.
It should be appreciated that in the embodiment of the present application, processor 502 can be central processing unit (Central
Processing Unit, CPU), which can also be other general processors, digital signal processor (Digital
Signal Processor, DSP), specific integrated circuit (Application Specific Integrated Circuit,
ASIC), ready-made programmable gate array (Field-Programmable Gate Array, FPGA) or other programmable logic
Device, discrete gate or transistor logic, discrete hardware components etc..Wherein, general processor can be microprocessor or
Person's processor is also possible to any conventional processor etc..
Those of ordinary skill in the art will appreciate that be realize above-described embodiment method in all or part of the process,
It is that relevant hardware can be instructed to complete by computer program.The computer program includes program instruction, computer journey
Sequence can be stored in a storage medium, which is computer readable storage medium.The program instruction is by the department of computer science
At least one processor in system executes, to realize the process step of the embodiment of the above method.
Therefore, the present invention also provides a kind of storage mediums.The storage medium can be computer readable storage medium.This is deposited
Storage media is stored with computer program, and processor is made to execute following steps when wherein the computer program is executed by processor:
Define one group of instruction；
Instruction is successively stored in memory address；
In use, according to interface circuit state out of specified memory address successively acquisition instruction；
Corresponding operation is executed according to order-driven interface circuit.
In one embodiment, the processor realizes one group of instruction step of the definition executing the computer program
When, it is implemented as follows step:
All operational orders of each state in defining interface circuit；
Definition waits instruction；
Defining operation END instruction.
In one embodiment, the processor is realized every in the defining interface circuit in the execution computer program
When all operational order steps of a state, it is implemented as follows step:
Obtain the desired value of each clock cycle total interface signal of each state in interface circuit；
The each state of interface circuit is successively formed a string according to all desired values in the same state same clock cycle
Numerical value, to obtain all operational orders of each state in interface circuit.
In one embodiment, the processor is realized described will instruct and is successively stored in the execution computer program
In memory address when step, it is implemented as follows step:
Instruction stateful in interface circuit is sorted according to the clock cycle；
Instruction after sequence is successively stored in corresponding memory address.
In one embodiment, the processor is realized described in use, according to interface in the execution computer program
Circuit state out of specified memory address successively acquisition instruction step when, be implemented as follows step:
In use, obtaining the current state of interface circuit；
The state current from interface circuit successively obtains the instruction in corresponding memory address.
In one embodiment, the processor is realized described according to order-driven interface in the execution computer program
When circuit executes corresponding operating procedure, it is implemented as follows step:
According to acquired instruction out of memory address, each interface signal of interface circuit is successively set；
Judge whether current instruction is operation END instruction；
If so, switching interface circuit state, and return described in use, according to interface circuit state from specified memory
Successively acquisition instruction in address；
If it is not, then returning to each interface letter for successively setting interface circuit according to acquired instruction out of memory address
Number.
In one embodiment, the processor realizes one group of instruction step of the definition executing the computer program
Before, following steps are also realized:
The interface signal connecting with front stage circuits is set.
The storage medium can be USB flash disk, mobile hard disk, read-only memory (Read-Only Memory, ROM), magnetic disk
Or the various computer readable storage mediums that can store program code such as CD.
Those of ordinary skill in the art may be aware that list described in conjunction with the examples disclosed in the embodiments of the present disclosure
Member and algorithm steps, can be realized with electronic hardware, computer software, or a combination of the two, in order to clearly demonstrate hardware
With the interchangeability of software, each exemplary composition and step are generally described according to function in the above description.This
A little functions are implemented in hardware or software actually, the specific application and design constraint depending on technical solution.Specially
Industry technical staff can use different methods to achieve the described function each specific application, but this realization is not
It is considered as beyond the scope of this invention.
In several embodiments provided by the present invention, it should be understood that disclosed device and method can pass through it
Its mode is realized.For example, the apparatus embodiments described above are merely exemplary.For example, the division of each unit, only
Only a kind of logical function partition, there may be another division manner in actual implementation.Such as multiple units or components can be tied
Another system is closed or is desirably integrated into, or some features can be ignored or not executed.
The steps in the embodiment of the present invention can be sequentially adjusted, merged and deleted according to actual needs.This hair
Unit in bright embodiment device can be combined, divided and deleted according to actual needs.In addition, in each implementation of the present invention
Each functional unit in example can integrate in one processing unit, is also possible to each unit and physically exists alone, can also be with
It is that two or more units are integrated in one unit.
If the integrated unit is realized in the form of SFU software functional unit and when sold or used as an independent product,
It can store in one storage medium.Based on this understanding, technical solution of the present invention is substantially in other words to existing skill
The all or part of part or the technical solution that art contributes can be embodied in the form of software products, the meter
Calculation machine software product is stored in a storage medium, including some instructions are used so that a computer equipment (can be a
People's computer, terminal or network equipment etc.) it performs all or part of the steps of the method described in the various embodiments of the present invention.
The above description is merely a specific embodiment, but scope of protection of the present invention is not limited thereto, any
Those familiar with the art in the technical scope disclosed by the present invention, can readily occur in various equivalent modifications or replace
It changes, these modifications or substitutions should be covered by the protection scope of the present invention.Therefore, protection scope of the present invention should be with right
It is required that protection scope subject to.
Claims (10)
1. signal sequence configuration method characterized by comprising
Define one group of instruction；
Instruction is successively stored in memory address；
In use, according to interface circuit state out of specified memory address successively acquisition instruction；
Corresponding operation is executed according to order-driven interface circuit.
2. signal sequence configuration method according to claim 1, which is characterized in that one group of instruction of the definition, comprising:
All operational orders of each state in defining interface circuit；
Definition waits instruction；
Defining operation END instruction.
3. signal sequence configuration method according to claim 2, which is characterized in that each shape in the defining interface circuit
All operational orders of state, comprising:
From the phase for obtaining each clock cycle total interface signal of each state in interface circuit in interface circuit Protocol document
Prestige value；
The each state of interface circuit is successively formed into a string of numerical value according to all desired values in the same state same clock cycle,
To obtain all operational orders of each state in interface circuit.
4. signal sequence configuration method according to claim 3, which is characterized in that described that instruction is successively stored in memory
In address, comprising:
Instruction stateful in interface circuit is sorted according to the clock cycle；
Instruction after sequence is successively stored in corresponding memory address.
5. signal sequence configuration method according to claim 4, which is characterized in that described in use, according to interface circuit
State successively acquisition instruction out of specified memory address, comprising:
In use, obtaining the current state of interface circuit；
The state current from interface circuit successively obtains the instruction in corresponding memory address.
6. signal sequence configuration method according to claim 5, which is characterized in that described according to order-driven interface circuit
Execute corresponding operation, comprising:
According to acquired instruction out of memory address, each interface signal of interface circuit is successively set；
Judge whether current instruction is operation END instruction；
If so, switching interface circuit state, and return described in use, according to interface circuit state from specified memory address
Inside successively acquisition instruction；
If it is not, then returning according to acquired instruction out of memory address, each interface signal of interface circuit is successively set.
7. signal sequence configuration method according to any one of claims 1 to 6, which is characterized in that one group of the definition refers to
Before order, further includes:
The interface signal connecting with front stage circuits is set.
8. signal sequence configuration device characterized by comprising
Instruction definition unit, for defining one group of instruction；
Storage unit is successively stored in memory address for that will instruct；
Acquiring unit, in use, according to interface circuit state out of specified memory address successively acquisition instruction；
Execution unit, for executing corresponding operation according to order-driven interface circuit.
9. a kind of computer equipment, which is characterized in that the computer equipment includes memory and processor, on the memory
It is stored with computer program, the processor is realized as described in any one of claims 1 to 7 when executing the computer program
Method.
10. a kind of storage medium, which is characterized in that the storage medium is stored with computer program, the computer program quilt
Processor can realize the method as described in any one of claims 1 to 7 when executing.
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