CN108736884B - Frequency dividing method and circuit thereof - Google Patents
Frequency dividing method and circuit thereof Download PDFInfo
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- CN108736884B CN108736884B CN201710261312.1A CN201710261312A CN108736884B CN 108736884 B CN108736884 B CN 108736884B CN 201710261312 A CN201710261312 A CN 201710261312A CN 108736884 B CN108736884 B CN 108736884B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
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Abstract
A frequency dividing method is used for dividing an input frequency signal to provide an output frequency signal. The frequency division method comprises the following steps: providing a mask signal according to an input frequency signal and an overflow algorithm by using an arbiter; and performing a frequency division operation on the input frequency signal according to the mask signal by using a frequency gating unit to generate an output frequency signal.
Description
Technical Field
The present invention relates to a frequency dividing method and a circuit thereof, and more particularly, to a frequency dividing method and a circuit thereof implemented in a digital manner.
Background
The frequency divider circuit can generate a signal with an appropriate frequency according to a reference frequency signal, and thus is widely used in many applications. The Frequency divider circuit used in the chip is usually implemented by a Phase Lock Loop (PLL) of an analog circuit, but the PLL occupies a large proportion of chip area, and a Frequency signal generated by the PLL formed by the analog circuit has disadvantages such as Frequency Holes (Frequency hooks) and Frequency Offsets (Frequency Offsets). In view of the above, there is a real need for improvement.
Disclosure of Invention
The invention aims to provide a frequency dividing method and a frequency dividing circuit thereof, which realize a frequency divider in an integrated circuit of a chip in a digital mode and can achieve frequency reduction with any proportion and uniform distribution.
In accordance with the above objective of the present invention, a frequency dividing method is provided for performing a frequency dividing operation on an input frequency signal to provide an output frequency signal. The frequency division method comprises the following steps: providing a mask signal according to an input frequency signal and an overflow algorithm by using an arbiter; and performing a frequency division operation on the input clock signal according to the mask signal by using a frequency gating unit to generate an output clock signal, wherein the frequency of the output clock signal is M/N times the frequency of the input clock signal, wherein M, N is a positive integer, and M is less than N, wherein the overflow algorithm includes a basic value with an initial value of zero, and the overflow algorithm performs the following processes in sequence every time one cycle of the input clock signal is passed: providing an accumulated value, wherein the accumulated value is equal to the base value plus M; judging whether the accumulated value is greater than or equal to N; if the judgment result is negative, the shielding signal is at a low voltage level, and the basic value is updated to the accumulated value; and if the judgment result is yes, the shielding signal is at a high voltage level, and the basic value is updated to the accumulated value minus N.
In some embodiments, the clock gating cell includes a D-type latch including a data input terminal, an enable input terminal, and a data output terminal, and an and gate including a first input terminal, a second input terminal, and an output terminal.
In some embodiments, the data input terminal receives the mask signal, the enable input terminal receives the input clock signal in an inverted manner, the data output terminal is connected to the first input terminal, the second input terminal receives the input clock signal, and the output terminal outputs the output clock signal.
According to the above object of the present invention, a frequency divider circuit for frequency dividing an input frequency signal to provide an output frequency signal is provided. The frequency division method comprises an arbiter and a frequency gating unit. The arbiter is used for providing the mask signal according to the input frequency signal and the overflow algorithm. The frequency gating unit is configured to perform a frequency division operation on an input clock signal according to a mask signal to generate an output clock signal, wherein a frequency of the output clock signal is M/N times a frequency of the input clock signal, wherein M, N is a positive integer, and M is smaller than N, wherein the overflow algorithm includes a basic value with an initial value of zero, and the overflow algorithm performs the following processes in sequence every period of the input clock signal: providing an accumulated value, wherein the accumulated value is equal to the base value plus M; judging whether the accumulated value is greater than or equal to N; if the judgment result is negative, the shielding signal is at a low voltage level, and the basic value is updated to the accumulated value; and if the judgment result is yes, the shielding signal is at a high voltage level, and the basic value is updated to the accumulated value minus N.
In some embodiments, the clock gating cell includes a D-type latch including a data input terminal, an enable input terminal, and a data output terminal, and an and gate including a first input terminal, a second input terminal, and an output terminal.
In some embodiments, the data input terminal receives the mask signal, the enable input terminal receives the input clock signal in an inverted manner, the data output terminal is connected to the first input terminal, the second input terminal receives the input clock signal, and the output terminal outputs the output clock signal.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
Aspects of the invention will be better understood from the following detailed description taken in conjunction with the accompanying drawings. It is noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
FIG. 1 is a system block diagram showing a frequency divider circuit according to an embodiment of the present invention;
FIG. 2 is a flow chart showing steps performed by an overflow algorithm in a cycle according to one embodiment of the invention;
FIG. 3 is a schematic diagram showing the algorithm of overflow according to an application of the present invention;
FIG. 4 is a circuit architecture diagram of a frequency gating cell according to an embodiment of the present invention; and
fig. 5 is a flow chart showing a frequency dividing method according to an embodiment of the invention.
Detailed Description
The present invention provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention from that described herein. For example, if the following description refers to a first feature being formed over a second feature, this may include embodiments in which the first feature is in direct contact with the second feature; this may also include embodiments in which additional features are formed between the first and second features, such that the first and second features are not in direct contact. Additionally, the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Also, spatially relative terms, such as lower, upper, higher and the like, may be used for ease of explanation of the relationship of one element or feature to another element or feature in the figures. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. These devices may also be rotated (e.g., by 90 degrees or to other orientations) and the spatially relative descriptors used herein interpreted accordingly.
Fig. 1 is a system block diagram of a frequency divider circuit 100 according to an embodiment of the invention. The frequency divider circuit 100 is used for frequency dividing the input frequency signal CLKIN to provide the output frequency signal CLKOUT. The frequency divider circuit 100 includes an arbiter 110 and a frequency gating unit 120. The arbiter 110 receives the input frequency signal CLKIN, and the arbiter 110 outputs a MASK signal MASK. The clock gating unit 120 receives the input clock signal CLKIN and the MASK signal MASK, respectively, and the clock gating unit 120 outputs an output clock signal CLKOUT.
In the present invention, the frequency of the output clock signal CLKOUT is down-scaled by M/N relative to the frequency of the input clock signal CLKIN, wherein M, N is a positive integer, and M is smaller than N.
The arbiter 110 receives the input clock signal CLKIN and outputs the MASK signal MASK according to an overflow algorithm, wherein the overflow algorithm includes a basic value with an initial value of zero, and the overflow algorithm is performed once every cycle of the input clock signal CLKIN as shown in fig. 2. Referring to FIG. 2, a flowchart illustrating steps performed by an overflow algorithm in a cycle according to an embodiment of the invention is shown. First, in step S21, an accumulated value is provided, wherein the accumulated value is equal to the base value + M. Next, in step S22, it is determined whether the accumulated value is equal to or greater than N. If the determination result is no, step S23 is performed to set the MASK signal MASK to the low voltage level and set the base value to the accumulated value. If the determination result is yes, step S24 is performed to set the MASK signal MASK to the high voltage level and set the base value to the accumulated value-N. How the overflow algorithm shown in fig. 2 is calculated is further explained by application examples below.
FIG. 3 is a schematic diagram showing the algorithm of overflow according to an application of the present invention. In this application example, the initial value of the basic value is 0, M is 7, N is 10, and each time one cycle of the input clock signal CLKIN passes, the accumulated value is +7, and then the following determination and setting are performed: when the accumulated value is smaller than 10, setting the MASK signal MASK to a low voltage level and setting the base value to be the accumulated value; when the accumulated value is equal to or greater than 10, the MASK signal MASK is set to the high voltage level and the base value is set to the accumulated value-10. For example, in the first period of the input clock signal CLKIN: the accumulated value is 7, and the accumulated value is less than 10, so the MASK signal MASK is set to the low voltage level and the base value is set to 7. For example, in the second period of the input clock signal CLKIN: the accumulated value is 14, the accumulated value is greater than 10, so the MASK signal MASK is set to the high voltage level and the basic value is set to 4; and so on. In the present application example, the MASK signal MASK obtained by the calculation of the overflow bit algorithm is shown in fig. 3.
Fig. 4 is a circuit architecture diagram of the frequency gating unit 120 according to an embodiment of the invention. The frequency gating cell 120 includes a D-latch 122 and an AND gate 124. The data input terminal D of the D-type latch 122 receives the MASK signal MASK, the enable input terminal E of the D-type latch 122 inversely receives the input clock signal CLKIN, the data output terminal Q of the D-type latch 122 is connected to the first input terminal IN1 of the and gate 124, the second input terminal IN2 of the and gate 124 receives the input clock signal CLKIN, and the output terminal OUT of the and gate 124 outputs the output clock signal CLKOUT.
The frequency gating cell 120 may be implemented via a combination of circuits as shown in fig. 4: when the MASK signal MASK is at a high voltage level, the output clock signal CLKOUT is synchronized with the input clock signal CLKIN; when the MASK signal MASK is at the low voltage level, the output clock signal CLKOUT maintains the low voltage level. On the other hand, the output clock signal CLKOUT is at the high voltage level only when both the input clock signal CLKIN and the MASK signal MASK are at the high voltage level. Specifically, the frequency gating unit 120 determines a down-ratio of the frequency of the output clock signal CLKOUT relative to the frequency of the input clock signal CLKIN according to the MASK signal MASK.
Referring back to fig. 3, as described in the previous section, the output clock signal CLKOUT is at the high voltage level only when the input clock signal CLKIN and the MASK signal MASK are both at the high voltage level, so that in the present application, the output clock signal CLKOUT output after the input clock signal CLKIN and the MASK signal MASK pass through the clock gating unit 120 is as shown in fig. 3. As can be seen from fig. 3, the frequency of the output clock signal CLKOUT is 0.7 times the frequency of the input clock signal CLKIN. Note that the above magnification corresponds to M/N7/10.
It is worth mentioning that M and N can be values selected by the user. That is, the frequency divider 100 of the present invention can achieve any ratio of frequency reduction.
It should be noted that the overflow algorithm of the present invention is not too complex, i.e., the frequency divider 100 of the present invention will not increase the cost of the whole circuit greatly.
It should be noted that the MASK signal MASK is made into a signal with a more even distribution by the overflow algorithm, so that the distribution of the output clock signal CLKOUT obtained after frequency division is also more even. That is, the frequency divider 100 of the present invention can achieve a more evenly distributed frequency reduction. Thus, the burden on the back end of the first-in-first-out (FIFO) device can be reduced.
Fig. 5 is a flow chart illustrating a frequency dividing method 500 according to an embodiment of the invention. The frequency dividing method 500 digitally divides an input frequency signal provided by a chip to generate an output frequency signal. First, in step 510, the arbiter provides a mask signal according to the input clock signal and an overflow algorithm. Next, in step 520, the frequency gating unit performs a frequency division operation on the input frequency signal according to the mask signal to generate an output frequency signal.
In summary, the present invention provides a frequency dividing method and a circuit thereof, which, compared to the conventional phase-locked loop using an analog circuit to implement the frequency dividing function, the digital frequency dividing circuit of the present invention is implemented in the integrated circuit of the chip in a digital manner, so as to save the chip area occupation and avoid the disadvantages of frequency holes and frequency offset of the frequency signal generated by the conventional phase-locked loop. The frequency dividing method and the circuit thereof can achieve the frequency reduction with any proportion and even distribution by matching with the overflow algorithm.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. It should also be understood that they may not depart from the spirit and scope of the present invention, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present invention.
Description of the symbols
100: frequency divider circuit
110: arbitrator
120: frequency gating cell
122: d-type latch
124: and gate
500: method of producing a composite material
510. 520, S21-S24: step (ii) of
CLKIN: inputting frequency signal
CLKOUT: outputting a frequency signal
D: data input terminal
E: enabling input terminal
IN 1: a first input terminal
IN 2: second input terminal
MASK: shielding signals
OUT: output end
Q: data output terminal
Claims (6)
1. A frequency dividing method for frequency dividing an input frequency signal to provide an output frequency signal, the frequency dividing method comprising:
providing a mask signal according to the input frequency signal and an overflow algorithm by using an arbiter; and
performing a frequency division operation on the input frequency signal according to the mask signal using a frequency gating unit to generate the output frequency signal,
wherein the frequency of the output frequency signal is M/N times the frequency of the input frequency signal, wherein M, N is a positive integer, and M is less than N,
wherein the overflow algorithm comprises a basic value with an initial value of zero, and the overflow algorithm performs the following processes in sequence every time a cycle of the input clock signal passes through:
providing an accumulated value, wherein the accumulated value is equal to the base value plus M;
Judging whether the accumulated value is greater than or equal to N;
if the judgment result is negative, setting the shielding signal to be a low voltage level, and updating the basic value to the accumulated value; and
if the judgment result is yes, the shielding signal is set to be a high voltage level, and the basic value is updated to be the accumulated value minus N.
2. The method for frequency division according to claim 1, wherein the frequency gating cell comprises a D-latch and an AND gate, the D-latch comprising a data input, an enable input and a data output, the AND gate comprising a first input, a second input and an output.
3. The method for frequency division according to claim 2, wherein the data input terminal receives the mask signal, the enable input terminal receives the input frequency signal in an inverted manner, the data output terminal is connected to the first input terminal, the second input terminal receives the input frequency signal, and the output terminal outputs the output frequency signal.
4. A frequency divider circuit for frequency dividing an input frequency signal to provide an output frequency signal, the frequency divider circuit comprising:
an arbiter for providing a mask signal according to the input clock signal and an overflow algorithm; and
A frequency gating unit for performing frequency division operation on the input frequency signal according to the mask signal to generate the output frequency signal,
wherein the frequency of the output frequency signal is M/N times the frequency of the input frequency signal, wherein M, N is a positive integer, and M is less than N,
wherein the overflow algorithm comprises a basic value with an initial value of zero, and the overflow algorithm performs the following processes in sequence every time a cycle of the input clock signal passes through:
providing an accumulated value, wherein the accumulated value is equal to the base value plus M;
judging whether the accumulated value is greater than or equal to N;
if the judgment result is negative, the shielding signal is at a low voltage level, and the basic value is updated to the accumulated value; and
if the judgment result is yes, the shielding signal is at a high voltage level, and the basic value is updated to the accumulated value minus N.
5. The frequency divider circuit of claim 4, wherein the frequency gating cell comprises a D-latch having a data input, an enable input, and a data output, and an AND gate having a first input, a second input, and an output.
6. The frequency divider circuit of claim 5, wherein the data input terminal receives the mask signal, the enable input terminal receives the input frequency signal in an inverted manner, the data output terminal is connected to the first input terminal, the second input terminal receives the input frequency signal, and the output terminal outputs the output frequency signal.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6026498A (en) * | 1994-08-10 | 2000-02-15 | Fujitsu Limited | Clock signal generator circuit using a logical result of an output of a computer and a source clock to generate plurality of clock signals |
| CN1497407A (en) * | 2002-09-30 | 2004-05-19 | 英特尔公司 | Method and device for reducing clock frequency during low working capacity |
| CN101114832A (en) * | 2006-07-28 | 2008-01-30 | 晨星半导体股份有限公司 | Delta-sigma modulated fractional-n pll frequency synthesizer |
| TW200926601A (en) * | 2007-12-03 | 2009-06-16 | Ind Tech Res Inst | Spread spectrum clock generating apparatus |
| CN104601146A (en) * | 2013-10-31 | 2015-05-06 | 精工爱普生株式会社 | Clock generating device, electronic apparatus, moving object, and clock generating method |
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2017
- 2017-04-20 CN CN201710261312.1A patent/CN108736884B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6026498A (en) * | 1994-08-10 | 2000-02-15 | Fujitsu Limited | Clock signal generator circuit using a logical result of an output of a computer and a source clock to generate plurality of clock signals |
| CN1497407A (en) * | 2002-09-30 | 2004-05-19 | 英特尔公司 | Method and device for reducing clock frequency during low working capacity |
| CN101114832A (en) * | 2006-07-28 | 2008-01-30 | 晨星半导体股份有限公司 | Delta-sigma modulated fractional-n pll frequency synthesizer |
| TW200926601A (en) * | 2007-12-03 | 2009-06-16 | Ind Tech Res Inst | Spread spectrum clock generating apparatus |
| CN104601146A (en) * | 2013-10-31 | 2015-05-06 | 精工爱普生株式会社 | Clock generating device, electronic apparatus, moving object, and clock generating method |
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