CN207896957U - A kind of high-speed frequency divider - Google Patents
A kind of high-speed frequency divider Download PDFInfo
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- CN207896957U CN207896957U CN201820243607.6U CN201820243607U CN207896957U CN 207896957 U CN207896957 U CN 207896957U CN 201820243607 U CN201820243607 U CN 201820243607U CN 207896957 U CN207896957 U CN 207896957U
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Abstract
The utility model discloses a kind of high-speed frequency dividers, including subtraction circuit, negative circuit and add circuit.Subtraction circuit receives N frequency dividing ratio signals and input clock signal and provides subtraction signal；Negative circuit receives the subtraction signal and provides anti-reflection signal；Add circuit receives position height (N 1) of the anti-reflection signal and frequency dividing ratio signal, provides carry signal.In even frequency division, which can obtain the carry signal that duty ratio is 50% as fractional frequency signal, avoid frequency jitter；In frequency division by odd integers, carry signal is compensated or adjusted, can equally obtain the fractional frequency signal that duty ratio is 50%.
Description
Technical field
The utility model is related to a kind of high-speed frequency dividers, more specific to be still not exclusively to duty cycle adjustment work(
The frequency divider of energy.
Background technology
In contemporary electronic systems, the ratio shared by digital electronic system is increasing.In digital logic circuit design,
Frequency divider is a kind of basic circuit, commonly used to be divided to some given frequency, obtains required frequency.Application at present is most
It is widely the frequency synthesis technique based on phaselocked loop, it can synthesize very high frequency, while phase noise is also smaller, because
This is using extremely wide.At a high speed, the frequency divider design of 50% duty ratio is always the difficult point in Design of PLL.It is public at present
The divider circuit known is complicated, and can bring the shake between period and period.How to improve, so that frequency divider is electric
Road is simple, and has that the ability of 50% duty ratio input clock signal is all exported when odd and even number divides is art technology
Personnel's technical issues that need to address.
Utility model content
To solve the above problems, the utility model provides a kind of high-speed frequency divider, including：Subtraction circuit has first
Input terminal, the second input terminal and output end, the first input end and the second input terminal receive frequency dividing ratio signal and input respectively
Clock signal, the subtraction circuit are based on the input clock signal and carry out subtraction to frequency dividing ratio signal, and in its output
End provides subtraction signal, and the frequency dividing ratio signal is N position digital signals, and wherein N is the integer more than 1；Negative circuit has defeated
Enter end and output end, input terminal is coupled to the output end of the subtraction circuit to receive the subtraction signal, and output end carries
For anti-reflection signal；And add circuit, there is first input end, the second input terminal and output end, first input end to be coupled to
For the output end of the negative circuit to receive the anti-reflection signal, the second input terminal, which receives, divides high half signal, the frequency dividing
High half signal is position height (N-1) of frequency dividing ratio signal, and output end provides carry signal, and the add circuit believes the anti-reflection
Number and high half signal of the frequency dividing carry out add operation.
The high-speed frequency divider can rapidly and accurately divide input clock signal according to frequency dividing ratio signal, due to adopting
With digital control, it is directly based upon clock signal and is divided, avoid frequency jitter.In even frequency division, the high speed
Frequency divider can obtain the fractional frequency signal that duty ratio is 50%, avoid frequency jitter.In frequency division by odd integers, carry is believed
It number compensates or adjusts, can equally obtain the fractional frequency signal that duty ratio is 50%.
Description of the drawings
Fig. 1 shows the circuit diagram of the high-speed frequency divider 10 of one embodiment according to the present utility model；
Fig. 2 shows the operation oscillograms 20 for adjusting circuit；
Fig. 3 shows to adjust the operation oscillogram 30 of circuit；
Fig. 4 shows the adjusting circuit 40 of one embodiment according to the present utility model；
Fig. 5 shows the adjusting circuit 50 of one embodiment according to the present utility model；
Fig. 6 shows the adjusting circuit 60 of one embodiment according to the present utility model；
Fig. 7 shows the adjusting circuit 70 of one embodiment according to the present utility model.
Specific implementation mode
The specific embodiment being described below represents the exemplary embodiment of the utility model, and substantially merely illustrative
It is illustrative and not limiting.In the description, refer to that " one embodiment " or " embodiment " means to combine described by the embodiment
Special characteristic, structure or characteristic be included at least one embodiment of the utility model.Term is " in one embodiment
In " in the description each position occur not all referring to identical embodiment, nor mutually exclusive other embodiment or
Person's various embodiments.All features disclosed in this specification or disclosed all methods or in the process the step of, in addition to mutual
Other than the feature and/or step of repulsion, it can combine in any way.
Specific embodiment of the present utility model is described in detail below with reference to the accompanying drawings.Through the identical attached drawing of all attached drawings
Label indicates identical component or feature.
Fig. 1 shows that the circuit diagram of the high-speed frequency divider 10 according to the utility model one embodiment, frequency divider 10 wrap
It includes subtraction circuit 101, negative circuit 102, add circuit 103 and adjusts circuit 104.Subtraction circuit 101 has the first input
End, the second input terminal and output end, first input end and the second input terminal receive frequency dividing ratio signal DIV respectively<N:0>With it is defeated
Enter clock signal CKIN, frequency dividing ratio signal DIV<N:0>For N position digital signals, wherein N is the integer more than 1.Subtraction circuit 101
Based on input clock signal CKIN to frequency dividing ratio signal DIV<N:0>Count with subtraction and subtracts in the offer of its output end
Method signal DIV_O<N:0>.In one embodiment, in the rising edge of each input clock signal CKIN, subtraction circuit 101 will
Frequency dividing ratio signal DIV<N:0>Subtract 1, such as in first rising edge of input clock signal CKIN by frequency dividing ratio signal DIV<N:0>
110 are kept to by 111, in the next rising edges of input clock signal CKIN by frequency dividing ratio signal DIV<N:0>It is kept to by 110
101 ... ..., by frequency dividing ratio signal DIV<N:0>111 are kept to by 000, it specifically can be with reference table 1.In other examples,
Subtraction circuit 101 can also input clock signal CKIN each failing edge by frequency dividing ratio signal DIV<N:0>Subtract 1 successively.
There is negative circuit 102 input terminal and output end, input terminal to be coupled to the output end of subtraction circuit 101 to connect
Receive subtraction signal DIV_O<N:0>, subtraction signal DIV_O of the negative circuit 102 to input<N:0>Reverse phase is carried out, output end carries
For anti-reflection signal DIV_N<N:0>.In one embodiment, if subtraction signal DIV_O<N:0>Be 101, then anti-reflection signal DIV_N
<N:0>It is 010, with specific reference to table 1.Negative circuit 102 can be realized with multiple phase inverters.
There is add circuit 103 control terminal, first input end, the second input terminal and output end, first input end to be coupled to
The output end of negative circuit 102 is to receive the anti-reflection signal DIV_N of the output of negative circuit 102<N:0>, the second input terminal, which receives, to be divided
Frequently high half signal DIV<N:1>, divide high half signal DIV<N:1>For frequency dividing ratio signal DIV<N:0>The position height (N-1).At one
In embodiment, if frequency dividing ratio signal DIV<N:0>For 111 (corresponding ten's digits 7), then the high position (N-1) be 11 (corresponding ten into
System number is 3)；If frequency dividing ratio signal DIV<N:0>For 110 (corresponding ten's digits 6), then the high position (N-1) be 11 (corresponding ten into
System is digital 3), referring specifically to table 1.In digital signal, the position (N-1) is approximately divided by 2 before taking, therefore DIV<N:1>Referred to as frequency dividing is high by half
Signal.Those skilled in the art can also use divides high half signal DIV as under type understands<N:1>：Frequency dividing ratio is believed
Number DIV<N:0>Extreme lower position 0, then divided by 2.If such as frequency dividing ratio signal DIV<N:0>It is 111, is 110 after lowest order zero setting
011 (011 i.e. 11, corresponding ten's digit 3) is obtained after (corresponding ten's digit 6) divided by 2, referring specifically to table 1.
The anti-reflection signal DIV_N that add circuit 103 exports negative circuit 102<N:0>With the high half signal DIV of frequency dividing<N:1
>Additional calculation is carried out, and carry signal CO is provided in output end.In one embodiment, if the high half signal DIV of frequency dividing<
N:1>With the anti-reflection signal DIV_N<N:0>The sum of need carry, then carry signal CO is 1, such as 110+010=1000, then into
Position signal CO is 1.If the high half signal DIV of frequency dividing<N:1>With the anti-reflection signal DIV_N<N:0>The sum of be not necessarily to carry, then
The carry signal is 0, such as 100+010=110, then carry signal CO is 0.In another embodiment it is also possible to will
Whether carry is corresponding is indicated to need carry with 0, and 1 indicates to be not necessarily to carry.In one embodiment, add circuit also has control
End, to receive input clock signal CKIN, the input clock signal CKIN based on control terminal is to anti-reflection signal DIV_N<N:0>
With the high half signal DIV of frequency dividing<N:1>Carry out additional calculation.In one embodiment, in input clock signal CKIN rising edges or
Failing edge is by anti-reflection signal DIV_N<N:0>With the high half signal DIV of frequency dividing<N:1>Carry out add operation/calculating.
Circuit 104 is adjusted, there is control terminal, first input end, the second input terminal and output end, control terminal to receive input
Clock signal CKIN, first input end receive frequency dividing low level signal DIV<0>(i.e. frequency dividing ratio signal DIV<N:0>Lowest order),
Its second input terminal is coupled to the output end of add circuit 103 to receive carry signal CO, and output end provides duty ratio essence
Upper is 50% output signal CKOUT.In one embodiment, if the lowest order of the frequency dividing ratio signal is first state (example
Such as 0, even frequency division), 104 direct output carry signal CO of circuit is adjusted as fractional frequency signal CKOUT, i.e. fractional frequency signal CKOUT
The substantially equal to described carry signal CO；If the frequency dividing ratio signal DIV<N:0>Lowest order be the second state (such as 1, very
Number frequency dividing), the adjusting circuit 104 is adjusted such that the fractional frequency signal to the pulse width of the carry signal CO
Duty ratio is substantially equal to 50%.In other words, if without circuit 104 is adjusted, it is fractional frequency signal directly to provide carry signal CO, also may be used
It realizes digital control high speed frequency dividing, obtains stable required frequency；It is added and adjusts circuit 104, can also realize duty cycle adjustment,
No matter frequency division by odd integers or even frequency division, can obtain duty ratio be 50% fractional frequency signal.
Table 1
As shown in table 1 and Fig. 2, it is assumed that frequency dividing ratio signal DIV<N:0>It is 100, then divides high half signal DIV<N:1>For
010 (0 is mended before 10), frequency dividing low level signal DIV<0>It is 0.When input clock signal CKIN pulses (such as rising edge) arrive
(period 1 T1), subtraction circuit 101 is to frequency dividing ratio signal DIV<N:0>Carry out a subtraction, the subtraction letter of output end
Number DIV_O<N:0>It is 011, by negative circuit 102, anti-reflection signal DIV_N<N:0>It is 100, this anti-reflection signal DIV_N<
N:0>(100) input terminal of add circuit 103, and the high half signal DIV of frequency dividing are transferred into<N:1>Signal (010) is defeated
Enter the lower progress of clock signal CKIN controls and add operation entirely, is i.e. 100+010=110, due to being not necessarily to carry, carry signal CO is 0.
The lower periods (second round T2) of input clock signal CKIN, subtraction circuit 101 is to frequency dividing ratio signal DIV<N:0>One is carried out again
Secondary subtraction, i.e. the subtraction signal DIV_O of its output end<N:0>Become 010 from 011, by negative circuit 102, anti-reflection letter
Number DIV_N<N:0>It is 101, this anti-reflection signal DIV_N<N:0>(101) it is transferred into an input terminal of add circuit 103,
With the high half signal DIV of frequency dividing<N:1>Signal (010) carries out adding operation, i.e. 101+010 entirely under input clock signal CKIN controls
=111, due to being not necessarily to carry, i.e. carry signal CO continues to remain 0 in second round T2.One at input clock signal CKIN
In the period (period 3 T3), subtraction circuit 101 is to frequency dividing ratio signal DIV<N:0>A subtraction, i.e. its output end are carried out again
Subtraction signal DIV_O<N:0>Become 001 from 010, by negative circuit 102, anti-reflection signal DIV_N<N:0>It is 110, this
Anti-reflection signal DIV_N<N:0>(110) input terminal of add circuit 103, and the high half signal DIV of frequency dividing are transferred into<N:1>
Signal (010) is carried out under input clock signal CKIN controls entirely plus operation, i.e. 110+010=1000, carry signal CO are 1,
Other work-based logics and sequential refer to table 1 and Fig. 2.As shown in Fig. 2, in period 1 T1 and second round T2, carry signal CO
Be 0, period 3 T3 and period 4 T4, carry signal CO be 1, i.e., carry signal form a cycle (CT1, CT2 or
CT3 the clock signal that) be four times of input clock signal period (T1, T2 ... T11 or T12) and duty ratio is 50%, that is, realize
Four frequency dividing (frequency dividing ratio signal DIV<N:0>It is 100,4) corresponding ten's digit is.Frequency dividing ratio signal DIV<N:0>Most
Low level is 0 (representing even frequency division), adjusts 104 direct output carry signal CO of circuit as fractional frequency signal CKOUT, i.e. frequency dividing letter
Number CKOUT is substantially equal to the carry signal CO.Before period 1 T1, due to not to carry signal CO and fractional frequency signal
CKOUT carries out state analysis, therefore its state is represented by dashed line in Fig. 2.
As shown in Table 2 and Fig. 3, it is assumed that frequency dividing ratio signal DIV<N:0>It is 101, then divides high half signal DIV<N:1>For
010, frequency dividing low level signal DIV<0>It is 1.(the period 1 when input clock signal CKIN pulses (such as rising edge) arrive
T1), subtraction circuit 101 is to frequency dividing ratio signal DIV<N:0>Carry out a subtraction, the subtraction signal DIV_O of output end<
N:0>It is 100, by negative circuit 102, anti-reflection signal DIV_N<N:0>It is 011, this anti-reflection signal DIV_N<N:0>(011)
It is transferred into an input terminal of add circuit 103, and the high half signal DIV of frequency dividing<N:1>Signal (010) is in input clock signal
CKIN controls are lower to be carried out adding operation entirely, i.e. 011+010=101, due to being not necessarily to carry, carry signal CO is 0.Believe in input clock
Number lower periods (second round T2) of CKIN, subtraction circuit 201 is to frequency dividing ratio signal DIV<N:0>A subtraction is carried out again,
That is the subtraction signal DIV_O of its output end<N:0>It is 011, by negative circuit 102, anti-reflection signal DIV_N<N:0>It is 100,
This anti-reflection signal DIV_N<N:0>(100) input terminal of add circuit 103, and the high half signal DIV of frequency dividing are transferred into<
N:1>Signal (010) carries out entirely plus operation under input clock signal CKIN control, i.e. 100+010=110, due to be not necessarily into
Position, i.e. carry signal CO continue to remain 0 in second round T2.One (the period 3 in period at input clock signal CKIN
T3), subtraction circuit 101 is to frequency dividing ratio signal DIV<N:0>A subtraction, the i.e. subtraction signal of its output end are carried out again
DIV_O<N:0>It is 010, by negative circuit 102, anti-reflection signal DIV_N<N:0>It is 101, this anti-reflection signal DIV_N<N:0
>(101) input terminal of add circuit 103, and the high half signal DIV of frequency dividing are transferred into<N:1>Signal (010) is in input
The CKIN controls of clock signal are lower to be carried out adding operation entirely, i.e. 101+010=111, i.e. carry signal CO continue to keep in period 3 T3
It is 0.In one period (period 4 T4) at input clock signal CKIN, subtraction circuit 101 is to frequency dividing ratio signal DIV<N:0>Again
Carry out a subtraction, i.e. the subtraction signal DIV_O of its output end<N:0>It is 001, by negative circuit 102, anti-reflection signal
DIV_N<N:0>It is 110, this anti-reflection signal DIV_N<N:0>(110) it is transferred into an input terminal of add circuit 103, and
Divide high half signal DIV<N:1>Signal (010) carries out adding operation, i.e. 110+010=entirely under input clock signal CKIN controls
1000, carry signal CO are 1, other work-based logics and sequential refer to table 2 and Fig. 3.
As shown in Fig. 2, in period 1 T1, second round T2 and period 3 T3, carry signal CO is 0, the period 4
T4 and period 5 T5, carry signal CO are 1, i.e., it is input clock that carry signal, which forms a cycle (CT1, CT2 or CT3),
The clock signal that five times of signal period (T1, T2 ... T14 or T15) and duty ratio are 40%, that is, realize five frequency dividing (frequency dividing ratios
Signal DIV<N:0>It is 101,5) corresponding ten's digit is.
Frequency dividing ratio signal DIV<N:0>Lowest order be 1 (representing frequency division by odd integers), adjust circuit 104 to the carry signal
The pulse width of CO is adjusted such that the duty ratio of the fractional frequency signal is substantially equal to 50%.According to the utility model one
A embodiment, as shown in figure 3, the carry signal adjusted signal CO ' of CO are sampled in input clock signal CKIN failing edges, it will be into
Position signal CO and Regulate signal CO ' takes OR (or logic) to obtain the output frequency division clock i.e. CKOUT that duty ratio is 50%.In addition
In one embodiment, can also with logic or other logics.
Table 2
Before period 1 T1, due to not carrying out state analysis to carry signal CO and fractional frequency signal CKOUT, therefore in Fig. 3
Its state is represented by dashed line.
Subtraction circuit 101, negative circuit 102, add circuit 103 are common circuits, are no longer illustrated herein.
Fig. 4 shows the adjusting circuit 40 of one embodiment according to the present utility model, adjusts circuit 40 and includes：
There is compensation circuit 41 first input end, the second input terminal and output end, first input end to receive the input
Clock signal CKIN, the second input terminal receive the carry signal CO, and the compensation circuit 41 is based on the clock signal
CKIN compensates the pulse width of the carry signal CO and provides the thermal compensation signal CP that duty ratio is 50% in output end；
And
Selection circuit 42 has selection end, first input end, the second input terminal and output end, selects described in the reception of end
Divide low level signal DIV<0>(lowest order of frequency dividing ratio signal), first input end receive the carry signal CO, and second
Input terminal receives the thermal compensation signal CP, and one is selected to provide the fractional frequency signal CKOUT in its output end.Work as even frequency division
When, it is fractional frequency signal CKOUT directly to provide carry signal CO, and when frequency division by odd integers compensates the duty ratio of carry signal CO to 50%
It is re-used as fractional frequency signal output.
Fig. 5 shows the adjusting circuit 50 of one embodiment according to the present utility model, adjusts circuit 50 and includes：
There is first phase inverter I1 input terminal and output end, input terminal to be coupled to frequency dividing low level signal DIV<0>, divide low
Position signal DIV<0>Output signal DIV_N is obtained by the first phase inverter I1<0>.
There is first and door A1 first input end, the second input terminal and output end, first input end to be coupled to add circuit
For 103 output end to receive the carry signal CO of add circuit 103, the second input terminal is coupled to the output end of phase inverter I1 to connect
Receive the output signal DIV_N of phase inverter I1<0>, the input signal of first input end and the second input terminal passes through with operation first
Output signal AO1 is generated with the output end of door A1.
Second and door A2 has first input end, the second input terminal and output end, first input end input frequency dividing low level letter
Number DIV<0>, the second input terminal is coupled to the output end of add circuit 103 to receive the carry signal CO of add circuit 103, and
The output end that the input signal of one input terminal and the second input terminal passes through with operation in second and door A2 generates output signal AO2.
There is second phase inverter I2 input terminal and output end, input terminal to receive input clock signal CKIN, input clock letter
Number CKIN obtains output signal CKIN_N by the second phase inverter A2.
There is d type flip flop D1 first input end, the second input terminal and output end, first input end to be coupled to second and door
For the output end of A2 to receive the output signal AO2 of second and door A2, the second input terminal is coupled to the output end of the second phase inverter I2
To receive the output signal CKIN_N of phase inverter I2, the input signal of first input end and the second input terminal passes through d type flip flop D1,
Output signal DO1 is generated in its output end.
There is first or door O1 first input end, the second input terminal and output end, first input end to be coupled to first and door
Output end to receive the output signal AO1 of first and door, the second input terminal is coupled to the output end of d type flip flop D1 to receive D
The first input end of the output signal DO1, first or door O1 of trigger D1 and the input signal process of the second input terminal or operation
Output signal OUT1 is generated in its output end.
There is second or door O2 first input end, the second input terminal and output end, first input end to be coupled to first or door
For the output end of O1 to receive the output signal OUT1 of first or door O1, the second input terminal is coupled to the output end of add circuit 103
To receive the first input end of the carry signal CO, second or door O2 of add circuit 103 and the input signal warp of the second input terminal
It crosses or operation generates output signal CKOUT in its output end.
Adjust circuit 60 logical expression be：CKOUT=CO ↑ DIV_N<0>+CO↓·DIV<0>+ CO ↑ (" CO ↑ " generation
Carry signal CO when table input clock signal CKIN rising edges arrive, " CO ↓ " represents input clock signal CKIN failing edges and arrives
Carry signal CO when coming).
This adjusts circuit and adds data selection function, can be to odd number or even frequency division than signal DIV<N:0>Into
Row selection, to decide whether that carry signal CO is adjusted, to realize final either frequency division by odd integers also than input signal
It is even frequency division than input signal, the output clock signal of 50% duty ratio is all obtained by frequency dividing circuit.Divide low level signal
DIV<0>(lowest order of input frequency dividing ratio signal) due to being binary digit, only there are two types of values：0 or 1, both values are just
Representing all odd number even frequency divisions may.As frequency dividing low level signal DIV<0>When=0, it is meant that the frequency dividing ratio signal of input is
Even frequency division is than signal, and when a rising edge clock arrives, the first phase inverter I1 outputs are 1, first and door A1 outputs are CO
↑, second with door A2 output is 0, d type flip flop D1 outputs be 0, first or door O1 outputs be CO ↑, second or door O2 export for CO ↑
That is CKOUT=CO ↑, by logical expression also recall that CKOUT=CO ↑, that is, export clock signal CKOUT be input clock letter
Carry signal CO when number CKIN rising edges arrive；Work as DIV<0>When=1, it is meant that the frequency divider frequency dividing ratio signal of input is strange
Number frequency dividing ratio signal, when a rising edge clock arrives, the first phase inverter I1 outputs are 0, first and door A1 outputs are 0, the
Two with door output be CO ↑, when the failing edge of this clock arrives, d type flip flop D1 generate non-zero outputs CO ↓, first or door O1 is defeated
Go out for CO ↓, second or door O2 outputs be CO ↑+CO ↓, i.e. CKOUT=CO ↑+CO ↓, CKOUT is equally obtained by logical expression
=CO ↑+CO ↓, that is, export the carry signal that clock signal CKOUT is add circuit when input clock signal CKIN rising edges arrive
When CO and input clock CKIN failing edges arrive the carry signal CO phases of add circuit or as a result, this output clock signal is
By the signal of duty cycle adjustment (compensation), it has 50% duty ratio.
Fig. 6 shows the adjusting circuit diagram 60 of one embodiment according to the present utility model.Adjusting circuit 60 includes：
There is first d type flip flop D1 first input end, the second input terminal and output end, first input end to be coupled to addition
The output end of circuit 103, to receive 103 carry signal CO of add circuit, the second input terminal receives input clock signal CKIN, the
The input signal of one input terminal and the second input terminal passes through d type flip flop D1, and output signal DO1 is generated in its output end；
There is first phase inverter I1 input terminal and output end, input terminal to receive input clock signal CKIN, input clock letter
Number CKIN obtains output signal CKIN_N by the first phase inverter I1；
There is second d type flip flop D2 first input end, the second input terminal and output end, first input end to be coupled to addition
The output end of circuit 103, to receive 103 carry signal CO of add circuit, the second input terminal is coupled to the defeated of the first phase inverter I1
Outlet is to receive the output signal CKIN_N of the first phase inverter I1, and the input signal of first input end and the second input terminal is by the
2-D trigger D2 generates output signal DO2 in its output end；
There is first or door O1 first input end, the second input terminal and output end, first input end to be coupled to the first D and touch
The output end of device D1 is sent out to receive the output signal DO1 of the first d type flip flop, the second input terminal is coupled to the second d type flip flop D2's
Output end to receive the output signal DO2 of the second d type flip flop D2, the input signal of first input end and the second input terminal pass through or
Output end of the operation in first or door O1 generates output signal OUT1；
First NAND gate N1, have first input end, the second input terminal and output end, first input end be coupled to first or
For the output end of door O1 to receive the output signal OUT1 of first or door O1, the second input terminal is coupled to frequency dividing low level signal DIV<0
>, the input signal of first input end and the second input terminal generates output letter by NAND operation in the first NAND gate N1 output ends
Number NOUT1；
There is second phase inverter I2 input terminal and output end, input terminal to be coupled to frequency dividing low level signal DIV<0>, divide low
Position signal DIV<0>Output signal DIV_N is generated by the second phase inverter I2<0>；
Second NAND gate N2 has first input end, the second input terminal and output end, and it is anti-that first input end is coupled to second
The output end of phase device I2 is to receive the output signal DIV_N of the second phase inverter I2<0>, the second input terminal is coupled to add circuit
103 output end is to receive the carry signal CO of add circuit 103, the input signal process of first input end and the second input terminal
Output end of the NAND operation in the second NAND gate N2 generates output signal NOUT2；
Third NAND gate N3, have first input end, the second input terminal and output end, first input end be coupled to first with
For the output end of NOT gate N1 to receive the output signal NOUT1 of the first NAND gate N1, the second input terminal is coupled to the second NAND gate N2
Output end to receive the output signal NOUT2 of the second NAND gate N2, the input signal warp of first input end and the second input terminal
The output end that NAND operation is crossed in third NAND gate N3 generates output signal CKOUT.
Its logical expression is：CKOUT=CO ↑ DIV_N<0>+(CO↓+CO↑)·DIV<0>.This duty cycle adjustment
(compensation) circuit equally adds data selection function, can be selected than signal odd number or even frequency division, to certainly
The fixed adjusting (compensation) that circuit whether is carried out by compensation circuit, to realize final either odd divider frequency dividing ratio input letter
Number or even number divider frequency dividing ratio input signal, the output clock signal of 50% duty ratio can be obtained by frequency dividing circuit.
Work as DIV<0>When=0, it is meant that the frequency dividing ratio signal of input be even frequency division than signal, when an input clock CKIN rising edge
No matter what signal the first input end of N1 inputs when arrival, NOUT1 outputs are all 1, while the output letter of the second phase inverter I2
Number DIV_N<0>=1, N2 output are CO ↑ negate, N3 outputs be CO ↑, by logical expression also recall that CKOUT=CO ↑, i.e.,
It is carry signal when input clock signal CKIN rising edges arrive to export clock signal CKOUT；Work as DIV<0>When=1, meaning
The frequency dividing ratio signal for input is frequency division by odd integers than signal, when an input clock CKIN rising edge arrives, the second phase inverter
The output signal DIV_N of I2<0>=0, no matter the second input signal CO of N2 ↑ why be worth, the output NOUT2 of N2 is 1, together
When, the first d type flip flop D1 outputs CO ↑, when this input clock signal CKIN failing edges arrive, the second d type flip flop D2 exports CO
↓, first or door output OUT1=CO ↑+CO ↓, NOUT1 output be (CO ↑+CO ↓) negates, NOUT3 output be CO ↑+CO ↓, pass through
Logical expression be known that CKOUT=CO ↑+CO ↓, that is, it is input clock signal CKIN rising edges to export clock signal CKOUT
Carry signal CO when carry signal CO when arrival arrives with input clock signal CKIN failing edges carry out or operation as a result,
This output clock signal is equally by the signal of duty cycle adjustment (compensation), it has 50% duty ratio.
Fig. 7 shows the adjusting circuit diagram 70 of one embodiment according to the present utility model.Compared with adjusting circuit 60, adjust
The main distinction of circuit 70 is：Second d type flip flop D2 has first input end, the second input terminal and output end, the first input
End is coupled to the first d type flip flop D1 output ends (receive the first d type flip flop D1 output signal DO1) rather than add circuit 103
Output end (receive 103 carry signal CO of add circuit).
Although the utility model has been combined its specific illustrative embodiment and is described, it is therefore apparent that, it is a variety of
Alternatively, modification and variation are apparent to those skilled in the art.The example of the utility model illustrated herein as a result,
Property embodiment is schematical and and non-limiting.It can make in the case where not departing from the spirit and scope of the utility model
Go out modification.In every case it is the content without departing from technical solutions of the utility model, according to the technical essence of the utility model to above real
Any simple modification, equivalent change and modification made by example are applied, are still within the scope of the technical solutions of the present invention.
In this disclosure used quantifier "one", "an" etc. be not excluded for plural number." first " in text, "
Two " etc. are merely represented in the sequencing occurred in the description of embodiment, in order to distinguish like." first ", " second " exist
Appearance in claims is only for the purposes of the fast understanding to claim rather than in order to be limited.Right is wanted
Any reference numeral in book is asked to should be construed as the limitation to range.
Claims (10)
1. a kind of high-speed frequency divider, including：
Subtraction circuit has first input end, the second input terminal and output end, the first input end and the second input terminal difference
Frequency dividing ratio signal and input clock signal are received, the subtraction circuit is based on the input clock signal and is carried out to frequency dividing ratio signal
Subtraction, and subtraction signal is provided in its output end, the frequency dividing ratio signal is N position digital signals, and wherein N is more than 1
Integer；
Negative circuit has input terminal and output end, and it is described to receive that input terminal is coupled to the output end of the subtraction circuit
Subtraction signal, output end provide anti-reflection signal；And
There is add circuit first input end, the second input terminal and output end, first input end to be coupled to the negative circuit
Output end to receive the anti-reflection signal, the second input terminal, which receives, divides high half signal, and high half signal of frequency dividing is point
Position height (N-1) of frequency ratio signal, output end provide carry signal, and the add circuit is to the anti-reflection signal and the frequency dividing
High half signal carries out add operation.
2. high-speed frequency divider according to claim 1, which is characterized in that the subtraction includes：In each input
The rising edge or failing edge of clock signal, the frequency dividing ratio signal subtract 1 successively.
3. high-speed frequency divider according to claim 1, which is characterized in that if high half signal of frequency dividing is believed with the anti-reflection
Number the sum of need carry, then the carry signal be 1；If frequency dividing the sum of high half signal and the anti-reflection signal are not necessarily to carry,
Then the carry signal is 0.
4. high-speed frequency divider according to claim 1, which is characterized in that add circuit also has control terminal, to receive
Input clock signal, in the input clock signal rising edge or failing edge, the add circuit is high to anti-reflection signal and frequency dividing
Half signal carries out add operation.
5. high-speed frequency divider according to claim 1, which is characterized in that the high-speed frequency divider further includes adjusting circuit,
There is the adjusting circuit control terminal, first input end, the second input terminal and output end, control terminal to receive the input clock
Signal, first input end receive the lowest order of the frequency dividing ratio signal, and the second input terminal is coupled to the add circuit
For output end to receive the carry signal, output end provides fractional frequency signal, wherein
If the lowest order of the frequency dividing ratio signal is first state, the fractional frequency signal is substantially equal to the carry signal；
If the lowest order of the frequency dividing ratio signal is the second state, it is described adjust circuit to the pulse width of the carry signal into
Row is adjusted to provide the fractional frequency signal that duty ratio is substantially equal to 50%.
6. high-speed frequency divider according to claim 5, which is characterized in that the pulse width to the carry signal
It is adjusted including adding or subtracting input clock signal pulse width for the pulse width of the carry signal.
7. high-speed frequency divider according to claim 5, which is characterized in that the duty ratio of the input clock signal is
50%, the adjusted signal of carry signal is sampled in input clock signal failing edge, carry signal and Regulate signal are taken or patrolled
It collects and obtains the fractional frequency signal that duty ratio is 50%.
8. high-speed frequency divider according to claim 5, which is characterized in that the adjusting circuit includes：
There is compensation circuit first input end, the second input terminal and output end, first input end to receive the input clock letter
Number, the second input terminal receives the carry signal, and the compensation circuit believes the carry based on the input clock signal
Number pulse width compensate and output end provide duty ratio be 50% thermal compensation signal；And
Selection circuit has selection end, first input end, the second input terminal and output end, end is selected to receive the frequency dividing ratio
The lowest order of signal, first input end receive the carry signal, and the second input terminal receives the thermal compensation signal, selects it
One provides the fractional frequency signal in its output end.
9. high-speed frequency divider according to claim 5, which is characterized in that the adjusting circuit includes：
There is first phase inverter input terminal and output end, input terminal to receive frequency dividing ratio signal lowest order；
First and door, there is first input end, the second input terminal and output end, first input end to be coupled to the defeated of add circuit
For outlet to receive carry signal, the second input terminal is coupled to the output end of phase inverter to receive anti-reflection signal；
Second and door, there is first input end, the second input terminal and output end, it is minimum that first input end receives frequency dividing ratio signal
Position, the second input terminal are coupled to add circuit output end to receive carry signal；
There is second phase inverter input terminal and output end, input terminal to receive input clock signal；
There is d type flip flop first input end, the second input terminal and output end, first input end to be coupled to the output of second and door
End, the second input terminal are coupled to the output end of the second phase inverter；
First or door, there is first input end, the second input terminal and output end, first input end to be coupled to the output of first and door
End, the second input terminal are coupled to the output end of d type flip flop；And
Second or door, there is first input end, the second input terminal and output end, first input end to be coupled to the output of first or door
End, the second input terminal are coupled to the output end of add circuit to receive carry signal, and output end provides the fractional frequency signal.
10. high-speed frequency divider according to claim 1, which is characterized in that the corresponding decimal number of the frequency dividing ratio signal
Word is the divider ratios of the high-speed frequency divider.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201820243607.6U CN207896957U (en) | 2018-02-11 | 2018-02-11 | A kind of high-speed frequency divider |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201820243607.6U CN207896957U (en) | 2018-02-11 | 2018-02-11 | A kind of high-speed frequency divider |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108111163A (en) * | 2018-02-11 | 2018-06-01 | 成都信息工程大学 | A kind of high-speed frequency divider |
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2018
- 2018-02-11 CN CN201820243607.6U patent/CN207896957U/en not_active Withdrawn - After Issue
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108111163A (en) * | 2018-02-11 | 2018-06-01 | 成都信息工程大学 | A kind of high-speed frequency divider |
| CN108111163B (en) * | 2018-02-11 | 2023-08-25 | 深圳市卓越信息技术有限公司 | High-speed frequency divider |
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