CN108664414B - DDR memory configuration space access method and device - Google Patents
DDR memory configuration space access method and device Download PDFInfo
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- CN108664414B CN108664414B CN201710206370.4A CN201710206370A CN108664414B CN 108664414 B CN108664414 B CN 108664414B CN 201710206370 A CN201710206370 A CN 201710206370A CN 108664414 B CN108664414 B CN 108664414B
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Abstract
The application provides a DDR memory configuration space access method and a device, wherein the method is applied to a system board card integrated with a processor and a DDR memory, the processor comprises a memory controller, a DDR configuration register and a 1 st level window configuration register to an Nth level (N is more than or equal to 2 and N is an integer) window configuration register with gradually decreasing priority, and the method comprises the following steps: the base address mapping of the DDR configuration register is obtained through an address mapping function, the DDR configuration register is configured to enable the configuration space access function of the DDR memory, the M-level window configuration register is configured according to the occupation condition of the M-level window configuration register (M is more than or equal to 2 and less than or equal to N, and M is an integer), the configured M-level window configuration register accesses the configuration space of the DDR memory to obtain the state of the DDR memory, the debugging process of the DDR memory is simplified, the problem of the DDR memory is accurately located, and the debugging time is shortened.
Description
Technical Field
The present application relates to the field of computer technologies, and in particular, to a method and an apparatus for accessing a DDR memory configuration space.
Background
With the rapid popularization of processors, the applications of processors as operation cores and control cores of computers in various fields are remarkably increased, and more system boards carrying the processors begin to be oriented to applications. Because the stability of the system board determines the normal operation of the computer on which the system board is installed, the system board needs to be subjected to stability debugging in the production process of the system board so as to ensure the stable operation of the computer.
At present, some processors, such as a Loongson processor, perform Data transmission by integrating a Double Data Rate (DDR) memory, so as to increase the operating speed of a computer configured with the Loongson processor. However, in practical applications, once the Loongson processor is in the operating state, the configuration space of the DDR memory cannot be accessed, the real-time working state of the DDR memory and possible problems cannot be known, that is, the DDR memory cannot be debugged, and accordingly, the debugging difficulty of the system board card is increased.
Disclosure of Invention
The application provides a DDR memory configuration space access method and device, and aims to solve the problems that a DDR memory is difficult to debug and a system board card is difficult to debug.
The DDR memory configuration space access method is applied to a system board card integrated with a processor and a DDR memory, wherein the processor comprises a memory controller, a DDR configuration register and a window configuration register, the window configuration register comprises a 1 st-level window configuration register and an Nth-level window configuration register, the priority of the window configuration register is gradually decreased, N is an integer greater than or equal to 2, and the method comprises the following steps:
acquiring the base address mapping of the DDR configuration register through an address mapping function;
configuring the DDR configuration register according to the base address mapping of the DDR configuration register, and enabling a configuration space access function of the DDR memory;
configuring the Mth-level window configuration register according to the occupation condition of the Mth-level window configuration register, wherein M is an integer which is greater than or equal to 2 and less than or equal to N;
and accessing the configuration space of the DDR memory through the configured M-level window configuration register to acquire the state of the DDR memory.
The application also provides a DDR memory configuration space access device, the device is integrated in a processor including a memory controller, a DDR configuration register and a window configuration register, the processor and the DDR memory are integrated in a system board card, wherein the window configuration register includes a level 1 window configuration register to a level N window configuration register whose priority gradually decreases, N is an integer greater than or equal to 2, the device includes:
the obtaining module is used for obtaining the base address mapping of the DDR configuration register through an address mapping function;
the access configuration module is used for configuring the DDR configuration register according to the base address mapping of the DDR configuration register and enabling the configuration space access function of the DDR memory;
the window configuration module is used for configuring the Mth-level window configuration register according to the occupation situation of the Mth-level window configuration register, wherein M is an integer which is greater than or equal to 2 and less than or equal to N;
and the access module is used for accessing the configuration space of the DDR memory through the configured Mth-level window configuration register so as to acquire the state of the DDR memory.
According to the DDR memory configuration space access method and device, the DDR configuration register is configured to enable the DDR memory configuration space access function, the M-level window configuration register with lower priority in the window configuration register is configured, and then the configured M-level window configuration register can access the DDR memory configuration space to obtain the state of the DDR memory, so that the state of the DDR memory can be obtained in real time, the operation is simple, the DDR memory stability debugging can be rapidly completed, the debugging difficulty of a system board card is correspondingly reduced, the debugging time is shortened, and the problems that the DDR memory configuration space cannot be accessed, the DDR memory debugging process is difficult, and the debugging difficulty of the system board card is large are solved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to these drawings without inventive exercise.
Fig. 1 is a schematic flowchart of a DDR memory configuration space access method according to a first embodiment of the present disclosure;
fig. 2 is a schematic flowchart of a second embodiment of a DDR memory configuration space access method provided in the present application;
fig. 3 is a schematic flowchart of a third embodiment of a DDR memory configuration space access method provided in the present application;
fig. 4 is a schematic structural diagram of a first embodiment of a DDR memory configuration space access device provided in the present application;
fig. 5 is a schematic structural diagram of a second embodiment of a DDR memory configuration space access device provided in the present application;
fig. 6 is a schematic structural diagram of a third embodiment of a DDR memory configuration space access device provided in the present application.
Detailed Description
The DDR memory configuration space access method and device provided by the embodiment of the application are mainly suitable for a system board card integrated with a processor and a DDR memory, the processor comprises a memory controller, a DDR configuration register and a window configuration register, the window configuration register comprises a 1 st-level window configuration register to an Nth-level window configuration register with gradually decreasing priority, and the M-level window configuration register is reconfigured to solve the problems that the DDR memory cannot be debugged due to the fact that the DDR memory cannot be accessed in the configuration space, and the system board card is difficult to debug.
In view of the fact that the window configuration register of the Loongson processor has a multi-level window design, the DDR memory configuration space access method is applied to the Loongson processor including the N-level window configuration register for explanation, where N is an integer greater than or equal to 2.
In this embodiment, the window configuration register of the Loongson processor includes: level 1 window configuration registers to level N window configuration registers of decreasing priority. That is, the Loongson processor may adopt a multi-stage crossbar structure, and the multi-stage crossbar windows may be configured separately for controlling the specific address to be sent to the specific receiving end for processing.
The level of the 1 st-level window configuration register (i.e. the 1 st-level crossbar switch) is higher than that of the M th-level window configuration register (i.e. the M-level crossbar switch, where M is an integer greater than or equal to 2 and less than or equal to N), and the configuration is important for the whole processor, and divides the basic framework of the CPU, and this setting is not displayed by the address window configuration register, so as to avoid the problem of access error during subsequent operations, the configuration of the 1 st-level window configuration register generally cannot be modified at will.
Compared with the 1 st-level window configuration register, the limitation condition of the address window configuration of the M-level window configuration register (namely, an M-level cross switch) is relatively weak, and software is mainly used for ensuring that no error occurs in the access content after the address window is reconfigured. The technical solution of the present application will be described in detail below with reference to specific examples.
It should be noted that the following specific embodiments may be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.
Fig. 1 is a schematic flowchart of a DDR memory configuration space access method according to an embodiment of the present disclosure. The method for accessing the DDR memory configuration space provided by the embodiment is applied to a system board integrated with a processor and a DDR memory, wherein the processor comprises a memory controller, a DDR configuration register and a window configuration register. The window configuration registers comprise a level 1 window configuration register to a level N window configuration register with gradually decreasing priority, wherein N is an integer greater than or equal to 2. As shown in fig. 1, the method for accessing the DDR memory configuration space provided in this embodiment includes the following steps:
step 11: and acquiring the base address mapping of the DDR configuration register through an address mapping function.
In this embodiment, the memory controller is an important component of the internal processor of the computer system for controlling the DDR memory and enabling the DDR memory to exchange data with the processor through the memory controller. Therefore, when the configuration space of the DDR memory needs to be accessed, the memory controller needs to be operated first, that is, a node of the memory controller is opened, so that the processor can operate the DDR configuration register or the window configuration register (actually, the mth-level window configuration register, where M is an integer greater than or equal to 2 and less than or equal to N), thereby achieving the purpose of accessing the configuration space of the DDR memory. Here, the node of the memory controller is a hub between the processor and the DDR memory, and for different system boards, the node of each memory controller may be set to be single or multiple, which may be set according to actual situations, and is not limited herein.
It should be noted that the memory controller determines the maximum memory capacity, the memory bank, the memory type and speed, the memory grain data depth and the data width, and other important parameters that can be used by the computer system, that is, the memory controller determines the memory performance of the computer system, and has a great influence on the overall performance of the computer system.
After the node of the memory controller is opened, the processor can operate the M-level window configuration register in the DDR configuration register and the window configuration register, and the realization possibility is provided for accessing the configuration space of the DDR memory.
Optionally, if the processor wants to access the DDR memory, the DDR configuration register needs to be reasonably configured first, and thus the processor needs to obtain a base address of the DDR configuration register. Because of the memory mapping function mmap, a file or other object can be mapped into memory. In this embodiment, the processor may obtain the base address mapping of the DDR configuration register through the memory mapping function mmap, that is, map the base address of the DDR configuration register to the virtual memory space of the processor by using the memory mapping function mmap to obtain the base address mapping of the DDR configuration register, and configure (read and modify) the DDR configuration register according to the base address mapping, so as to achieve the purpose of enabling the access function of the configuration space of the DDR memory.
Step 12: and configuring the DDR configuration register according to the base address mapping of the DDR configuration register, so that the configuration space access function of the DDR memory is enabled.
Specifically, after the system board is initialized and the DDR memory is configured, the configuration space of the DDR memory may not be accessed, and therefore, if the processor wants to access the configuration space of the DDR memory, the processor needs to reconfigure the DDR configuration register. Optionally, after the base address mapping of the DDR configuration register is obtained, the initial configuration of the DDR configuration register may be read and written or modified according to the base address mapping of the DDR configuration register, so that the processor may access the configuration space of the DDR memory after the DDR configuration register is reconfigured.
Step 13: and configuring the Mth-level window configuration register according to the occupation condition of the Mth-level window configuration register.
Wherein M is an integer greater than or equal to 2 and less than or equal to N.
After the system board card is initialized and configured, each window configuration register (including the 1 st-nth window configuration registers) is also configured correspondingly, and different window configuration registers correspond to different addresses. Therefore, if the DDR memory is to be accessed through the mth window configuration register, the occupation situation of the mth window configuration register needs to be known first, and the mth window configuration register is configured accordingly according to the occupation situation of the mth window configuration register.
Specifically, the processor may check the configuration condition of the mth window configuration register by scanning the mth window configuration register, and add an address of the DDR memory to the empty mth window configuration register with a lower priority or modify a window address of the mth window configuration register with a higher priority to an address of the DDR memory according to the occupation condition of the mth window configuration register.
It should be noted that the mth-level window configuration register described in this embodiment actually refers to a multi-level crossbar switch address window configuration register, and the processor adopts a multi-level crossbar switch structure and can access different addresses by configuring the multi-level crossbar switch window.
It should be noted that, when the processor is added with a crossbar structure, the system redundancy time will be increased, and the processing speed of the processor will be reduced, so the number of window configuration register stages included in the window configuration register will affect the processing capability of the processor, and therefore, selecting an appropriate mth window configuration register can achieve the function of accessing the DDR memory space without greatly affecting the processing speed of the processor.
Step 14: and accessing the configuration space of the DDR memory through the configured M-level window configuration register to acquire the state of the DDR memory.
After the DDR configuration register is reconfigured in the above steps 11 and 12, the configuration space of the DDR memory can be accessed, and after the mth window configuration register is configured in step 13, the processor can access the address corresponding to the DDR memory, so that even when the system board card corresponds to the computer in the running process, the processor can access the configuration space of the DDR memory through the configured mth window configuration register, and further determine the real-time state of the DDR memory according to the parameter information (for example, statistical information of error checking and correcting) in the DDR memory, thereby correspondingly implementing the debugging of the DDR memory.
It should be noted that the DDR memory configuration space access method provided in this embodiment does not limit the configuration order of the DDR configuration register and the mth window configuration register, and in another embodiment of the present application, the processor may also configure the mth window configuration register according to the occupation condition of the mth window configuration register, and then configure the DDR configuration register to enable the DDR memory configuration space access function. That is, step 13 may be executed before step 11, or simultaneously with step 11, and the order is not limited as long as the DDR configuration register and the mth window configuration register are configured separately.
According to the DDR memory configuration space access method provided by the embodiment of the application, the DDR configuration register is configured according to the base address mapping of the DDR configuration register obtained through an address mapping function, the DDR memory configuration space access function is enabled, the M-level window configuration register is configured according to the occupation condition of the M-level window configuration register, and the configured M-level window configuration register accesses the DDR memory configuration space to obtain the state of the DDR memory.
As an example, on the basis of the embodiment described in fig. 1, fig. 2 is a schematic flowchart of a second embodiment of a DDR memory configuration space access method provided in the present application. As shown in fig. 2, in this embodiment, when both N and M are 2, that is, when the window configuration registers include a level 1 window configuration register and a level 2 window configuration register with decreasing priorities, step 13 (configuring the level M window configuration register according to the occupation situation of the level M window configuration register) may be implemented in the following feasible manner.
Step 21: and scanning the 2 nd-level window configuration register to acquire the occupation condition of the 2 nd-level window configuration register.
In practical application, considering the processing capability of the integrated processor, the window configuration register in this embodiment may be a window configuration register including a level 1 window configuration register and a level 2 window configuration register, so in this embodiment, the processor needs to access the configuration space of the DDR memory through the level 2 window configuration register, but after the system board card is initially configured, the window address of each level 2 window configuration register corresponds to a different address, so that the occupation condition of the level 2 window configuration register needs to be obtained first, and the level 2 window configuration register is processed correspondingly according to the occupation condition of the level 2 window configuration register.
Step 22: and judging whether an unoccupied first window configuration register exists in the 2 nd-level window configuration register according to the occupation condition of the 2 nd-level window configuration register, if so, executing the step 23, and if not, executing the step 24 and the step 25.
In this embodiment, the first window configuration register refers to a register corresponding to the level 2 window configuration, that is, a window configuration register with a relatively low priority level. In order to reduce the influence of the reconfiguration window configuration register on the functions of the processor, whether the unoccupied first window configuration register exists in the 2 nd-level window configuration register is checked, and the first window configuration register or other window configuration registers are operated according to the checked result.
Step 23: and adding the address of the DDR memory on the unoccupied first window configuration register.
As an example, when there is an unoccupied first window configuration register in the level 2 window configuration register, an address of the DDR memory may be directly added to the unoccupied first window configuration register, so that the DDR memory and the level 2 window configuration register may be associated without affecting initial performance of other window configuration registers.
Step 24: a modifiable second window configuration register in the level 2 window configuration register is looked up.
The second window configuration register can be modified to be a second window configuration register which is higher in priority than the first window configuration register in the level 2 window configuration register and is contained by the first window configuration register.
As another example, when all the first window configuration registers in the level 2 window configuration registers are occupied, the addresses of the DDR memory cannot be directly added to the first window configuration registers. At this time, the processor searches a modifiable second window configuration register in a second window configuration register with a higher priority level than the first window configuration register, and then modifies the modifiable second window configuration register appropriately to associate the DDR memory with the window configuration register.
Optionally, the modifiable second window configuration register is a second window configuration register that is at the same level as the first window configuration register but has a higher priority than the first window configuration register, and the modifiable second window configuration register is included in the first window configuration register, which means that the window address range of the modifiable second window configuration register is smaller than the window address range of the first window configuration register.
Step 25: and modifying the window address of the modifiable second window configuration register into the address of the DDR memory.
And when the processor determines that the second window configuration register can be modified, modifying the window address of the second window configuration register into the address of the DDR memory, and associating the DDR memory with the level 2 window configuration register so as to achieve the purpose that the processor accesses the configuration space of the DDR memory.
The DDR memory configuration space access method provided in this embodiment obtains the occupation status of the 2 nd window configuration register by scanning the 2 nd window configuration register, and further when there is an unoccupied first window configuration register in the level 2 window configuration register, adding the address of DDR memory on the unoccupied first window configuration register, when all the first window configuration registers in the level 2 window configuration register are occupied, by searching the modifiable second window configuration register in the 2 nd-level window configuration register and modifying the window address of the modifiable second window configuration register into the address of the DDR memory, therefore, the DDR memory and the 2 nd level window configuration register can be associated, and a foundation is laid for the processor to access the configuration space of the DDR memory through the configured 2 nd level window configuration register so as to obtain the state of the DDR memory.
Optionally, on the basis of the method for accessing the DDR memory configuration space provided in the embodiment shown in fig. 1 or fig. 2, the step 14 (accessing the DDR memory configuration space through the configured mth window configuration register to obtain the status of the DDR memory) may be implemented by the steps in the embodiment shown in fig. 3.
Fig. 3 is a flowchart illustrating a third embodiment of a method for accessing a DDR memory configuration space provided in the present application. As shown in fig. 3, in this embodiment, the step 14 (accessing the configuration space of the DDR memory through the configured mth window configuration register to obtain the status of the DDR memory) includes the following steps:
step 31: and acquiring the address mapping of the DDR memory by using an address mapping function.
In this embodiment, after adding the address of the DDR memory to the first unoccupied window configuration register or modifying the window address of the second modifiable window configuration register to the address of the DDR memory, the address of the DDR memory is associated with the mth window configuration register, and in order to enable the processor to access the DDR memory, the address mapping of the DDR memory may be obtained by using an address mapping function, so that the processor can access the DDR memory by using the address mapping method.
Step 32: and accessing the configuration space of the DDR memory through the address mapping to acquire the state of the DDR memory.
The processor is used for accessing the configuration space of the DDR memory according to the address mapping of the DDR memory, so that the state of the DDR memory can be determined according to the state information of each functional parameter in the DDR memory by setting certain functions in the DDR memory, and the debugging of the DDR memory is further realized.
As an example, when the configuration space of the DDR memory is accessed through the address mapping to obtain the state of the DDR memory, the configuration information of the configuration space of the DDR memory may be obtained according to the address mapping, that is, the processor may first access the configuration space of the DDR memory according to the address mapping to obtain the configuration information of the configuration space, and further determine the configuration function in the DDR memory; secondly, when the error checking function is configured in the DDR memory, the processor may obtain statistical information of the error checking function in the DDR memory according to the obtained configuration information, where the statistical information may include: counting information of error checking errors, wherein the statistical information can comprise parameter information such as error positions, error numbers and the like; and finally, the processor can determine the state of the DDR memory according to the statistical information of the error checking function, namely, the stability of the DDR memory is judged according to the error position and the error number of the error checking function, so that the stability information of the DDR memory is determined according to the judgment result, and the stability debugging of the DDR memory is further realized.
It should be noted that other functional parameters may be added to the DDR memory to reflect the status of the DDR memory, which is not limited in this embodiment, and only the functional parameters capable of reflecting the stability of the DDR memory may be configured, and all of them belong to the protection scope of the present application.
The DDR memory configuration space access method provided by this embodiment obtains the address mapping of the DDR memory by using the address mapping function, and then accesses the DDR memory configuration space through the address mapping to obtain the state of the DDR memory, which does not affect the implementation of each function in the DDR memory, and has the advantages of easy implementation manner, simple operation, and capability of quickly completing the stability debugging of the DDR memory.
Further, on the basis of the foregoing embodiments, after the processor determines the stability of the DDR memory according to the obtained state of the DDR memory, that is, after accessing the configuration space of the DDR memory through address mapping to obtain the state of the DDR memory, the DDR memory configuration space access method provided in the embodiment of the present application further performs the following steps:
and releasing the base address mapping of the DDR configuration register and the address mapping of the DDR memory, which are obtained through the address mapping function, and recovering the initial configuration of the DDR configuration register and the M-level window configuration register.
Specifically, when accessing the configuration space of the DDR memory, it can be known from step 11 in the embodiment shown in fig. 1 that the processor obtains the base address mapping of the DDR configuration register through the address mapping function, at this time, the processor can configure the DDR configuration register according to the base address mapping of the DDR configuration register, so as to enable the configuration space access function of the DDR memory, and it can be known from step 32 in the embodiment shown in fig. 3 that the address mapping function can be used to obtain the address mapping of the DDR memory, and the configuration space of the DDR memory is accessed through the address mapping, so as to achieve the purpose of obtaining the state of the DDR memory. However, after the state of the DDR memory is obtained to implement the debugging of the DDR memory, in order not to affect the initial function configuration of the processor and the DDR memory, both the base address mapping of the DDR configuration register obtained by the address mapping function and the address mapping of the DDR memory are released, so that the configuration of the DDR configuration register and the M-th window configuration register is restored to the initial configuration, and the function before accessing the DDR memory is restored.
The following are embodiments of the apparatus of the present application that may be used to perform embodiments of the method of the present application. For details which are not disclosed in the embodiments of the apparatus of the present application, reference is made to the embodiments of the method of the present application.
Fig. 4 is a schematic structural diagram of a first embodiment of a DDR memory configuration space access device provided in the present application. The DDR memory configuration space access device provided in the embodiment of the present application is integrated in a processor including a memory controller, a DDR configuration register, and a window configuration register, where the processor and the DDR memory are integrated in a system board card, the window configuration register includes a level 1 window configuration register to a level N window configuration register whose priorities are gradually decreased, and N is an integer greater than or equal to 2. As shown in fig. 4, in the present embodiment, the apparatus includes:
an obtaining module 41, configured to obtain, through an address mapping function, a base address mapping of the DDR configuration register.
The access configuration module 42 is configured to configure the DDR configuration register according to the base address mapping of the DDR configuration register acquired by the acquisition module 41, so as to enable a configuration space access function of the DDR memory.
A window configuration module 43, configured to configure the mth-level window configuration register according to an occupation situation of the mth-level window configuration register, where M is an integer greater than or equal to 2 and less than or equal to N.
The accessing module 44 is configured to access the configuration space of the DDR memory through the configured mth window configuration register to obtain the state of the DDR memory.
The DDR memory configuration space access device provided in the embodiment of the present application may be used to execute the technical solution of the method embodiment shown in fig. 1, and the implementation principle and the technical effect are similar, which are not described herein again.
Optionally, on the basis of the foregoing embodiment, fig. 5 is a schematic structural diagram of a second embodiment of the DDR memory configuration space access device provided in the present application. As shown in fig. 5, in the DDR memory configuration space access device according to the embodiment of the present invention, when the reference voltage N, M is 2, the window configuration module 43 includes: an address adding unit 51, a lookup unit 52 and an address modification unit 53.
The address adding unit 51 is configured to add an address of the DDR memory to the unoccupied first window configuration register when the unoccupied first window configuration register exists in the level 2 window configuration register.
The searching unit 52 is configured to search the modifiable second window configuration register in the level 2 window configuration register when all the first window configuration registers in the level 2 window configuration register are occupied.
Wherein, the modifiable second window configuration register is a second window configuration register which has higher priority than the first window configuration register in the level 2 window configuration register and is contained by the first window configuration register.
The address modification unit 53 is configured to modify the window address of the modifiable second window configuration register to the address of the DDR memory.
The DDR memory configuration space access device provided in the embodiment of the present application may be used to execute the technical solution of the method embodiment shown in fig. 2, and the implementation principle and the technical effect are similar, which are not described herein again.
Further, on the basis of the embodiment in fig. 4 or fig. 5, fig. 6 is a schematic structural diagram of a third embodiment of the DDR memory configuration space access device provided in the present application. As shown in fig. 6, in the DDR memory configuration space access device provided in the embodiment of the present application, the access module 44 includes: an address map obtaining unit 61 and a memory state obtaining unit 62.
The address mapping obtaining unit 61 is configured to obtain the address mapping of the DDR memory by using the address mapping function.
The memory status obtaining unit 62 is configured to access the configuration space of the DDR memory through the address mapping to obtain the status of the DDR memory.
Optionally, the memory state obtaining unit 62 is specifically configured to obtain configuration information of a configuration space of the DDR memory according to the address mapping, and obtain statistical information of an error checking function in the DDR memory according to the configuration information, where the statistical information includes: and checking error counting information by errors, and determining the state of the DDR memory according to the statistical information of the error checking function.
The DDR memory configuration space access device provided in the embodiment of the present application may be used to execute the technical solution of the method embodiment shown in fig. 3, and the implementation principle and the technical effect are similar, which are not described herein again.
Further, on the basis of the foregoing embodiment, the DDR memory configuration space access device provided in the present application further includes: and releasing the module.
The release module is configured to release the base address mapping of the DDR configuration register and the address mapping of the DDR memory, which are obtained by the address mapping function, after the memory state obtaining unit accesses the configuration space of the DDR memory through the address mapping to obtain the state of the DDR memory, and recover the initial configuration of the DDR configuration register and the M-th window configuration register.
According to the DDR memory configuration space access method and device, the DDR configuration register is configured, the DDR memory configuration space access function is enabled, the M-level window configuration register is configured, and then the DDR memory configuration space can be accessed through the configured M-level window configuration register to obtain the state of the DDR memory, so that the state of the DDR memory can be obtained in real time, the operation is simple, the DDR memory stability debugging can be rapidly completed, the debugging difficulty of a system board card is correspondingly reduced, and the debugging time is shortened.
Those of ordinary skill in the art will understand that: all or a portion of the steps of implementing the above-described method embodiments may be performed by hardware associated with program instructions. The program may be stored in a computer-readable storage medium. When executed, the program performs steps comprising the method embodiments described above; and the aforementioned storage medium includes: various media that can store program codes, such as ROM, RAM, magnetic or optical disks.
Finally, it should be noted that: the above embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present application.
Claims (10)
1. A DDR memory configuration space access method is applied to a system board card integrated with a processor and a DDR memory, the processor comprises a memory controller, a DDR configuration register and a window configuration register, wherein the window configuration register comprises a 1 st level window configuration register to an Nth level window configuration register with gradually decreasing priority, N is an integer greater than or equal to 2, and the method comprises the following steps:
acquiring the base address mapping of the DDR configuration register through an address mapping function;
configuring the DDR configuration register according to the base address mapping of the DDR configuration register, and enabling a configuration space access function of the DDR memory;
configuring an Mth-level window configuration register according to the occupation condition of the Mth-level window configuration register, wherein M is an integer which is greater than or equal to 2 and less than or equal to N;
and accessing the configuration space of the DDR memory through the configured M-level window configuration register to acquire the state of the DDR memory.
2. The method according to claim 1, wherein when both N and M are 2, configuring the mth-level window configuration register according to an occupation status of the mth-level window configuration register comprises:
when an unoccupied first window configuration register exists in the M-level window configuration register, adding the address of the DDR memory to the unoccupied first window configuration register;
when all first window configuration registers in the Mth-level window configuration register are occupied, searching a modifiable second window configuration register in the Mth-level window configuration register, wherein the modifiable second window configuration register is a second window configuration register which is higher in priority than the first window configuration register in the Mth-level window configuration register and is contained by the first window configuration register;
and modifying the window address of the modifiable second window configuration register into the address of the DDR memory.
3. The method according to claim 1 or 2, wherein the accessing the configuration space of the DDR memory through the configured mth window configuration register to obtain the status of the DDR memory comprises:
acquiring the address mapping of the DDR internal memory by using the address mapping function;
and accessing the configuration space of the DDR memory through the address mapping to acquire the state of the DDR memory.
4. The method of claim 3, wherein the accessing the configuration space of the DDR memory through the address mapping to obtain the status of the DDR memory comprises:
acquiring configuration information of a configuration space of the DDR memory according to the address mapping;
acquiring statistical information of an error checking function in the DDR memory according to the configuration information, wherein the statistical information comprises: error checking erroneous count information;
and determining the state of the DDR memory according to the statistical information of the error checking function.
5. The method as claimed in claim 3, wherein after the accessing the configuration space of the DDR memory through the address mapping to obtain the status of the DDR memory, the method further comprises:
releasing the base address mapping of the DDR configuration register and the address mapping of the DDR memory, which are obtained through the address mapping function;
and restoring the initial configuration of the DDR configuration register and the Mth-level window configuration register.
6. A DDR memory configuration space access device is integrated in a processor comprising a memory controller, a DDR configuration register and a window configuration register, wherein the processor and the DDR memory are integrated in a system board card, the window configuration register comprises a level 1 window configuration register to a level N window configuration register with gradually decreasing priority, and N is an integer greater than or equal to 2, the device comprises:
the obtaining module is used for obtaining the base address mapping of the DDR configuration register through an address mapping function;
the access configuration module is used for configuring the DDR configuration register according to the base address mapping of the DDR configuration register and enabling the configuration space access function of the DDR memory;
the window configuration module is used for configuring an Mth-level window configuration register according to the occupation situation of the Mth-level window configuration register, wherein M is an integer which is greater than or equal to 2 and less than or equal to N;
and the access module is used for accessing the configuration space of the DDR memory through the configured Mth-level window configuration register so as to acquire the state of the DDR memory.
7. The apparatus of claim 6, wherein when both N and M are 2, the window configuration module comprises: the device comprises an address adding unit, a searching unit and an address modifying unit;
the address adding unit is configured to add an address of the DDR memory to the unoccupied first window configuration register when the unoccupied first window configuration register exists in the mth window configuration register;
the searching unit is configured to search a modifiable second window configuration register in the mth-level window configuration register when all first window configuration registers in the mth-level window configuration register are occupied, where the modifiable second window configuration register is a second window configuration register which is higher in priority than the first window configuration register and is included in the first window configuration register in the mth-level window configuration register;
and the address modification unit is used for modifying the window address of the modifiable second window configuration register into the address of the DDR memory.
8. The apparatus of claim 6 or 7, wherein the access module comprises: an address mapping obtaining unit and a memory state obtaining unit;
the address mapping obtaining unit is configured to obtain an address mapping of the DDR memory by using the address mapping function;
the memory state obtaining unit is configured to access the configuration space of the DDR memory through the address mapping to obtain the state of the DDR memory.
9. The apparatus according to claim 8, wherein the memory status obtaining unit is specifically configured to obtain configuration information of a configuration space of the DDR memory according to the address mapping, and obtain statistical information of an error checking function in the DDR memory according to the configuration information, where the statistical information includes: and checking error counting information by errors, and determining the state of the DDR memory according to the statistical information of the error checking function.
10. The apparatus of claim 8, further comprising: a release module;
the release module is configured to release the base address mapping of the DDR configuration register and the address mapping of the DDR memory, which are obtained by the address mapping function, after the memory state obtaining unit accesses the configuration space of the DDR memory through the address mapping to obtain the state of the DDR memory, and recover the initial configuration of the DDR configuration register and the M-th window configuration register.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101256472A (en) * | 2007-03-01 | 2008-09-03 | 国际商业机器公司 | System, equipment and method for switching command of memory and processor of interface connection |
| CN102609040A (en) * | 2012-01-12 | 2012-07-25 | 北京国基科技股份有限公司 | Home-made computer to be reinforced and safety BIOS (basic input output system) operating method for same |
| CN102789384A (en) * | 2012-07-12 | 2012-11-21 | 北京航空航天大学 | Method for implementing server operating system applied to Loongson 3B processor |
| CN106339258A (en) * | 2016-08-10 | 2017-01-18 | 西安诺瓦电子科技有限公司 | Management method and device for shared memory of programmable logic device and microprocessor |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090251867A1 (en) * | 2007-10-09 | 2009-10-08 | Sharma Viswa N | Reconfigurable, modularized fpga-based amc module |
-
2017
- 2017-03-31 CN CN201710206370.4A patent/CN108664414B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101256472A (en) * | 2007-03-01 | 2008-09-03 | 国际商业机器公司 | System, equipment and method for switching command of memory and processor of interface connection |
| CN102609040A (en) * | 2012-01-12 | 2012-07-25 | 北京国基科技股份有限公司 | Home-made computer to be reinforced and safety BIOS (basic input output system) operating method for same |
| CN102789384A (en) * | 2012-07-12 | 2012-11-21 | 北京航空航天大学 | Method for implementing server operating system applied to Loongson 3B processor |
| CN106339258A (en) * | 2016-08-10 | 2017-01-18 | 西安诺瓦电子科技有限公司 | Management method and device for shared memory of programmable logic device and microprocessor |
Non-Patent Citations (1)
| Title |
|---|
| 基于3G网络的嵌入式远程视频监控系统的设计与实现;林杉;《中国优秀硕士学位论文全文数据库》;20160315;全文 * |
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