CN110941395A - Dynamic random access memory, memory management method, system and storage medium - Google Patents
Dynamic random access memory, memory management method, system and storage medium Download PDFInfo
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0658—Controller construction arrangements
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
- G06F9/321—Program or instruction counter, e.g. incrementing
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention provides a dynamic random access memory, a memory management method, a system and a storage medium, wherein the dynamic random access memory comprises a circuit substrate, a DRAM chip set, a memory controller, a first interface and a second interface, wherein the DRAM chip set, the memory controller, the first interface and the second interface are integrated on the circuit substrate; the memory controller is respectively connected with the DRAM chip set and the first interface and responds to the read-write request of the central processing unit connected to the first interface; and the memory controller is connected with the second interface, and when the instruction set read by the central processing unit in the DRAM chipset meets a preset condition, acquires a subsequent instruction set of the instruction set in the DRAM chipset from a mass storage device through the second interface, and stores the subsequent instruction set in the DRAM chipset. The invention can enable the central processing unit to be in a high-efficiency operation state all the time, is suitable for the fields of cloud computing and the like, and can greatly improve the operation efficiency of the system.
Description
Technical Field
The present invention relates to the field of computers, and more particularly, to a dynamic random access memory, a memory management method, a system and a storage medium.
Background
At present, the technology of DRAM (Dynamic Random Access Memory) has been greatly developed, and various types of SDRAM (synchronous Dynamic Random Access Memory), Double Data Rate (DDR) SDRAM, double data rate generation 2 (DDR2) SDRAM, double data rate generation 3 (DDR3) SDRAM, and double data rate generation 4 (DDR4) SDRAM are mainly used. For the DRAM of the above type, a memory controller and a DRAM chip (i.e., a memory granule) are generally used, and a Central Processing Unit (CPU) sends control commands including clock signals, command control signals, address signals and the like to the DRAM chip via the memory controller, and controls the read/write operations of data signals to the DRAM chip through the control commands.
When the computer system executes the program, the relevant program and data executed by the CPU need to be put into the DRAM, when the program is executed, the CPU fetches an instruction from the DRAM according to the content of the current program pointer register and executes the instruction, then fetches the next instruction and executes the next instruction, and the execution is not stopped until the program finishes the instruction. The working process is the process of continuously fetching and executing the instruction, and finally, the calculated result is put into the memory address appointed by the instruction.
However, since the cost of the DRAM is high and the storage capacity of the DRAM is limited, most programs are stored in a mass storage device with relatively low cost, such as a hard disk, a solid state disk, and the like, and when the computer runs, the CPU needs to move data in the mass storage device to the DRAM and write data of the DRAM into the mass storage device. Moreover, the interaction speed between the mass storage device and the central processing unit is much lower than that between the central processing unit and the DRAM, so that the overall operation efficiency of the computer system is greatly influenced.
Disclosure of Invention
The present invention provides a dynamic random access memory, a memory management method, a system and a storage medium, aiming at the problem that the operating efficiency is affected by the interaction speed between a central processing unit and a mass storage device in the computer system.
The present invention provides a dynamic random access memory, which comprises a circuit substrate, a DRAM chip set integrated on the circuit substrate, a memory controller, a first interface for connecting a central processing unit, and a second interface for connecting a mass storage device; the memory controller is respectively connected with the DRAM chip set and the first interface, responds to the read-write request of the central processing unit connected to the first interface, acquires an instruction set from the DRAM chip set, is connected to the central processing unit through first interface data and writes execution result data of the central processing unit into the DRAM chip set;
and the memory controller is connected with the second interface, and when the instruction set read by the central processing unit in the DRAM chipset meets a preset condition, acquires a subsequent instruction set of the instruction set in the DRAM chipset from a mass storage device through the second interface, and stores the subsequent instruction set in the DRAM chipset.
Preferably, the DRAM chipset includes at least two logic storage areas that are a main mapping area and a standby mapping area for each other, and the logic storage area where the instruction set currently read by the central processing unit is located is the main mapping area, and the other logic storage areas are the standby mapping areas;
the preset conditions are as follows: the number of the instruction sets waiting to be read in the main mapping area is smaller than a preset value, or the time for the instruction sets waiting to be read in the main mapping area to be executed in the central processing unit is smaller than a preset time.
Preferably, the memory controller stores a subsequent instruction set of the instruction set in the main mapping area acquired from a mass storage device through the second interface to a standby mapping area when the instruction set read by the central processing unit in the DRAM chipset meets a preset condition;
the at least two logic memory areas switch the main mapping area and the standby mapping area according to the program address appointed by the program counter in the central processing unit.
Preferably, the sizes of the two logical storage areas are equal, and the size of the subsequent instruction set acquired by the memory controller is equal to that of the logical storage area;
before storing a subsequent instruction set of the instruction set in the main mapping area to a spare mapping area, the memory controller writes the contents of the spare mapping area back to the original address of the mass storage device if the contents of the spare mapping area are updated.
Preferably, the first interface is a DRAM interface, the second interface is a PCIE interface, and the mass storage device is connected to the second interface through a PCIE bus.
Preferably, the mass storage device is constituted by a mass flash memory chip integrated onto the circuit substrate, and the mass flash memory chip is connected to the memory controller through the second interface.
An embodiment of the present invention further provides a memory management method, where the memory includes a DRAM chipset, and the memory is connected to a central processing unit through a first interface and connected to a mass storage device through a second interface, and the method includes:
sending the instruction set stored in the DRAM chipset to the central processing unit for execution through the first interface data connection and writing the execution result data of the central processing unit into the DRAM chipset in response to the request of the central processing unit;
when the instruction set read by the central processing unit in the DRAM chipset meets a preset condition, acquiring a subsequent instruction set of the instruction set in the DRAM chipset from a mass storage device through the second interface, and storing the subsequent instruction set to the DRAM chipset.
Preferably, the DRAM chipset includes at least two logic storage areas that are a main mapping area and a standby mapping area for each other, and the logic storage area where the instruction set currently sent to the central processing unit is located is the main mapping area, and the other logic storage areas are the standby mapping areas, and the main mapping area and the standby mapping area are switched by the at least two logic storage areas according to a program address specified by a program counter in the central processing unit;
the preset conditions are as follows: the number of instruction sets waiting to be read in the main mapping area is smaller than a preset value, or the time for the instruction sets waiting to be read in the main mapping area to be executed in the central processing unit is smaller than preset time;
the retrieving, from mass storage via the second interface, a subsequent instruction set of the instruction sets in the DRAM chipset and storing the subsequent instruction set to the DRAM chipset, comprising:
obtaining a subsequent instruction set of the instruction set in the primary mapping area from a mass storage device through the second interface and storing the subsequent instruction set to a standby mapping area;
before storing a subsequent instruction set of the instruction set in the main mapping area to a standby mapping area, if the content of the standby mapping area is updated, writing the content in the standby mapping area back to the original address of the mass storage device.
The invention also provides a computer system, which comprises a central processing unit and a dynamic random access memory, wherein the dynamic random access memory comprises a circuit substrate, a DRAM chip set integrated on the circuit substrate, a memory controller, a first interface used for connecting the central processing unit and a second interface used for connecting a mass storage device, the memory controller comprises a storage unit, a processing unit and a computer program which is stored in the storage unit and can run on the processing unit, and the steps of the memory management method are realized when the processing unit executes the computer program.
The present invention also provides a computer readable storage medium, storing a computer program which, when executed by a processor, implements the steps of the memory management method as described above.
According to the dynamic random access memory, the memory management method, the system and the storage medium, the memory controller directly updates the content in the DRAM chip set according to the instruction set being executed by the central processing unit, so that the central processing unit does not need to interact with a large-capacity storage device, the central processing unit can be always in a high-efficiency running state, the dynamic random access memory, the memory management system and the storage medium are suitable for the fields of cloud computing and the like, and the running efficiency of the system can be greatly improved.
Drawings
FIG. 1 is a diagram of a DRAM according to an embodiment of the present invention;
FIG. 2 is a diagram of the interaction of the DRAM with the CPU and the mass storage device according to the present invention;
fig. 3 is a flowchart illustrating a memory management method according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Fig. 1 is a schematic diagram of a dynamic random access memory according to an embodiment of the present invention, which can be applied to a computer system, such as a cloud server, and is used for temporarily storing programs and data executed by a central processing unit. The DRAM of the present embodiment includes a circuit substrate 10, and a DRAM chipset 11, a memory controller 12, a first interface 13, and a second interface 14 integrated on the circuit substrate 10. The DRAM chipset 11 may specifically include a plurality of DRAM chip particles.
The first interface 13 can be a DRAM interface, and the DRAM can interact with the cpu at high speed through the first interface 13; the second interface 14 may be a PCIE (peripheral component interconnect express) interface, and the dram or the memory controller 12 may be connected to a mass storage device through the second interface 14, where the mass storage device may be an SSD (Solid State Disk) or an HDD (Hard Disk Drive).
In the circuit substrate 10, the memory controller 12 is connected to the DRAM chipset 11 and the first interface 13, respectively, so that the central processing unit connected to the first interface 13 can read the instruction set from the DRAM chipset 11 and write data to the DRAM chipset 11 through the first interface 13 and the memory controller 12 (specifically, the central processing unit can obtain the instruction set from the DRAM chipset 11 according to the program pointer and execute it); the memory controller 12 is connected to the DRAM chipset 11 and the second interface 14, respectively, and implements interaction of the DRAM chipset 11 with data in a mass storage device connected to the second interface 14. Specifically, when the instruction set (i.e. the instruction set not read by the central processing unit, which may include instruction codes and data) in the DRAM chipset 11 waiting for the central processing unit to read meets the preset condition, the memory controller 12 obtains a subsequent instruction set (including instruction codes and data) of the instruction set in the DRAM chipset 11 from the mass storage device through the second interface 14, and stores the subsequent instruction set in the DRAM chipset 11.
The dynamic random access memory directly updates the content in the DRAM chip set 11 according to the instruction set being executed by the central processing unit through the memory controller 12, so that the dynamic random access memory can be automatically updated according to the running state of the central processing unit, the storage capacity of the dynamic random access memory is nearly infinite, the central processing unit does not need to interact with a large-capacity storage device, the central processing unit can be always in a high-efficiency running state, the dynamic random access memory is suitable for the fields with higher requirements on computing resources, such as cloud computing, and the like, and the running efficiency of the system can be greatly improved.
In an embodiment of the present invention, as shown in fig. 2, the DRAM chipset 11 includes two logic storage areas 111 that are a main mapping area and a standby mapping area, where the two logic storage areas 111 are respectively a storage space in the DRAM chipset 11 and respectively store an instruction set for the cpu 20 to process, and the cpu 20 also writes an execution result of the instruction set into the logic storage area 111. The logic memory area 111 where the instruction set currently read by the central processing unit is located is a main mapping area, the other logic memory area 111 is a standby mapping area, and the main mapping area and the standby mapping area can be switched by the two logic memory areas 111 according to a jump instruction (i.e. a jump code in an instruction code) executed by the central processing unit 20. The instruction sets stored in the main mapping area and the standby mapping area are respectively from the mass storage device 30, and the instruction sets stored in the main mapping area and the standby mapping area respectively correspond to a certain section of instruction set in the mass storage device 30, that is, the main mapping area and the standby mapping area correspond to two "windows" of the mass storage device 30, through which the central processing unit 20 can obtain the instruction sets stored in the mass storage device 30. The content shown in the "window" is controlled by the dram memory controller 12.
Specifically, the cpu 20 obtains the instruction set from the main map area through the first interface 13 and the memory controller 12 according to a Program address specified by a Program Counter (Program Counter). Under normal conditions, the original address +1 is automatically used as the program address of the next instruction set after the program counter executes one instruction set, so that the central processing unit 20 acquires the next instruction set from the main mapping area according to the updated program address; if CPU 20 executes the jump instruction, the program counter uses the original address + n or-n as the program address of the next instruction set according to the jump value n, and CPU 20 obtains the next instruction set from the main mapping area according to the updated program address. When the program address specified by the program counter is located in the standby mapping area, the main mapping area and the standby mapping area complete the switch.
Of course, in practical applications, the DRAM chipset 11 may include more logical storage areas 111, and one of the logical storage areas 111 is a main mapping area, and the other logical storage areas 111 are standby mapping areas.
Specifically, the memory controller 12 may update the contents of the DRAM chipset 11 in the following manner: when the number of the instruction sets waiting for the central processing unit to read in the main mapping region is smaller than the preset value, or the time for the instruction sets waiting for reading in the main mapping region to be executed in the central processing unit is smaller than the preset time, the memory controller 12 obtains the subsequent instruction set of the instruction set in the DRAM chipset 11 from the mass storage device through the second interface 14, and stores the subsequent instruction set in the DRAM chipset 11 (meanwhile, the pointer is adjusted according to the instruction set in the main mapping region and the instruction set in the updated standby mapping region, so that the central processing unit can read the instruction sets in sequence). By the method, the instruction set in the dynamic random access memory can be updated in time, so that the instruction execution of the central processing unit is not influenced.
Preferably, the memory controller 12 may store the subsequent instruction set of the instruction set in the main mapping region acquired from the mass storage device 30 through the second interface 14 to the standby mapping region when the instruction set read by the central processing unit 20 in the DRAM chipset 11 meets a preset condition, for example, when the number of the instruction sets read by the central processing unit in the main mapping region is less than a preset value, or the time for the instruction set read by the central processing unit in the main mapping region to be executed in the central processing unit is less than a preset time. Thus, by controlling the preset condition, when the capacity of the logic storage area 111 is small, the efficient operation of the central processing unit 20 is not affected, and the resources of the DRAM chipset 11 are saved.
Specifically, when the instruction set waiting for the central processing unit to read in the DRAM chipset 11 does not include a jump instruction, or the instruction set waiting for the central processing unit to read in the DRAM chipset 11 includes a jump instruction and the instruction set pointed by the jump instruction is still in the DRAM chipset 11, the subsequent instruction set starts with the next instruction of the last instruction in the main mapping area of the DRAM chipset 11; when the instruction set waiting for the cpu to read in the DRAM chipset 11 includes a jump instruction and the instruction set pointed to by the jump instruction is not in the DRAM chipset 11, the subsequent instruction set starts from the instruction pointed to by the jump instruction.
For management, the two logical storage areas 111 may be equal in size (i.e., equal in storage space), and the memory controller 12 may obtain a subsequent instruction set and a logical storage area that are equal in size. By the above manner, the access efficiency of the memory controller 12 can be improved.
Since the central processing unit 20 writes the execution result into the logic storage area 111 when executing the instruction set, before storing the subsequent instruction set of the instruction set in the main mapping area into the standby mapping area, if the content of the standby mapping area is updated (i.e. the central processing unit 20 writes the execution result of the instruction set), the memory controller 12 needs to write the content in the standby mapping area (the result updated by the central processing unit 20) back to the original address of the mass storage device 30. That is, before storing the subsequent instruction set of the instruction set in the main mapping region into the standby mapping region, the memory controller 12 first determines whether the content of the standby mapping region is updated, and if not, directly stores the subsequent instruction set into the standby mapping region, otherwise, writes the content (i.e., the updated content) in the standby mapping region back to the original address of the mass storage device 30, and then stores the subsequent instruction set into the standby mapping region.
In an embodiment of the present invention, the mass storage device may be independent of the dynamic random access memory, and the mass storage device is connected to the second interface 14 through a PCIE bus (when the second interface 14 is a PCIE interface). In addition, the mass storage device may be integrated into a dynamic random access memory, for example, the mass storage device may be formed by a mass flash memory chip integrated onto the circuit substrate 10, and the mass flash memory chip is connected to the memory controller 12 through the second interface 14, in which case the second interface 14 may adopt a PCIE interface or other high speed interface to improve data throughput efficiency.
As shown in fig. 3, an embodiment of the present invention further provides a memory management method, where the memory may be a dynamic random access memory, and the memory includes a DRAM chipset 11, and the memory is connected to the central processing unit through a first interface and connected to the mass storage device through a second interface. The method of the present embodiment may be executed by a memory controller in a memory, and the method includes:
step S31: in response to a request from the central processing unit, the instruction set stored in the DRAM chipset is sent to the central processing unit for execution and the execution data of the central processing unit is written to the DRAM chipset.
The DRAM chip set can comprise two logic storage areas which are a main mapping area and a standby mapping area, wherein the logic storage area where an instruction set sent to the central processing unit is located is the main mapping area, the other logic storage area is the standby mapping area, and the main mapping area and the standby mapping area are switched by the two logic storage areas according to a jump instruction executed by the central processing unit. Of course, in practical applications, the DRAM chipset 11 may include more logical storage areas 111, and one of the logical storage areas 111 is a main mapping area, and the other logical storage areas 111 are standby mapping areas.
The instruction sets stored in the main mapping area and the standby mapping area are respectively from the mass storage device, and the instruction sets stored in the main mapping area and the standby mapping area respectively correspond to a certain section of instruction set in the mass storage device, namely the main mapping area and the standby mapping area are equivalent to two windows of the mass storage device, and the central processing unit can acquire the instruction sets stored in the mass storage device through the two windows. The content shown in the "window" is controlled by the memory controller of the dynamic random access memory.
Step S32: when the instruction set read by the central processing unit in the DRAM chipset meets the preset condition, acquiring a subsequent instruction set of the instruction set in the DRAM chipset from a mass storage device through a second interface, and storing the subsequent instruction set in the DRAM chipset.
The preset conditions may be: the number of the instruction sets waiting to be read in the main mapping area is smaller than a preset value, or the time for the instruction sets waiting to be read in the main mapping area to be executed in the central processing unit is smaller than preset time.
In the above step S32, a subsequent instruction set of the instruction set in the main mapping area may be obtained from the mass storage device through the second interface, and the subsequent instruction set is stored to the standby mapping area. And, before storing the subsequent instruction set of the instruction set in the main mapping area to the standby mapping area, if the contents of the standby mapping area are updated, writing the contents in the standby mapping area back to the original address of the mass storage device.
The memory management method in this embodiment is the same as the dram in the embodiment corresponding to fig. 1, and the specific implementation process is detailed in the embodiment of the dram, and the technical features in the embodiment of the dram are applicable in this embodiment of the method, which is not described herein again.
The present invention also provides a computer system, which includes a central processing unit, a dynamic random access memory, and the dynamic random access memory includes a circuit substrate, and a DRAM chipset integrated on the circuit substrate, a memory controller, a first interface for connecting the central processing unit, and a second interface for connecting a mass storage device, the memory controller includes a storage unit, a processing unit, and a computer program stored in the storage unit and operable on the processing unit, and the processing unit implements the steps of the memory management method as shown in fig. 3 when executing the computer program.
The computer system in this embodiment and the dynamic random access memory in the embodiment corresponding to fig. 1-2 belong to the same concept, and specific implementation processes thereof are detailed in the corresponding method embodiments, and technical features in the method embodiments are correspondingly applicable in this device embodiment, which is not described herein again.
An embodiment of the present invention further provides a computer-readable storage medium, where a computer program is stored on the storage medium, and when the computer program is executed by a processor, the steps of the memory management method are implemented. The computer-readable storage medium in this embodiment and the internal dynamic random access memory in the embodiment corresponding to fig. 1-2 belong to the same concept, and specific implementation processes thereof are detailed in the corresponding method embodiments, and technical features in the method embodiments are correspondingly applicable in this device embodiment, which is not described herein again.
It should be understood that, the sequence numbers of the steps in the foregoing embodiments do not imply an execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.
It is obvious to those skilled in the art that, for convenience and simplicity of description, the foregoing functional units and modules are merely illustrated in terms of division, and in practical applications, the foregoing functions may be distributed as needed by different functional units and modules. Each functional unit and module in the embodiments may be integrated in one processor, or each unit may exist alone physically, or two or more units are integrated in one unit, and the integrated unit may be implemented in a form of hardware, or in a form of software functional unit. In addition, specific names of the functional units and modules are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present application. The specific working processes of the units and modules in the system may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and reference may be made to the related descriptions of other embodiments for parts that are not described or illustrated in a certain embodiment.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
In the embodiments provided in the present application, it should be understood that the disclosed dram, memory management method and computer system may be implemented in other ways. For example, the dynamic random access memory embodiments described above are merely illustrative.
In addition, functional units in the embodiments of the present application may be integrated into one processor, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The integrated modules/units, if implemented in the form of software functional units and sold or used as separate products, may be stored in a computer readable storage medium. Based on such understanding, all or part of the flow in the method of the embodiments described above can be realized by a computer program, which can be stored in a computer-readable storage medium and can realize the steps of the embodiments of the methods described above when the computer program is executed by a processor. Wherein the computer program comprises computer program code, which may be in the form of source code, object code, an executable file or some intermediate form, etc. The computer-readable medium may include: any physical or interface switching device, recording medium, usb disk, removable hard disk, magnetic disk, optical disk, computer Memory, Read-Only Memory (ROM), Random Access Memory (RAM), electrical carrier wave signal, telecommunication signal, software distribution medium, etc., capable of carrying said computer program code. It should be noted that the computer readable medium may contain other components which may be suitably increased or decreased as required by legislation and patent practice in jurisdictions, for example, in some jurisdictions, computer readable media which may not include electrical carrier signals and telecommunications signals in accordance with legislation and patent practice.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.
Claims (10)
1. A dynamic random access memory is characterized by comprising a circuit substrate, a DRAM chip set, a memory controller, a first interface and a second interface, wherein the DRAM chip set is integrated on the circuit substrate; the memory controller is respectively connected with the DRAM chip set and the first interface, responds to the read-write request of the central processing unit connected to the first interface, acquires an instruction set from the DRAM chip set, is connected to the central processing unit through first interface data and writes execution result data of the central processing unit into the DRAM chip set;
and the memory controller is connected with the second interface, and when the instruction set read by the central processing unit in the DRAM chipset meets a preset condition, acquires a subsequent instruction set of the instruction set in the DRAM chipset from a mass storage device through the second interface, and stores the subsequent instruction set in the DRAM chipset.
2. The dynamic random access memory according to claim 1, wherein the DRAM chipset comprises at least two logical storage areas that are a main mapping area and a standby mapping area, and the logical storage area where the instruction set currently read by the central processing unit is located is the main mapping area, and the other logical storage areas are the standby mapping areas;
the preset conditions are as follows: the number of the instruction sets waiting to be read in the main mapping area is smaller than a preset value, or the time for the instruction sets waiting to be read in the main mapping area to be executed in the central processing unit is smaller than a preset time.
3. The DRAM of claim 2, wherein the memory controller stores a subsequent instruction set of the instruction set in the main mapping area retrieved from the mass storage device through the second interface to a standby mapping area when the instruction set read by the cpu in the DRAM chipset meets a predetermined condition;
the at least two logic memory areas switch the main mapping area and the standby mapping area according to the program address appointed by the program counter in the central processing unit.
4. The dynamic random access memory of claim 3, wherein the sizes of the at least two logical storage areas are equal, and the subsequent instruction set fetched by the memory controller is equal to the size of the logical storage area;
before storing a subsequent instruction set of the instruction set in the main mapping area to a spare mapping area, the memory controller writes the contents of the spare mapping area back to the original address of the mass storage device if the contents of the spare mapping area are updated.
5. The dynamic random access memory of claim 1, wherein the first interface is a DRAM interface, the second interface is a PCIE interface, and the mass storage device is connected to the second interface via a PCIE bus.
6. The dram of claim 1, wherein the mass storage device is comprised of a mass flash memory chip integrated onto the circuit substrate, and the mass flash memory chip is connected to the memory controller through the second interface.
7. A method of memory management, said memory comprising a DRAM chipset, and said memory being coupled to a central processing unit via a first interface and to a mass storage device via a second interface, said method comprising:
sending the instruction set stored in the DRAM chipset to the central processing unit for execution through the first interface data connection and writing the execution result data of the central processing unit into the DRAM chipset in response to the request of the central processing unit;
when the instruction set read by the central processing unit in the DRAM chipset meets a preset condition, acquiring a subsequent instruction set of the instruction set in the DRAM chipset from a mass storage device through the second interface, and storing the subsequent instruction set to the DRAM chipset.
8. The memory management method according to claim 7, wherein the DRAM chipset comprises at least two logical storage areas that are a primary mapping area and a standby mapping area, and the logical storage area where the instruction set currently sent to the cpu is located is the primary mapping area, and the other logical storage areas are the standby mapping areas, and the at least two logical storage areas switch the primary mapping area and the standby mapping area according to the program address specified by the program counter in the cpu;
the preset conditions are as follows: the number of instruction sets waiting to be read in the main mapping area is smaller than a preset value, or the time for the instruction sets waiting to be read in the main mapping area to be executed in the central processing unit is smaller than preset time;
the retrieving, from mass storage via the second interface, a subsequent instruction set of the instruction sets in the DRAM chipset and storing the subsequent instruction set to the DRAM chipset, comprising:
obtaining a subsequent instruction set of the instruction set in the primary mapping area from a mass storage device through the second interface and storing the subsequent instruction set to a standby mapping area;
before storing a subsequent instruction set of the instruction set in the main mapping area to a standby mapping area, if the content of the standby mapping area is updated, writing the content in the standby mapping area back to the original address of the mass storage device.
9. A computer system comprising a central processing unit, a dynamic random access memory, and the dynamic random access memory comprises a circuit substrate and a DRAM chipset integrated onto the circuit substrate, a memory controller, a first interface for connecting to the central processing unit and a second interface for connecting to a mass storage device, wherein the memory controller comprises a storage unit, a processing unit and a computer program stored in the storage unit and executable on the processing unit, and the processing unit implements the steps of the memory management method according to any one of claims 7 to 8 when executing the computer program.
10. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the steps of the memory management method according to one of claims 7 to 8.
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