CN108614791B - Serial pulse generating circuit and charging device - Google Patents
Serial pulse generating circuit and charging device Download PDFInfo
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- CN108614791B CN108614791B CN201611130269.7A CN201611130269A CN108614791B CN 108614791 B CN108614791 B CN 108614791B CN 201611130269 A CN201611130269 A CN 201611130269A CN 108614791 B CN108614791 B CN 108614791B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
- G06F13/4072—Drivers or receivers
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
- H02J7/007—Regulation of charging or discharging current or voltage
- H02J7/00711—Regulation of charging or discharging current or voltage with introduction of pulses during the charging process
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
- H02J7/02—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries for charging batteries from ac mains by converters
- H02J7/04—Regulation of charging current or voltage
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Abstract
The invention discloses a serial pulse generating circuit and a charging device, wherein the circuit comprises: the receiving end is used for receiving a request voltage signal output by the equipment to be charged; the parallel conversion module is connected with the receiving end and used for generating N paths of parallel digital signals corresponding to the request voltage signals according to the request voltage signals; and the serial pulse generation module is connected with the parallel conversion module and is used for dividing the frequency of the clock signal according to the state of each path of digital signal to generate a pulse signal corresponding to the pulse width and controlling the pulse signals corresponding to the N paths of parallel digital signals to be sequentially output so as to output the serial pulse signal corresponding to the request voltage signal. Therefore, the serial pulse generating circuit of the embodiment of the invention utilizes the high-precision clock signal to generate the serial pulse signal corresponding to the request voltage signal, improves the time precision of signal output, and effectively reduces the chip area.
Description
Technical Field
The present invention relates to the field of communications technologies, and in particular, to a serial pulse generating circuit and a charging device having the same.
Background
In the related art, the secondary chip of the charging device sends out a corresponding serial pulse sequence combination according to a request voltage signal, and provides the serial pulse sequence combination to the primary chip through the optical coupler, so that the primary chip controls the charging device to output a corresponding request voltage. As shown in fig. 1, the serial pulse generating circuit in the related art charges and discharges a capacitor C1 ' by using current sources I1 ' and I2 ' to generate pulses and frequency cycles with corresponding widths by adjusting the magnitude of the charging and discharging currents.
However, the related art has a disadvantage that the accuracy of the frequency period and the pulse width of the output of the serial pulse generating circuit is low due to the limited accuracy of the capacitor and the current source. Further, if a pulse output of hundreds of us is to be output, the charging and discharging current needs to be set to a small level so as not to increase the area of the capacitor too much, which further reduces the output accuracy.
Therefore, improvements are needed in the related art.
Disclosure of Invention
The present invention is directed to solving, at least to some extent, one of the technical problems in the related art. To this end, an object of the present invention is to provide a serial pulse generating circuit that can improve the accuracy of a serial pulse signal by dividing a high-accuracy clock and performing logic processing.
Another object of the present invention is to provide a charging device.
In order to achieve the above object, an embodiment of the present invention provides a serial pulse generating circuit, including: the receiving end is used for receiving a request voltage signal output by the equipment to be charged; the parallel conversion module is connected with the receiving end and used for generating N paths of parallel digital signals corresponding to the request voltage according to the request voltage signal; and the serial pulse generation module is connected with the parallel conversion module and is used for dividing the frequency of the clock signal according to the state of each path of digital signal to generate a pulse signal corresponding to the pulse width and controlling the pulse signals corresponding to the N paths of parallel digital signals to be sequentially output so as to output the serial pulse signal corresponding to the request voltage signal.
According to the serial pulse generating circuit provided by the embodiment of the invention, the request voltage signal output by the charging equipment is received through the receiving end, the parallel conversion module generates N paths of parallel digital signals corresponding to the request voltage signal according to the request voltage signal, the serial pulse generating module divides the frequency of the clock signal according to the state of each path of digital signal to generate a pulse signal corresponding to the pulse width, and controls the pulse signals corresponding to the N paths of parallel digital signals to be output in sequence, so that the serial pulse signal corresponding to the request voltage signal is output. Therefore, the serial pulse generating circuit of the embodiment of the invention utilizes the high-precision clock signal to generate the serial pulse signal corresponding to the request voltage signal, improves the time precision of signal output, and effectively reduces the chip area.
According to one embodiment of the invention, the serial pulse generating module comprises: a counting unit for counting the number of outputs of the N-path parallel digital signals to generate a count signal; the pulse width control signal generating unit is respectively connected with the counting unit and the parallel conversion module and is used for controlling the N paths of parallel digital signals to be sequentially output according to the counting signal; and the frequency dividing unit is connected with the pulse width control signal generating unit and is used for dividing the frequency of the clock signal according to the state of each path of digital signal so as to generate a pulse signal corresponding to the pulse width.
According to an embodiment of the present invention, the frequency dividing unit includes: a clock signal generator for generating a clock signal; the first frequency divider is connected with the clock signal generator and is used for dividing the frequency of the clock signal to generate a pulse signal with a first pulse width; a second frequency divider for dividing the clock signal to generate a pulse signal of a first pulse width when the first frequency divider is masked and dividing the pulse signal of the first pulse width to generate a pulse signal of a second pulse width when the first frequency divider participates in the frequency division; and the logic control subunit is respectively connected with the pulse width control signal generation unit, the clock signal generator, the first frequency divider and the second frequency divider, and is used for controlling the first frequency divider to participate in frequency division or be shielded according to the state of each path of digital signal.
According to one embodiment of the present invention, the logic control subunit includes: the input end of the NOT gate is connected with the pulse width control signal generating unit; a first input end of the first NAND gate is connected with an output end of the NOT gate, and a second input end of the first NAND gate is connected with the clock signal generator; a first input end of the second nand gate is connected with the pulse width control signal generating unit, and a second input end of the second nand gate is connected with the first frequency divider; and a first input end of the third NAND gate is connected with the output end of the first NAND gate, a second input end of the third NAND gate is connected with the output end of the second NAND gate, and the output end of the third NAND gate is connected with the second frequency divider.
According to a specific embodiment of the present invention, the second pulse width may be an integer multiple of the first pulse width.
According to an embodiment of the present invention, the serial pulse generating module further includes: the first end of the trigger is respectively connected with the counting unit and the counting unit, the second end of the trigger is connected with the frequency dividing unit, the third end of the trigger is used for receiving a trigger signal, and the trigger enables the counting unit and the frequency dividing unit after receiving the trigger signal through the third end.
According to one embodiment of the invention, the parallel conversion module comprises: the judging unit is used for judging the voltage level of the request voltage signal; the decoding unit is connected with the judging unit and is used for generating a voltage state signal according to the voltage level of the request voltage signal; and the parallel coding unit is connected with the decoding unit and is used for generating N paths of parallel digital signals corresponding to the request voltage signals according to the voltage state signals.
According to an embodiment of the present invention, the device to be charged may be a mobile phone or a tablet computer.
In order to achieve the above object, according to another aspect of the present invention, a charging device includes: a secondary chip comprising the serial pulse generation circuit according to any one of claims 1 to 8, the secondary chip being configured to generate a serial pulse signal corresponding to the request voltage signal from the request voltage signal; and the main side chip is used for adjusting the voltage output of the main side chip according to the serial pulse signal.
According to the charging device provided by the embodiment of the invention, the secondary chip generates the serial pulse signal corresponding to the request voltage signal through the serial pulse generating circuit of the embodiment, and further, the primary chip adjusts the voltage output of the primary chip according to the serial pulse signal. Therefore, the charging device provided by the embodiment of the invention utilizes the high-precision clock signal to generate the serial pulse signal corresponding to the request voltage signal, so that the time precision of signal output is improved, and the voltage output is effectively regulated.
According to one embodiment of the invention, the charging device is used for charging a device to be charged, wherein the device to be charged can be a mobile phone or a tablet computer.
Drawings
Fig. 1 is a circuit schematic diagram of a serial pulse generating circuit in the related art;
FIG. 2 is a block schematic diagram of a serial pulse generation circuit according to an embodiment of the present invention;
FIG. 3a is a block schematic diagram of a serial pulse generation circuit according to one embodiment of the present invention;
FIG. 3b is a circuit schematic of a serial pulse generation circuit according to an embodiment of the present invention;
FIG. 4 is a circuit schematic of a serial pulse generation circuit according to one embodiment of the present invention;
FIG. 5 is a block schematic diagram of a serial pulse generation circuit according to another embodiment of the present invention;
FIG. 6 is a waveform diagram of input and output signals of a serial pulse generating circuit according to an embodiment of the invention;
FIG. 7 is a block schematic diagram of a charging device according to an embodiment of the invention; and
fig. 8 is a circuit schematic of a charging device according to one embodiment of the invention.
Reference numerals:
the receiving terminal 10, the parallel conversion module 20 and the serial pulse generation module 30;
a judgment unit 201, a decoding unit 202, and a parallel encoding unit 203;
a counting unit 301, a pulse width control signal generating unit 302, a frequency dividing unit 303, a flip-flop 304 and an MCG module 305;
a clock signal generator 310, a first frequency divider 320, a second frequency divider 330, and a logic control subunit 340; a not gate 341, a first nand gate 342, a second nand gate 343, and a third nand gate 344;
a secondary chip 100, a serial pulse generating circuit 101 and a main side chip 200;
switch tube Q and opto-coupler chip IC.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are illustrative and intended to be illustrative of the invention and are not to be construed as limiting the invention.
The serial pulse generating circuit and the charging device having the same according to the embodiments of the present invention are described below with reference to the accompanying drawings.
Fig. 2 is a block schematic diagram of a serial pulse generation circuit according to an embodiment of the present invention. As shown in fig. 2, the serial pulse generating circuit includes: a receiving end 10, a parallel conversion module 20 and a serial pulse generation module 30.
The receiving terminal 10 is configured to receive a request voltage signal output by a device to be charged; the parallel conversion module 20 is connected to the receiving terminal 10, and the parallel conversion module 20 is configured to generate N parallel digital signals corresponding to the request voltage signal according to the request voltage signal; the Serial pulse generating module 30 is connected to the parallel converting module 20, and the Serial pulse generating module 30 is configured to divide the frequency of the clock Signal according to the state of each digital Signal to generate a pulse Signal with a corresponding pulse width, and control the pulse signals corresponding to the N parallel digital signals to be sequentially Output to Output a Serial pulse Signal SSO (Serial Signal Output) corresponding to the requested voltage Signal.
Specifically, as shown in fig. 2, the receiving end 10 of the serial pulse generating circuit may be connected to voltage request ports D + and D-of the device to be charged, and the receiving end 10 detects voltages of the voltage request ports D + and D-respectively to obtain request voltage signals output by the device to be charged, where serial pulse signals SSO corresponding to different request voltage signals are different, and the charging device adjusts voltage output according to the serial pulse signals SSO to meet the voltage requirement of the device to be charged.
Further, the parallel conversion module 20 determines the request voltage signal received by the receiving terminal 10 and generates N parallel digital signals a0 to a (N-1) corresponding to the request voltage signal, where N is an integer greater than 1, and each of the digital signals has different high and low level states, so that the serial pulse generation module 30 divides the frequency of the clock signal according to the level state of each of the digital signals to generate a pulse signal corresponding to a pulse width, for example, if the digital signal a0 is in a low level state, the serial pulse generation module 30 generates a pulse signal of a first pulse width; if the digital signal a0 is in a high state, the serial pulse generating module 30 generates a pulse signal with a second pulse width.
In this way, the serial pulse generation module 30 controls the pulse signals corresponding to the N parallel digital signals to be sequentially output, where the pulse signals with different pulse widths correspond to different digital levels, for example, the pulse signal with the first pulse width corresponds to "0", and the pulse signal with the second pulse width corresponds to "1", so that serial conversion of the N parallel digital signals a0 to a (N-1) can be realized to output the serial pulse signal SSO corresponding to the request voltage signal, and the charging device adjusts the voltage output according to the serial pulse signal SSO.
According to an embodiment of the present invention, as shown in fig. 3a, the parallel conversion module 20 includes: a judgment unit 201, a decoding unit 202, and a parallel encoding unit 203.
The judging unit 201 is configured to judge a voltage level of the request voltage signal; the decoding unit 202 is connected to the judging unit 201, and the decoding unit 202 is configured to generate a voltage status signal according to the voltage level at which the request voltage signal is located; the parallel encoding unit 203 is connected to the decoding unit 202, and the parallel encoding unit 203 is configured to generate N parallel digital signals a0 to a (N-1) corresponding to the request voltage signal according to the voltage status signal.
Specifically, the receiving terminal 10 detects voltages of the voltage request ports D + and D-to obtain the request voltage signals (e.g. 3.3V, 0.6V and 0V) output by the device to be charged, the determining unit 201 may include a plurality of comparators, the determining unit 201 determines the voltage level of the request voltage signal after receiving the request voltage signal output by the device to be charged, wherein the determination result may be represented by a level state combination of D + H, D + L, D-H and D-L, and outputs the determination result to the decoding unit 202, and the decoding unit 202 generates corresponding voltage state signals, such as V5, V9 and V12, according to the determination result. The parallel encoding unit 203 receives the voltage state signal, converts the voltage state signal into N-channel parallel digital signals a0 to a (N-1), and outputs the N-channel parallel digital signals a0 to a (N-1) to the serial pulse generation module 30. The different level state combinations of the N paths of parallel digital signals A0 to A (N-1) correspond to different voltage state signals.
According to an embodiment of the present invention, the correspondence relationship between the voltage status signal generated by the decoding unit 202 and the request voltage signal according to the charging protocol Q2.0 can be as shown in the following table 1:
TABLE 1
| Voltage of D + port | Voltage of D-port | Voltage status signal |
| 0.6V | 0.6V | V12 (namely 12V) |
| 3.3V | 0.6V | V9 (namely 9V) |
| 3.3V | 3.3V | 20V |
| 0.6V | 0V | V5 (i.e. 5V) |
As can be seen from table 1, when the voltage of the voltage request port D + is 3.3V and the voltage of the voltage request port D-is 0.6V, the voltage status signal generated by the decoding unit 202 is V9, the serial pulse generating module 30 outputs the serial pulse signal SSO corresponding to the request voltage signal, and the charging device adjusts the voltage output to 9V according to the serial pulse signal SSO; when the voltage of the voltage request port D + is 0.6V and the voltage of the voltage request port D-is 0V, the voltage status signal generated by the decoding unit 202 is V5, the serial pulse generating module 30 outputs the serial pulse signal SSO corresponding to the request voltage signal, and the charging device adjusts the voltage output to 5V according to the serial pulse signal SSO.
According to an embodiment of the present invention, as shown in fig. 3b, the serial pulse generating circuit further includes a switch assembly 50, and the switch assembly 50 is connected between the receiving terminal 10 and the parallel converting module 20. The method comprises the steps of firstly carrying out USB BC1.2 detection at the moment when a serial pulse generating circuit is electrified, controlling a voltage request port D + and a voltage request port D-to be in short-circuit connection in an initial state, controlling the voltage request port D-to be disconnected with a ground resistor, simultaneously detecting the voltage of the voltage request port D +, controlling the voltage request port D + and the voltage request port D-to be disconnected with the short-circuit connection when the voltage of the voltage request port D + reaches a preset voltage value, such as 0.6V, and the duration time exceeds a preset time, such as 1s, and further judging a charging protocol, namely detecting the voltages of the voltage request ports D + and D-to obtain a request voltage signal output by a device to be charged.
According to an embodiment of the present invention, as shown in fig. 3b, the serial pulse generating circuit further includes: and a power detection unit 40, wherein the power detection unit 40 is connected to a preset power supply VDD, and the power detection unit 40 is configured to detect whether the preset power supply VDD of the serial pulse generation circuit fails, and control the serial pulse generation circuit to stop outputting the serial pulse signal SSO when the preset power supply VDD fails.
According to an embodiment of the present invention, as shown in fig. 4, the serial pulse generating module 30 includes: a counting unit 301, a pulse width control signal generating unit 302 and a frequency dividing unit 303.
The counting unit 301 is configured to count the number of outputs of the N-path parallel digital signals a0 to a (N-1) to generate a count signal; the pulse width control signal generating unit 302 is respectively connected with the counting unit 301 and the parallel conversion module 20, and the pulse width control signal generating unit 302 is used for controlling N parallel digital signals to be sequentially output according to the counting signal; the frequency dividing unit 303 is connected to the pulse width control signal generating unit 302, and the frequency dividing unit 303 is configured to divide the frequency of the clock signal according to the state of each digital signal to generate a pulse signal corresponding to the pulse width.
According to an embodiment of the present invention, as shown in fig. 4, the serial pulse generating module 30 further includes: and a first end of the flip-flop 304 is connected with the counting unit 301, a second end of the flip-flop 304 is respectively connected with the counting unit 301 and the frequency dividing unit 303, a third end of the flip-flop 304 is used for receiving a trigger signal, and the flip-flop 304 enables the counting unit 301 and the frequency dividing unit 303 after receiving the trigger signal through the third end.
According to an embodiment of the present invention, as shown in fig. 4, the third terminal of the flip-flop 304 may be connected to an MCG (multi Clock Generator) module 305, the MCG module 305 is configured to output a trigger signal to the flip-flop 304, when a request voltage signal output by a device to be charged changes, a level state of the corresponding N-path parallel digital signals a0 to a (N-1) changes, at this time, the MCG module 305 outputs a trigger signal (e.g., a mode state change pulse signal) to the flip-flop 304, and the third terminal of the flip-flop 304 outputs a high level to enable the counting unit 301 and the frequency dividing unit 303.
According to an embodiment of the present invention, the flip-flop 304 may be an RS flip-flop. The reset terminal of the RS flip-flop is connected to the counting unit 301 as the first terminal to receive the PE signal (i.e., the reset signal) output by the counting unit 301, the output terminal of the RS flip-flop is connected to the counting unit 301 and the frequency dividing unit 303 as the second terminal, and the set terminal of the RS flip-flop is used as the third terminal to receive the trigger signal.
Specifically, the serial pulse generation module 30 may convert the N-way parallel digital signals a0 to a (N-1) into a serial pulse signal corresponding to the request voltage signal. After the flip-flop 304 enables the counting unit 301 and the frequency dividing unit 303 to start operating, the counting unit 301 counts the number of output pulses of the N-channel parallel digital signals a0 to a (N-1), the counting signal can be represented by an (m +1) -bit binary number, for example, when m is 2, the counting signal can be represented by B2B1B0, the counting unit 301 can increase the counting value of B2B1B0 by 1 each time it receives one pulse signal, the pulse width control signal generating unit 302 controls the N-channel parallel digital signals a0 to a (N-1) to be sequentially output according to the counting signal to obtain corresponding pulse width control signals PWct, and outputs the pulse width control signals PWct to the frequency dividing unit 303. Further, the frequency dividing unit 303 divides the clock signal according to the state of each digital signal to generate a pulse signal corresponding to the pulse width.
According to one embodiment of the present invention, the pulse signal may be a positive pulse (e.g., SSO-1 in FIG. 6) or a negative pulse (e.g., SSO-2 in FIG. 6).
According to an embodiment of the present invention, assuming that there are 6 parallel input signals a 0-a 5, the count signal generated by the counting unit 301 can be represented by B2B1B0, i.e., m is 2, and the generated serial pulse signal is a positive pulse, at this time, the pulse width control signal generating unit 302 can control the N parallel digital signals a 0-a (N-1) to be sequentially output according to the corresponding relationship in table 2, so as to obtain the corresponding pulse width control signal PWct.
TABLE 2
| Counting signal | Pulse width controlSignal PWct |
| Count signal B2B1B0 ═ 000 " | A0 |
| Count signal B2B1B0 ═ 001 " | A1 |
| Count signal B2B1B0 ═ 010 " | A2 |
| Count signal B2B1B0 ═ 011 " | A3 |
| Count signal B2B1B0 ═ 100 " | A4 |
| Count signal B2B1B0 ═ 101 " | A5 |
| Count signal B2B1B0 ═ 110 " | PWct＝0，PE＝1 |
As can be seen from table 2, the count signal B2B1B0 is "000" and the pulse width control signal PWct is the digital signal a0 in the default case; after the 1 st pulse period, the counting signal B2B1B0 is "001", and the output pulse width control signal PWct is the digital signal a 1; after the 2 nd pulse signal, the count signal B2B1B0 becomes "010", and the output pulse width control signal PWct is the digital signal a 2; after the 3 rd pulse signal, the count signal B2B1B0 becomes "011", and the output pulse width control signal PWct is the digital signal A3; after the 4 th pulse signal, the count signal B2B1B0 becomes "100", and the output pulse width control signal PWct is the digital signal a 4; after the 5 th pulse signal, the count signal B2B1B0 becomes "101", and the output pulse width control signal PWct is the digital signal a 5. After the serial pulse generating module 30 outputs the 6 th pulse signal, the count signal B2B1B0 is equal to "110", the PE signal output by the counting unit 301 is at a high level, at this time, the reset terminal of the RS flip-flop receives the high level, so that the RS flip-flop outputs a low level to control the counting unit 301 to stop counting, and control the frequency dividing unit 303 to stop generating the pulse signal.
According to another embodiment of the present invention, it is also assumed that there are 6 parallel input signals a0 to a5, the count signal generated by the counting unit 301 can be represented by B2B1B0, i.e., m is 2, and the generated serial pulse signal is a negative pulse, and at this time, the pulse width control signal generating unit 302 can control the N parallel digital signals a0 to a (N-1) to be sequentially output according to the corresponding relationship of table 3 to obtain the corresponding pulse width control signal PWct.
TABLE 3
| Condition | Output pulse width control signal PWct |
| Count signal B2B1B0 ═ 000 " | “1” |
| The count signal B2B1B0 ≠ "000" and SSO ═ 1 " | “0” |
| The count signal B2B1B0 is "001" and SSO is "0" | A0 |
| The count signal B2B1B0 is "010" and SSO is "0" | A1 |
| The count signal B2B1B0 is "011" and SSO is "0" | A2 |
| The count signal B2B1B0 is "100" and SSO is "0" | A3 |
| The count signal B2B1B0 is "101" and SSO is "0" | A4 |
| The count signal B2B1B0 is "110" and SSO is "0" | A5 |
| Count signal B2B1B0 ═ 111 " | PWct＝0，PE＝1 |
As can be seen from table 3, when the count signal B2B1B0 is "000", the output pulse width control signal PWct is at a high level, and the serial pulse signal SSO outputs a high level; when the count signal B2B1B0 ≠ "000" and the serial pulse signal SSO is at a high level, the output pulse width control signal PWct is at a low level. In this way, after the 1 st pulse period, when the count signal B2B1B0 is "001" and the serial pulse signal SSO is at the low level, the output pulse width control signal PWct is the digital signal a 0; after the 2 nd pulse signal, when the count signal B2B1B0 becomes "010" and the serial pulse signal SSO is at a low level, the pulse width control signal PWct output is the digital signal a 1; after the 3 rd pulse signal, when the count signal B2B1B0 is "011" and the serial pulse signal SSO is at a low level, the output pulse width control signal PWct is the digital signal a 2; after the 4 th pulse signal, when the count signal B2B1B0 is "100" and the serial pulse signal SSO is at the low level, the output pulse width control signal PWct is the digital signal A3; after the 5 th pulse signal, when the count signal B2B1B0 is "101" and the serial pulse signal SSO is at a low level, the output pulse width control signal PWct is the digital signal a 4; when the count signal B2B1B0 becomes "110" and the serial pulse signal SSO is at the low level after the 6 th pulse signal, the output pulse width control signal PWct is the digital signal a 5. After the serial pulse generating module 30 outputs the 7 th pulse signal, the count signal B2B1B0 is "111", and the PE signal (i.e., the reset signal) output by the counting unit 301 is at a high level, at this time, the reset terminal of the RS flip-flop receives the high level, so that the RS flip-flop outputs a low level to control the counting unit 301 to stop counting, and control the frequency dividing unit 303 to stop generating the pulse signal.
According to an embodiment of the present invention, as shown in fig. 5, the frequency dividing unit 303 includes: a clock signal generator 310, a first frequency divider 320, a second frequency divider 330, and a logic control subunit 340.
The clock signal generator 310 is configured to generate a clock signal; the first frequency divider 320 is connected to the clock signal generator 310, and the first frequency divider 320 is configured to divide the clock signal to generate a pulse signal with a first pulse width; the second frequency divider 330 is configured to divide the frequency of the clock signal to generate a pulse signal of a first pulse width when the first frequency divider 320 is masked, and to divide the frequency of the pulse signal of the first pulse width to generate a pulse signal of a second pulse width when the first frequency divider 320 participates in the frequency division; the logic control subunit 340 is respectively connected to the pulse width control signal generating unit 302, the clock signal generator 310, the first frequency divider 320, and the second frequency divider 330, and the logic control subunit 340 is configured to control the first frequency divider 320 to participate in frequency division or to be masked according to a state of each digital signal.
According to an embodiment of the present invention, as shown in fig. 5, the logic control subunit 340 includes: the pulse width control circuit comprises a not gate 341, a first nand gate 342, a second nand gate 343 and a third nand gate 344, wherein the input end of the not gate 341 is connected with the pulse width control signal generating unit 302; the first input end of the first nand gate 342 is connected to the output end of the nand gate 341, and the second input end of the first nand gate 342 is connected to the clock signal generator 310; a first input end of the second nand gate 343 is connected to the pulse width control signal generating unit 302, and a second input end of the second nand gate 343 is connected to the first frequency divider 320; a first input of the third nand-gate 344 is connected to the output of the first nand-gate 342, a second input of the third nand-gate 344 is connected to the output of the second nand-gate 343, and an output of the third nand-gate 344 is connected to the second frequency divider 330.
Specifically, the clock signal generator 310 may include a clock divider for dividing the high-precision clock signal CLK and outputting a clock signal of a corresponding frequency, i.e., the preset clock signal PUL, and the pulse width control signal generation unit 302 controls the N-way parallel digital signals a0 to a (N-1) to be sequentially output according to the count signals B0 to Bm.
More specifically, if the digital signal output by the pulse width control signal generation unit 302 is at a high level (i.e., the pulse width control signal PWct is at a high level), the not gate 341 outputs a low level, the first nand gate 342 performs logic processing on the preset clock signal PUL and the low level output by the not gate 341 to output a high level, and at the same time, the first frequency divider 320 performs frequency division to generate a pulse signal of a first pulse width, and as known from the logic function of the nand gate, the logic control subunit 340 performs logic processing on the pulse signal of the first pulse width to generate a first output signal, which is consistent with the pulse signal of the first pulse width, and the second frequency divider 330 performs frequency division processing on the first output signal to generate a pulse signal of a second pulse width. If the digital signal output by the pulse width control signal generating unit 302 is at a low level, the not gate 341 outputs a high level, the enable terminal of the first frequency divider 320 receives a low level, so the first frequency divider 320 is shielded, the second nand gate 343 outputs a high level, according to the logic function of the nand gate, the logic control subunit 340 performs logic processing on the preset clock signal PUL to generate a second output signal, the second output signal is consistent with the preset clock signal PUL, and the second frequency divider 330 performs frequency division processing on the second output signal to generate a pulse signal with the first pulse width.
According to an embodiment of the present invention, the second pulse width may be an integer multiple of the first pulse width. Preferably, the second pulse width may be twice the first pulse width.
According to an embodiment of the present invention, assuming that there are 6 parallel input signals a 0-a 5 and the level states of the 6 parallel input signals a 0-a 5 are shown in fig. 6, and it can be known from the analysis of table 2 and table 3 that when the pulse width control signal generating unit 302 controls the N parallel digital signals a 0-a (N-1) to be sequentially output according to the corresponding relationship shown in table 2, the second frequency divider 330 can output the serial pulse signal SSO-1, wherein the pulse signal SSO-1 is a positive pulse; when the pulse width control signal generating unit 302 controls the N parallel digital signals a0 to a (N-1) to be sequentially output according to the correspondence relationship shown in table 3, the second frequency divider 330 may output the serial pulse signal SSO-2, where the pulse signal SSO-2 is a negative pulse.
In this way, the frequency dividing unit 303 may divide the clock signal according to the state of each digital signal to generate pulse signals (e.g., the serial pulse signal SSO-1 or SSO-2) corresponding to different pulse widths, where the pulse signals of different pulse widths correspond to different digital levels, e.g., the pulse signal of the first pulse width corresponds to "0" and the pulse signal of the second pulse width corresponds to "1". Thus, the serial pulse signal sequence shown in fig. 6 is "110101", so that serial conversion of the N parallel digital signals a0 to a (N-1) can be realized to output the serial pulse signal SSO corresponding to the request voltage, and the charging device adjusts the voltage output according to the serial pulse signal SSO.
According to an embodiment of the present invention, the device to be charged may be a mobile phone or a tablet computer.
In summary, according to the serial pulse generating circuit provided by the embodiment of the present invention, the receiving end receives the request voltage output by the charging device, the parallel conversion module generates N parallel digital signals corresponding to the request voltage signal according to the request voltage signal, and the serial pulse generating module divides the frequency of the clock signal according to the state of each digital signal to generate a pulse signal corresponding to a pulse width, and controls the pulse signals corresponding to the N parallel digital signals to be sequentially output, so as to output the serial pulse signal corresponding to the request voltage signal. Therefore, the serial pulse generating circuit of the embodiment of the invention utilizes the high-precision clock signal to generate the serial pulse signal corresponding to the request voltage signal, improves the time precision of signal output, and effectively reduces the chip area.
Fig. 7 is a block diagram of a charging device according to an embodiment of the present invention. As shown in fig. 7, the charging device 300 includes: a secondary chip 100 and a main side chip 200, wherein the secondary chip 100 comprises a serial pulse generating circuit 101, and the secondary chip 100 is used for generating a serial pulse signal SSO corresponding to a request voltage signal according to the request voltage signal; the main-side chip 200 is used for adjusting the voltage output of the main-side chip according to the serial pulse signal SSO.
It should be noted that, because the adjustment level of the voltage output in the charging protocol Q3.0 is more, the serial pulse signal SSO may be used for signal transmission, and when the serial pulse signal SSO is used for signal transmission, the pulse signals with different pulse widths correspond to different digital levels, for example, the pulse signal with the first pulse width corresponds to "0" and the pulse signal with the second pulse width corresponds to "1", so that different request voltage signals may correspond to different pulse signals. In the embodiment of the present invention, the serial pulse signal SSO needs to have higher precision to ensure that the primary chip 200 can detect and decode the serial pulse signal SSO output by the secondary chip 100, so as to adjust the voltage output of the primary chip. In addition, in order to reduce the influence of signal delay in the signal transmission process and improve the anti-interference capability of the serial pulse signal SSO, it is necessary to ensure the pulse width of the serial pulse signal SSO.
According to an embodiment of the present invention, as shown in fig. 8, the serial pulse generating circuit 101 is connected to the voltage request ports D + and D-of the device to be charged to obtain the request voltage signal output by the device to be charged, and outputs the serial pulse signal SSO corresponding to the request voltage signal according to the request voltage signal, wherein the serial pulse signals SSO corresponding to different request voltage signals are different. Furthermore, the serial pulse signal SSO output by the secondary chip 100 can be output to the primary-side chip 200 through the optocoupler chip IC of the charging device 300, and the primary-side chip 200 decodes the received signal and controls the switching tube Q to be turned on or off according to the decoding result to adjust the voltage output of the primary-side chip, i.e., adjust the output voltages at two ends of Vout + and Vout-.
According to an embodiment of the present invention, the charging device is used for charging a device to be charged, wherein the device to be charged may be a mobile phone or a tablet computer.
In summary, according to the charging device provided by the embodiment of the invention, the secondary chip generates the serial pulse signal corresponding to the request voltage signal through the serial pulse generating circuit of the embodiment, and further, the primary chip adjusts the voltage output of the primary chip according to the serial pulse signal. Therefore, the charging device provided by the embodiment of the invention utilizes the high-precision clock signal to generate the serial pulse signal corresponding to the request voltage signal, so that the time precision of signal output is improved, and the voltage output is effectively regulated.
In the description of the present invention, it is to be understood that the terms "central," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the invention and to simplify the description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and are therefore not to be considered limiting of the invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or they may be connected internally or in any other suitable relationship, unless expressly stated otherwise. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In the present invention, unless otherwise expressly stated or limited, the first feature "on" or "under" the second feature may be directly contacting the first and second features or indirectly contacting the first and second features through an intermediate. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.
Claims (10)
1. A serial pulse generating circuit, comprising:
the receiving end is used for receiving a request voltage signal output by the equipment to be charged;
the parallel conversion module is connected with the receiving end and used for generating N paths of parallel digital signals corresponding to the request voltage signals according to the request voltage signals;
and the serial pulse generation module is connected with the parallel conversion module and is used for dividing the frequency of the clock signal according to the state of each path of digital signal to generate a pulse signal corresponding to the pulse width and controlling the pulse signals corresponding to the N paths of parallel digital signals to be sequentially output so as to output the serial pulse signal corresponding to the request voltage signal.
2. The serial pulse generating circuit according to claim 1, wherein the serial pulse generating module comprises:
a counting unit for counting the number of outputs of the N-path parallel digital signals to generate a count signal;
the pulse width control signal generating unit is respectively connected with the counting unit and the parallel conversion module and is used for controlling the N paths of parallel digital signals to be sequentially output according to the counting signal;
and the frequency dividing unit is connected with the pulse width control signal generating unit and is used for dividing the frequency of the clock signal according to the state of each path of digital signal so as to generate a pulse signal corresponding to the pulse width.
3. The serial pulse generating circuit according to claim 2, wherein the frequency dividing unit comprises:
a clock signal generator for generating a clock signal;
the first frequency divider is connected with the clock signal generator and is used for dividing the frequency of the clock signal to generate a pulse signal with a first pulse width;
a second frequency divider for dividing the clock signal to generate a pulse signal of a first pulse width when the first frequency divider is masked and dividing the pulse signal of the first pulse width to generate a pulse signal of a second pulse width when the first frequency divider participates in the frequency division;
and the logic control subunit is respectively connected with the pulse width control signal generation unit, the clock signal generator, the first frequency divider and the second frequency divider, and is used for controlling the first frequency divider to participate in frequency division or be shielded according to the state of each path of digital signal.
4. The serial pulse generating circuit of claim 3, wherein the logic control subunit comprises:
the input end of the NOT gate is connected with the pulse width control signal generating unit;
a first input end of the first NAND gate is connected with an output end of the NOT gate, and a second input end of the first NAND gate is connected with the clock signal generator;
a first input end of the second nand gate is connected with the pulse width control signal generating unit, and a second input end of the second nand gate is connected with the first frequency divider;
and a first input end of the third NAND gate is connected with the output end of the first NAND gate, a second input end of the third NAND gate is connected with the output end of the second NAND gate, and the output end of the third NAND gate is connected with the second frequency divider.
5. The serial pulse generating circuit of claim 3, wherein the second pulse width is an integer multiple of the first pulse width.
6. The serial pulse generating circuit of claim 2, wherein the serial pulse generating module further comprises:
the first end of the trigger is connected with the counting unit, the second end of the trigger is respectively connected with the counting unit and the frequency dividing unit, the third end of the trigger is used for receiving a trigger signal, and the trigger enables the counting unit and the frequency dividing unit after receiving the trigger signal through the third end.
7. The serial pulse generating circuit of claim 1, wherein the parallel conversion module comprises:
the judging unit is used for judging the voltage level of the request voltage signal;
the decoding unit is connected with the judging unit and is used for generating a voltage state signal according to the voltage level of the request voltage signal;
and the parallel coding unit is connected with the decoding unit and is used for generating N paths of parallel digital signals corresponding to the request voltage according to the voltage state signal.
8. The serial pulse generating circuit of claim 1, wherein the device to be charged is a mobile phone or a tablet computer.
9. A charging device, comprising:
a secondary chip comprising the serial pulse generation circuit according to any one of claims 1 to 8, the secondary chip being configured to generate a serial pulse signal corresponding to the request voltage signal from the request voltage signal;
and the main side chip is used for adjusting the voltage output of the main side chip according to the serial pulse signal.
10. The charging device according to claim 9, wherein the charging device is configured to charge a device to be charged, and the device to be charged is a mobile phone or a tablet computer.
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| CN201611130269.7A CN108614791B (en) | 2016-12-09 | 2016-12-09 | Serial pulse generating circuit and charging device |
| PCT/CN2017/110499 WO2018103500A1 (en) | 2016-12-09 | 2017-11-10 | Serial pulse generation circuit and charging device |
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| CN201611130269.7A CN108614791B (en) | 2016-12-09 | 2016-12-09 | Serial pulse generating circuit and charging device |
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| CN114070348A (en) * | 2021-09-27 | 2022-02-18 | 南京矽力微电子技术有限公司 | Single-wire isolated communication module, system and communication method |
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| CN1885721A (en) * | 2005-06-21 | 2006-12-27 | 三星电子株式会社 | Phase locked loop circuit and method of locking a phase |
| CN203217298U (en) * | 2013-01-31 | 2013-09-25 | 无锡德思普科技有限公司 | Parallel data port AD sampling system based on DSP |
| CN104092274A (en) * | 2014-07-29 | 2014-10-08 | 深圳市至高通信技术发展有限公司 | Intelligent charger with output voltage changing function |
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| JP3795392B2 (en) * | 2001-12-28 | 2006-07-12 | 株式会社 エニイワイヤ | Control and monitoring signal transmission system |
| US20070150761A1 (en) * | 2005-12-28 | 2007-06-28 | International Business Machines Corporation | Power supply communication system and method |
| JP4308858B2 (en) * | 2007-02-16 | 2009-08-05 | セイコーエプソン株式会社 | Power transmission control device, power reception control device, non-contact power transmission system, power transmission device, power reception device, and electronic equipment |
| CN202749886U (en) * | 2012-09-24 | 2013-02-20 | 宁波汉浦工具有限公司 | Lithium battery charging circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1885721A (en) * | 2005-06-21 | 2006-12-27 | 三星电子株式会社 | Phase locked loop circuit and method of locking a phase |
| CN203217298U (en) * | 2013-01-31 | 2013-09-25 | 无锡德思普科技有限公司 | Parallel data port AD sampling system based on DSP |
| CN104092274A (en) * | 2014-07-29 | 2014-10-08 | 深圳市至高通信技术发展有限公司 | Intelligent charger with output voltage changing function |
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Effective date of registration: 20210210 Address after: 518119 No.1 Yan'an Road, Kuiyong street, Dapeng New District, Shenzhen City, Guangdong Province Patentee after: BYD Semiconductor Co.,Ltd. Address before: 518118 BYD Road, Pingshan New District, Shenzhen, Guangdong 3009 Patentee before: BYD Co.,Ltd. |