CN108614271B - Multichannel ultrasonic wave arbitrary waveform signal generator with feedback correction - Google Patents
Multichannel ultrasonic wave arbitrary waveform signal generator with feedback correction Download PDFInfo
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S15/00—Systems using the reflection or reradiation of acoustic waves, e.g. sonar systems
- G01S15/88—Sonar systems specially adapted for specific applications
- G01S15/89—Sonar systems specially adapted for specific applications for mapping or imaging
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/52—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S15/00
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Abstract
The invention discloses a multichannel ultrasonic wave arbitrary waveform signal generator with feedback correction, which comprises a PC end, a JTAG interface, an FPGA, an active crystal oscillator, a DAC module, a filtering module, a feedback module and a start key, wherein the feedback module is connected with the starting key; the invention adopts DDS technology to generate m paths of phase signals in parallel; a feedback module and a feedback signal processing module are added behind the filter circuit; the multi-channel signal detection device is characterized in that only one m-channel selector and one ADC module are used for detecting multi-channel signals, so that the consumption of resources is greatly reduced, and the structure is more compact; meanwhile, the feedback signal processing module can detect the actual initial phases of the multipath signals; only one zero detection module is used for sequentially obtaining initial phases of all channels and converting the amplitude and the phase in a table look-up mode, so that resources occupied by feedback signal processing are greatly reduced.
Description
Technical Field
The invention relates to a multi-channel DDS signal generator, in particular to a multi-channel ultrasonic wave arbitrary waveform signal generator with feedback correction.
Background
The ultrasonic phased array technology forms various effects such as focusing and scanning of a synthesized sound beam by controlling the emission of each array element of an array transducer, thereby carrying out ultrasonic imaging. In the phased array ultrasonic emission state, each array element in the array transducer is sequentially excited according to a certain delay rule, and the generated ultrasonic emission sub-beams are spatially synthesized to form a focusing point and directivity. The delay rule of each array element excitation is changed, the focus position and the beam direction can be changed, and scanning focusing in a certain space range is formed. The key digital technology in the ultrasonic phased array system mainly refers to space-time control of the wave beam, and advanced digital electronic technology and microcomputer technology are adopted to accurately control the phased wave beam in the transmitting state so as to obtain the optimal transmitting wave beam characteristic.
Compared with the traditional frequency synthesizer, the direct digital frequency synthesizer (DDS) has many advantages in frequency synthesis and arbitrary waveform generation, such as fast frequency conversion, short output signal establishment time, high spectrum purity, extremely high frequency precision and resolution, easiness in controlling various modulation modes and the like. FPGA (Field-Programmable Gate Array, field programmable gate array) as a high performance programmable logic device can provide an excellent solution for a variety of circuits, and the implementation with FPGA will be more flexible and controllable for digital frequency synthesis. And because the integration level of the FPGA is particularly high, the whole system can be downloaded into the same chip, so-called system on chip (SoC) is realized, thereby the volume of the product with large and small size is increased, and the reliability of the system is improved.
In the existing multi-channel ultrasonic signal transmitting technology, the basic structure of each channel consists of a phase accumulator (PD), a waveform memory (RAM), a digital-to-analog converter (DAC) and a low-pass filter (LPF), so as to form a multi-channel signal generator which is mutually independent and has a certain phase difference.
The ultrasonic phased array transmitting technology has the following defects: 1. the phase error between the actual phase and the ideal phase is large due to the delay difference between the wiring and the chip. 2. The multi-channel signal generator with feedback requires a plurality of phase accumulators (PD), waveform memories (RAM), digital-to-analog converters (DAC) and filter circuits and analog-to-digital converters (ADC) in multiple channels, which makes the circuit complex and difficult to realize.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides a multichannel ultrasonic arbitrary waveform signal generator with feedback correction.
The aim of the invention is realized by the following technical scheme: a multi-channel ultrasonic wave arbitrary waveform signal generator with feedback correction comprises a PC end, a JTAG interface, an FPGA, a DAC module, a filtering module and a feedback module;
the PC end stores phase and amplitude mapping data of an ultrasonic wave form into m wave form lookup table RAMs through a JTAG interface, wherein m represents the number of channels, the amplitude and phase mapping data are stored into two phase lookup table RAMs, a first phase lookup table stores phase information of a first quadrant and a fourth quadrant, a second phase lookup table stores phase information of a second quadrant and a third quadrant, data types of phase signals and amplitude signals are binary unsigned numbers, the highest bit is defined to represent a symbol bit, and the rest bits represent data bits;
the FPGA receives mapping data, channel control signals, frequency control signals and initial phase signals in the corresponding RAMs through a JTAG interface; forming m channels in the FPGA by utilizing a DDS (direct digital synthesizer) according to the channel control signals and the frequency control signals, sequentially searching signals of the m channels from corresponding waveform lookup tables to obtain amplitude signals corresponding to phases, connecting the amplitude signals to a DAC (digital-to-analog conversion) module for digital-to-analog conversion, filtering an output waveform by utilizing a filtering module, and connecting each filtered channel to a feedback module;
the feedback module consists of a multiplexer and an ADC module; the multiplexer and the ADC module sequentially sample each channel and convey the sampled signals to a feedback signal processing module in the FPGA;
the feedback signal processing module comprises a buffer, a zero detection module, a phase compensation unit, a phase difference calculation unit, a state detection unit and a phase correction unit;
the zero detection module consists of a comparator and an m-bit system counter, the counter of the zero detection module starts to count, the sampled amplitude signal is compared with the minimum amplitude signal in m channels, and if the amplitude is detected to be larger than the minimum amplitude, the amplitude signal is marked as w i The counter obtains the corresponding channel serial number i, and m-1 amplitude signals are recorded as follows: w (w) i+1 w i+2 …w m w 1 w 2 …w i-1 The corresponding channel sequence number is recorded as: i+1i+ … 1 2 … i-1; and sequentially taking the values of all channels after one counting period: w' i w′ i+1 w′ i+2 … w′ m w′ 1 w′ 2 … w′ i-1 The method comprises the steps of carrying out a first treatment on the surface of the The obtained data are sent to a state detection unit, the previous amplitude signal and the next amplitude signal of each channel are subtracted, and the value of the highest bit, namely the sign bit, is represented by A; if the amplitude of the previous amplitude signal is greater than the amplitude of the next amplitude signal, a=0, and if the amplitude is less than the amplitude of the next amplitude signal, a=1; at the same time make m paths of amplitude signals w i w i+1 w i+2 … w m w 1 w 2 … w i-1 Sending the phase compensation unit, obtaining a corresponding phase value from a phase lookup table by using a table lookup method, and inquiring a corresponding phase from a first phase lookup table if A=1; if a=0, querying a corresponding phase value from the second phase lookup table; compensating the phase of each channel;
the phase difference calculating unit subtracts the compensated phase value from a preset initial phase signal to obtain the phase difference of each channel, and the value of the highest bit, namely the sign bit, is represented by B; if the compensated phase value is greater than the initial phase, b=0, and if it is less than b=1; then modifying the initial phase according to the phase difference calculation unit; b=0 indicates a phase advance, and b=indicates a phase retard; if the phase difference is advanced, the initial phase of the channel is subtracted by the phase correction unit, and if the phase difference is retarded, the phase difference is added by the phase correction unit, and finally the phase difference is fed back to the DDS for correction.
Further, generating a phase rotation value mif file and a phase rotation value mif file at a PC end by utilizing MATLAB, generating a RAM IP core through an IP core function in Quartus II software, and importing the generated mif file data into the RAM IP core; and transmitting the control instruction and the transmitting parameters into the FPGA through the JTAG interface.
Further, the method comprises the steps of,generating a clock signal f by an active crystal oscillator cLk And are respectively connected to the multiplexer and the ADC of the FPGA, the DAC module and the feedback module.
Further, the channel control signal includes a channel number and a channel number m selected by a user, the frequency control signal is a frequency signal of the transmitted ultrasonic waveform set by the user, and the initial phase signal is an initial phase signal of the transmitted ultrasonic waveform set by the user.
Further, the FPGA receives the channel control signals and the frequency control signals to generate a corresponding phase accumulator, data output by the phase accumulator are sent to corresponding m adders to be accumulated with the received initial phase signals, address information of each channel is obtained, and amplitude signals corresponding to the phases are searched for according to the address information in a corresponding waveform lookup table.
The beneficial effects of the invention are as follows: compared with the prior art, the invention adopts DDS technology to generate m paths of phase signals in parallel. And a feedback module and a feedback signal processing module are added behind the filter circuit. The multi-channel signal detection device is characterized in that only one m-channel selector and one ADC module are used for detecting multi-channel signals, so that the consumption of resources is greatly reduced, and the structure is more compact. Meanwhile, the feedback signal processing module can detect the actual initial phases of the multipath signals. The method can sequentially obtain initial phases of all channels by using only one zero detection module and convert the amplitude and the phase by combining a table look-up mode, improves the accuracy of detecting the phase, and greatly reduces the resources occupied by feedback signal processing.
Drawings
FIG. 1 is a schematic illustration of the overall structure of the present invention;
FIG. 2 is a schematic diagram of the operation of the interior of the FPGA;
fig. 3 is a schematic diagram of the operation of the DDS;
FIG. 4 is a schematic block diagram of a feedback module;
fig. 5 is a schematic block diagram of feedback signal processing.
Detailed Description
The invention is described in further detail below with reference to the drawings and the specific examples.
The invention can generate the phase-to-amplitude. Mif file and the amplitude-to-phase. Mif file at the PC (personal computer) end by utilizing MATLAB. Through the rich IP core (intellectual property core) function in the Quartz II software provided by Altera company, a RAM IP core is generated and the generated. Mif file data is imported therein. Writing control program and transmitting parameters, transmitting the control program and transmitting parameters into a development board of an FPGA (field programmable gate array) chip of Altera company through a JTAG interface, storing corresponding phase and amplitude information into a corresponding waveform lookup table (RAM) and a corresponding phase lookup table (RAM), and forming a special circuit inside the FPGA.
Fig. 1 is a schematic diagram of the overall structure of the invention, which mainly comprises a PC terminal, a JTAG interface, an FPGA, an active crystal oscillator, a DAC module, a filter module, a feedback module and a start key. The PC end stores phase and amplitude mapping data of an ultrasonic wave form into m wave form lookup tables through a JTAG interface, wherein m represents the number of channels, the amplitude and phase mapping data are stored into two phase lookup tables, the first amplitude and phase mapping phase lookup table stores phase information of a first quadrant and a fourth quadrant, and the second amplitude and phase mapping phase lookup table stores phase information of a second quadrant and a third quadrant. And corresponding special circuits are formed inside the FPGA. Clock signal f generated by active crystal oscillator cLk And the feedback module is respectively connected to the FPGA, the DAC module and the feedback module.
Fig. 2 shows a schematic diagram of the operation of the interior of the FPGA. The FPGA receives mapping data, channel control signals, frequency control signals and initial phase signals in the corresponding RAMs through a JTAG interface; the channel control signal comprises a channel sequence number and a channel number m selected by a user, the frequency control signal is a frequency signal of an emitted ultrasonic wave form set by the user, and the initial phase signal is an initial phase signal of the emitted ultrasonic wave form set by the user; after the data transmission is completed, pressing a start key; and forming m channels by utilizing a DDS (direct digital frequency synthesizer) in the FPGA according to the channel control signals and the frequency control signals, sequentially obtaining amplitude signals corresponding to the phases from corresponding waveform lookup tables i by the signals of the m channels, connecting the amplitude signals to a DAC (digital-to-analog converter) module for digital-to-analog conversion, filtering output waveforms, connecting each channel after filtering to a feedback module, and connecting signals output by the feedback module to a feedback signal processing module in the FPGA.
Fig. 3 shows a schematic diagram of the operation of the DDS. The FPGA receives the channel control signals and the frequency control signals to generate a corresponding phase accumulator, data output by the phase accumulator are sent to corresponding m adders to be accumulated with the received initial phase signals, address information of each channel is obtained, and amplitude signals corresponding to the phases are searched for according to the address information in a corresponding waveform lookup table i.
Fig. 4 shows a schematic block diagram of the feedback module in the present invention. It consists of a multiplexer and an ADC module. The multiplexer and the ADC module adopt the same frequency f cLk Is provided. The method comprises the steps of sequentially sampling all channels and transmitting sampled signals to a feedback signal processing module in the FPGA.
Fig. 5 presents a schematic block diagram of the feedback signal processing of the invention. The zero detection module consists of a comparator and an m-bit counter, and the value of m is determined by a channel control signal. The working principle is that the counter starts counting and compares the sampled amplitude signal with the minimum amplitude signal in m channels. If the amplitude is detected to be greater than the minimum value, the amplitude signal is marked as w i The counter obtains the corresponding channel serial number i, sequentially stores the data into the memory, and marks m-1 amplitude signals as follows: w (w) i+1 w i+2 … w m w 1 w 2 … w i-1 The corresponding channel sequence number is recorded as: i+1i+ … 1 2 … i-1; and then the value of each channel after a counting period is taken: w' i w′ i+1 w′ i+2 … w′ m w′ 1 w′ 2 … w′ i-1 . The obtained data are sent to a state detection unit, and the previous amplitude signal and the next amplitude signal of each channel are subtracted, and the value of the highest bit, namely the sign bit, is denoted by A. If the amplitude of the previous amplitude signal is greater than the amplitude of the next amplitude signal, a=0If smaller than a=1.
At the same time make m paths of amplitude signals w i w i+1 w i+2 … w m w 1 w 2 … w i-1 Sending the phase compensation unit to obtain corresponding phase value p from the phase lookup table by using a table lookup method i If a=1, the corresponding phase value is queried from the first phase lookup table. If a=0, the corresponding phase value is queried from the second phase look-up table. And compensating the phase of each channel: i.e. channel i has a phase p i -0, the second channel phase p i+1 -1, the phase of the last channel in turn being p i-1 -(m-1)。
The phase difference calculating unit subtracts the compensated phase value from a preset initial phase signal to obtain a phase difference of each channel, wherein the value of the sign bit which is the highest bit is represented by B, if the compensated phase value is greater than the initial phase, b=0, and if the compensated phase value is less than the initial phase, b=1. The initial phase is modified according to the phase difference calculation unit. For example, b=0 indicates a phase advance; b=1 then represents the phase lag. If the channel is advanced, the initial phase of the channel is subtracted from the phase difference, if the channel is retarded, the initial phase is added with the complementary code of the phase difference, and finally the complementary code is fed back to the DDS for correction.
In this specification, it should be noted that the multi-channel signal generator provided in the embodiment of the present invention is only a specific example of the present invention, and it is obvious that the technical solution of the present invention is not limited to the signal generator described in the foregoing embodiment, and in fact, various modifications, transformations and variations may be made in the technical solution of the present invention. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense. Any simple modification and equivalent variations and modifications of the above embodiments according to the technical principles of the present invention should be considered to fall within the scope of the present invention.
Claims (5)
1. The multichannel ultrasonic wave arbitrary waveform signal generator with feedback correction is characterized by comprising a PC end, a JTAG interface, an FPGA, a DAC module, a filtering module and a feedback module;
the PC end stores phase and amplitude mapping data of an ultrasonic wave form into m wave form lookup table RAMs through a JTAG interface, wherein m represents the number of channels, the amplitude and phase mapping data are stored into two phase lookup table RAMs, a first phase lookup table stores phase information of a first quadrant and a fourth quadrant, a second phase lookup table stores phase information of a second quadrant and a third quadrant, data types of phase signals and amplitude signals are binary unsigned numbers, the highest bit is defined to represent a symbol bit, and the rest bits represent data bits;
the FPGA receives mapping data, channel control signals, frequency control signals and initial phase signals in the corresponding RAMs through a JTAG interface; forming m channels in the FPGA by utilizing a DDS (direct digital synthesizer) according to the channel control signals and the frequency control signals, sequentially searching signals of the m channels from corresponding waveform lookup tables to obtain amplitude signals corresponding to phases, connecting the amplitude signals to a DAC (digital-to-analog conversion) module for digital-to-analog conversion, filtering an output waveform by utilizing a filtering module, and connecting each filtered channel to a feedback module;
the feedback module consists of a multiplexer and an ADC module; the multiplexer and the ADC module sequentially sample each channel and convey the sampled signals to a feedback signal processing module in the FPGA;
the feedback signal processing module comprises a buffer, a zero detection module, a phase compensation unit, a phase difference calculation unit, a state detection unit and a phase correction unit;
the zero detection module consists of a comparator and an m-bit system counter, the counter of the zero detection module starts to count, the sampled amplitude signal is compared with the minimum amplitude signal in m channels, and if the amplitude is detected to be larger than the minimum amplitude, the amplitude signal is marked as w i The counter obtains the corresponding channel serial number i, and m-1 amplitude signals are recorded as follows: w (w) i+1 w i+2 … w m w 1 w 2 … w i-1 The corresponding channel sequence number is recorded as: i+1i+ … 1 2 … i-1; and sequentially taking the values of all channels after one counting period: w' i w′ i+1 w′ i+2 … w′ m w′ 1 w′ 2 … w′ i-1 The method comprises the steps of carrying out a first treatment on the surface of the The obtained data are sent to a state detection unit, the previous amplitude signal and the next amplitude signal of each channel are subtracted, and the value of the highest bit, namely the sign bit, is represented by A; if the amplitude of the previous amplitude signal is greater than the amplitude of the next amplitude signal, a=0, and if the amplitude is less than the amplitude of the next amplitude signal, a=1; at the same time make m paths of amplitude signals w i w i+1 w i+2 … w m w 1 w 2 … w i-1 Sending the phase compensation unit, obtaining a corresponding phase value from a phase lookup table by using a table lookup method, and inquiring the corresponding phase value from a first phase lookup table if A=1; if a=0, querying a corresponding phase value from the second phase lookup table; compensating the phase of each channel;
the phase difference calculating unit subtracts the compensated phase value from a preset initial phase signal to obtain the phase difference of each channel, and the value of the highest bit, namely the sign bit, is represented by B; if the compensated phase value is greater than the initial phase, b=0, and if it is less than b=1; then modifying the initial phase according to the phase difference calculation unit; b=0 indicates a phase advance, and b=indicates a phase retard; if the phase difference is advanced, the initial phase of the channel is subtracted by the phase correction unit, and if the phase difference is retarded, the phase difference is added by the phase correction unit, and finally the phase difference is fed back to the DDS for correction.
2. The multi-channel ultrasonic wave arbitrary waveform signal generator with feedback correction according to claim 1, wherein a MATLAB is utilized to generate a phase-to-amplitude-converted mif file and a phase-to-amplitude-converted mif file at a PC end, a RAM IP core is generated through an IP core function in Quartus II software, and the generated mif file data is imported into the RAM IP core; and transmitting the control instruction and the transmitting parameters into the FPGA through the JTAG interface.
3. The multi-channel ultrasonic arbitrary waveform signal generator with feedback correction according to claim 1, wherein the clock signal f is generated by an active crystal oscillator cLk And are respectively connected to the multiplexer and the ADC of the FPGA, the DAC module and the feedback module.
4. The multi-channel ultrasonic arbitrary waveform signal generator with feedback correction according to claim 1, wherein the channel control signal includes a channel number and a channel number m selected by a user, the frequency control signal is a frequency signal of an ultrasonic waveform to be transmitted set by the user, and the initial phase signal is an initial phase signal of the ultrasonic waveform to be transmitted set by the user.
5. The multi-channel ultrasonic wave arbitrary waveform signal generator with feedback correction according to claim 1, wherein the FPGA receives the channel control signal and the frequency control signal to generate a corresponding phase accumulator, the data output by the phase accumulator is sent to the corresponding m adders to be accumulated with the received initial phase signal, address information of each channel is obtained, and the amplitude signal corresponding to the phase is searched according to the address information in the corresponding waveform lookup table.
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| CN109814656B (en) * | 2018-12-28 | 2021-01-22 | 中电科仪器仪表有限公司 | Signal generation device and method for arbitrary waveform generator |
| CN110045017A (en) * | 2019-04-26 | 2019-07-23 | 中国计量大学 | The underwater ultrasound phased array fault detection system of wireless data transmission and method of detection |
| CN110234119B (en) * | 2019-06-06 | 2022-05-06 | 四川九洲电器集团有限责任公司 | Signal source generating system based on DAC chip |
| CN110333490B (en) * | 2019-07-30 | 2022-12-27 | 西安电子工程研究所 | Asynchronous multichannel arbitrary waveform generation method based on pipeline working mode |
| CN110380216B (en) * | 2019-07-30 | 2021-09-03 | 西安天和防务技术股份有限公司 | Phase configuration method, device, equipment and storage medium in phased array radar |
| CN110838843B (en) * | 2019-11-22 | 2022-08-02 | 中国电子科技集团公司第五十八研究所 | Anti-irradiation DDS circuit |
| CN111707975B (en) * | 2020-06-24 | 2022-09-02 | 中国电子科技集团公司第四十一研究所 | Radio frequency signal generation system and method suitable for helium optical pump magnetometer |
| CN113720222B (en) * | 2021-08-30 | 2023-06-16 | 山西宇翔信息技术有限公司 | Radio fuse, phase correction method thereof, platform and readable storage medium |
| CN114129920B (en) * | 2021-11-29 | 2023-09-26 | 中国医学科学院生物医学工程研究所 | Phased array ultrasonic transducer excitation system for improving accurate frequency |
| CN115033053A (en) * | 2022-03-03 | 2022-09-09 | 阿里巴巴达摩院(杭州)科技有限公司 | Signal processing method and storage medium |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101324825A (en) * | 1996-08-12 | 2008-12-17 | 蒂科电子公司 | Acoustic condition sensor employing many mutually non-orthogonal waves |
| CN102481139A (en) * | 2009-07-15 | 2012-05-30 | 美国国家半导体公司 | Sub-beam forming transmitter circuitry for ultrasound system |
| CN103713279A (en) * | 2014-01-07 | 2014-04-09 | 武汉大学 | Multi-channel synchronization excitation source system |
| CN107635470A (en) * | 2015-02-25 | 2018-01-26 | 决策科学医疗有限责任公司 | acoustic signal transmission connection and connection medium |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6901157B2 (en) * | 2001-01-15 | 2005-05-31 | Fuji Photo Film Co., Ltd. | Ultrasonic diagnostic apparatus |
-
2018
- 2018-07-06 CN CN201810741637.4A patent/CN108614271B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101324825A (en) * | 1996-08-12 | 2008-12-17 | 蒂科电子公司 | Acoustic condition sensor employing many mutually non-orthogonal waves |
| CN102481139A (en) * | 2009-07-15 | 2012-05-30 | 美国国家半导体公司 | Sub-beam forming transmitter circuitry for ultrasound system |
| CN103713279A (en) * | 2014-01-07 | 2014-04-09 | 武汉大学 | Multi-channel synchronization excitation source system |
| CN107635470A (en) * | 2015-02-25 | 2018-01-26 | 决策科学医疗有限责任公司 | acoustic signal transmission connection and connection medium |
Non-Patent Citations (2)
| Title |
|---|
| Enhancement of ultrasonic testing equipment time based resolution by synthetic waveform generator;Ohta, K. et al.;Proceedings of the 6th Symposium on Ultrasonic Electronics;全文 * |
| 一种用于超声检漏探头激励的任意波形发生器;綦磊;孙立臣;李征;;电子测量技术(08);全文 * |
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