CN108572892B - PowerPC multi-core processor-based offline test method and device - Google Patents

PowerPC multi-core processor-based offline test method and device Download PDF

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CN108572892B
CN108572892B CN201710151367.7A CN201710151367A CN108572892B CN 108572892 B CN108572892 B CN 108572892B CN 201710151367 A CN201710151367 A CN 201710151367A CN 108572892 B CN108572892 B CN 108572892B
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test
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target program
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test task
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CN108572892A (en
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李国静
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Datang Mobile Communications Equipment Co Ltd
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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/22Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2236Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors
    • G06F11/2242Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors in multi-processor systems, e.g. one processor becoming the test master
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/22Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2273Test methods
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/22Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26Functional testing
    • G06F11/261Functional testing by simulating additional hardware, e.g. fault simulation
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/22Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26Functional testing
    • G06F11/263Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers

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Abstract

The embodiment of the invention provides an offline testing method and device based on a PowerPC multi-core processor, wherein the method comprises the following steps: when the PowerPC multi-core processor is in the running state of a multi-core multi-process and needs to be tested off line, determining a target program to be tested; loading a test task for the target program; extracting a test case from the target program; executing the test case by adopting the simulation interface; when the test case is completely executed, the test task is finished and deleted, and the problems that in the prior art, when a specific failed test case is independently executed, compiling, linking and loading programs must be repeated, so that software compiling and loading are time-consuming, and a multi-core multi-thread time sequence cannot be simulated and tested are solved, so that the working efficiency of an embedded program system is improved in a multi-core multi-process architecture mode, and the completeness of testing and the reliability of testing are also guaranteed.

Description

PowerPC multi-core processor-based offline test method and device
Technical Field
The invention relates to the technical field of computers, in particular to an offline testing method based on a PowerPC multi-core processor and an offline testing device based on the PowerPC multi-core processor.
Background
With the rapid development of the embedded technology, the embedded processing demand is also rapidly increasing, and today with the rapid development of the integrated circuit technology, the performance of a single-core processor has been developed to a relatively high level, it is not enough to improve the real-time performance of a system by simply improving the performance of the single-core processor, a system architecture is developing towards the design direction of a multiprocessor, so as to solve the problems of too high complexity and insufficient computing capability of a single-processor system, and particularly, a CPU with a simplified instruction set architecture like a PowerPC multi-core processor is excellent in information processing technology in various fields, so that the CPU is favored by a great number of users.
At present, a processor based on PowerPC is applied to an embedded real-time communication system program platform in a large scale, and the processor is mainly characterized in that multi-core multi-process concurrent processing is adopted, so that the development of the embedded real-time communication system in the current stage is also adapted, the real-time performance of the embedded system is exerted to the maximum extent through multi-core multi-thread program task concurrent processing, and the purpose of millisecond-level or even microsecond-level real-time communication of the communication system is achieved.
As is known, in the process of program development, testing is a very important development link, and there are many methods for current program development and testing, most of which is unit testing or off-line testing, and generally only one PC (Personal Computer) or server with related program development tools is needed. Typically, such testing has a simulation process to simulate various external messages or trigger conditions of the program subsystem, compile linked runs, and observe or verify program run results.
According to the flow scheme of implementing the off-line test on the program by using the prior art, the test of the program is started, the stages of compiling, linking, loading, running and the like are required, if a plurality of cases are executed and a certain test case which does not pass is independently executed, the stages of compiling, linking, loading, running and the like are required to be re-executed, and for a complete embedded real-time program system, the code amount is generally larger, and the stages of compiling, linking, loading and the like which are executed once are likely to consume longer, so that the test time is prolonged, the labor input is increased, and finally the test efficiency is low.
Disclosure of Invention
In view of the above problems, embodiments of the present invention are provided to provide an offline testing method based on a PowerPC multi-core processor and an offline testing apparatus based on a PowerPC multi-core processor, which overcome or at least partially solve the above problems.
In order to solve the above problems, an embodiment of the present invention discloses an offline test based on a PowerPC multi-core processor, where the PowerPC multi-core processor has a simulation interface for completely simulating an external operating environment, and the method includes:
when the PowerPC multi-core processor is in the running state of a multi-core multi-process and needs to be tested off line, determining a target program to be tested;
loading a test task for the target program;
extracting a test case from the target program;
executing the test case by adopting the simulation interface;
and when the test case is completely executed, ending and deleting the test task.
Preferably, after the step of executing the test case by using the simulation interface, the method further includes:
acquiring a test report generated by executing the test case;
and judging whether the test case is completely executed according to the test report, and returning to the step of extracting the test case from the target program when the test case is not completely executed.
Preferably, the step of loading a test task for the target program comprises:
and loading the test task into the target program by reconfiguring the timed interrupt notification message of the test task, and starting the test task.
Preferably, the step of loading a test task for the target program further comprises:
acquiring a test script of the target program;
loading a test task on the target program by adopting the test script;
the step of ending and deleting the test task comprises:
ending the test task;
and deleting the test task from the target program by adopting the test script.
Preferably, the step of loading a test task for the target program further comprises:
acquiring a console command of the target program;
and loading a test task to the target program by adopting the console command.
The step of ending and deleting the test task comprises:
ending the test task;
and deleting the test task from the target program by adopting the console command.
In order to solve the above problems, an embodiment of the present invention discloses an offline testing device based on a PowerPC multi-core processor, where the PowerPC multi-core processor has a simulation interface for completely simulating an external operating environment, and the device includes a software code module and a testing module:
the software code module is used for determining a target program to be tested when the PowerPC multi-core processor is in the running state of a multi-core multi-process and needs to be tested off-line;
the test module comprises a test loading submodule, a test execution submodule and a test resetting submodule; wherein the content of the first and second substances,
the test loading submodule is used for loading a test task aiming at the target program;
the test execution submodule is used for extracting a test case from the target program and executing the test case by adopting the simulation interface;
and the test reset submodule is used for finishing and deleting the test task when the test case is completely executed.
Preferably, the test module further comprises:
the test report acquisition submodule is used for acquiring a test report generated by executing the test case;
the judgment submodule is used for judging whether the test case is executed completely according to the test report and calling the test reset submodule when the test case is executed completely; and returning to the test execution submodule when the test case is not completely executed.
Preferably, the test loading submodule includes:
and the test task starting unit is used for loading the test task into the target program and starting the test task by reconfiguring the timed interrupt notification message of the test task.
Preferably, the test loading submodule further includes:
a test script obtaining unit, configured to obtain a test script of the target program;
the first test task loading unit is used for loading a test task to the target program by adopting the test script;
the test reset sub-module comprises:
a first task ending unit, configured to end the test task;
and the first task deleting unit is used for deleting the test task from the target program by adopting the test script.
Preferably, the test loading submodule further includes:
a console command acquisition unit for acquiring a console command of the target program;
the second test task loading unit is used for loading a test task to the target program by adopting the console command;
the test reset sub-module comprises:
the second task ending unit is used for ending the test task;
and the second task deleting unit is used for deleting the test task from the target program by adopting the console command.
Compared with the prior art, the embodiment of the invention has the following advantages:
by applying the method of the embodiment of the invention, the test task is not loaded when the test is not needed, so that the formal code of the embedded program system is not influenced; when the test is needed, the test task is loaded, and the external interface is completely simulated, so that the formal program system code is unknown to the test, the test can be completely operated according to the existing multi-core multi-process architecture mode, the time sequence and the interface are completely consistent, and the completeness of the test is ensured. And when the test is finished, in the test resetting step, the test task is removed from the application, and the initial state of the program system is recovered, so that the formal code of the embedded program system is not influenced although the test process of the continuous steps is carried out.
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FIG. 1 is a block diagram of a prior art off-line program testing system
FIG. 2 is a flowchart illustrating steps of an embodiment of an offline testing method based on a PowerPC multi-core processor according to the present invention;
FIG. 3 is a block diagram of an embodiment of an offline testing apparatus based on a PowerPC multi-core processor according to the present invention.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
Referring to a schematic block diagram of a conventional program offline testing system shown in fig. 1, in the conventional program offline testing system, an offline test is generally performed as follows:
the interface adaptation unit 104 can make some interface adaptations to the simulation unit 101 and the verification unit 102 in a targeted manner according to the difference of the tested software code unit 103 so as to interface with the software formal code.
The simulation unit 101 simulates all external interfaces and inputs in the whole software running process, and simultaneously drives the test process to execute the offline test according to the sequence of starting a test program, compiling, linking, loading and running, loading the program, executing a case, detecting whether the test is finished, outputting a test report and finishing the test by using control means such as codes or scripts and the like.
The verification unit 102 verifies the processing result of the software code unit 103 at the end of the test.
The method has the defects that the method is not suitable for an embedded multi-core multi-process real-time program platform system, the time sequence of parallel processing of the multi-core multi-process program when the whole machine runs is not considered at all, the difference with the whole machine is large, codes which pass unit testing or offline testing are often used, various problems can occur during the whole machine integration testing, the method is not representative, and the reliability is not high. This is because the conventional off-line testing system needs to use some program development tools on the PC to perform off-line testing on formal program codes through the simulation and verification unit. However, these programs generally can only execute some procedures or commands sequentially, that is, the tested program code units must be program code modules or sub-modules executed in a certain sequence, for the current multi-core multi-process embedded program system, there are multiple concurrent program tasks on each core or process, there may be operations that affect each other such as a certain time sequence or cross access between each task module unit, and there inevitably exists a certain dependency relationship between each task module unit, so that the final overall program output result largely depends on the current execution time sequence and access sequence of each program module unit, and therefore, the program offline test system applying the prior art is not suitable for the multi-core multi-process embedded program system.
Meanwhile, in the existing scheme, the built test system, the simulation unit and the verification unit are carried out aiming at a specific program module or a specific sub-module, so that the test system is different along with different tested program codes, even if the interface adaptation unit is used for adaptation, the aim of not modifying the simulation and verification unit can be achieved, and the workload is artificially increased by the interface adaptation.
Compared with the whole machine integration environment, the operation environment of the existing program offline test model is greatly different, the processing time sequence and the interface are inconsistent, and various problems still exist in the whole machine integration test of codes passing through a series of offline tests.
Example one
Referring to fig. 2, a flowchart illustrating steps of an embodiment of an offline testing method based on a PowerPC multi-core processor according to the present invention is shown, which may specifically include the following steps:
step 201, when the PowerPC multi-core processor is in a multi-core multi-process running state and needs to be tested off-line, determining a target program to be tested;
in practical application, the embodiment of the invention can be applied to an embedded real-time communication system program platform for multi-core and multi-process concurrent processing, and the technology can relate to various fields such as communication, traffic, household appliances, medical treatment and the like.
In specific implementation, the embodiment of the invention can determine the target program to be tested when the PowerPC multi-core processor is in the running state of multi-core and multi-process and needs to be tested offline.
For example, in a computer equipped with a related program development tool, when the PowerPC multi-core processor is in a multi-core and multi-process running state, it is necessary to perform offline test on a program in the development process, and at this time, it is possible to determine a target program to be tested by acquiring API (Application Programming Interface) information of the target program.
Step 202, loading a test task aiming at the target program;
in a preferred embodiment of the present invention, the test task may be loaded into the target program by reconfiguring the timer interrupt notification message of the test task, and the test task is started.
For example, when the PowerPC multi-core processor is in the running state of a multi-core and multi-process, the timed interrupt notification message of the test task is reconfigured by a loading module in the processor, the test task is loaded, and the test task is notified to start the running mode.
In another preferred embodiment of the present invention, a test task may also be loaded for the target program by:
in the mode 1, the test script of the target program is obtained, and the test script is adopted to load the test task to the target program.
And 2, acquiring a console command of the target program, and loading a test task on the target program by using the console command.
Of course, it is feasible for those skilled in the art to load the test task on the target program in any one or more of the manners described above, and the present invention is not limited thereto.
Step 203, extracting a test case from the target program;
in a specific implementation, the embodiment of the present invention may extract a part of a target program as a test case of the target program according to an actual requirement, or may extract an entire code of a program to be tested as a test case of the target program.
Step 204, executing the test case by adopting the simulation interface;
in practical application, the embodiment of the invention can be additionally provided with a simulation interface for completely simulating an external operation environment, the simulation interface is adopted to execute the test case, and the induced target program still stays in the external operation environment, so that the target program code is invisible to test in the test process, and the test is completed under the condition of completely running a real program code flow and a real time sequence.
In a preferred embodiment of the present invention, the present invention may further obtain a test report generated by executing the test case in a test process, judge whether the test case is executed completely according to the test report, and return to the step of extracting the test case from the target program when a judgment result indicates that the test case is not executed completely; if the determination result is that the test case is completely executed, step 205 is executed.
In practical application, the embodiment of the invention can directly return to the step of extracting the test case from the target program when a certain test case fails to be tested in execution or a research and development worker wants to repeatedly execute any one or more test cases, and the off-line test process of the program is repeated without repeatedly compiling, linking and loading the program version.
For example, when the test case of a certain target program is completely executed, the generated test report shows that the case fails to be tested, or when a developer wishes to repeatedly execute any one or more test cases, a new case can be directly extracted from the target program, and an offline test can be executed on the new case.
And step 205, ending and deleting the test task when the test case is executed.
In a specific implementation, the embodiment of the present invention may delete the test task and restore the initial state of the program system by reconfiguring the timed interrupt notification message of the task.
In a preferred embodiment of the present invention, the test task may be ended and deleted as follows:
in the mode 1, the test script is adopted to delete the test task from the target program, and the test task is ended.
And 2, deleting the test task from the target program by adopting the console command, and finishing the test task.
Of course, it is feasible that one skilled in the art can end and delete the testing task in any one or more of the ways described above, and the invention is not limited thereto.
By applying the method of the embodiment of the invention in practical application, the tested target program can be recovered to the initial state when the test case of the tested target program is executed in the test; when the test case of the detected target program is not completely executed in the test, or when research personnel hope to repeatedly execute any one or more test cases, under the condition of aiming at a plurality of cases, no matter continuous execution or single execution, the method can directly return to the step of extracting the test case from the target program, and the program offline test flow is repeated without repeatedly compiling, linking and loading program versions, so that the test efficiency is improved; in addition, the embodiment of the invention can not load the test task when the test is not needed, thereby having no influence on formal codes of the embedded program system; when a test is needed, in the test loading step, a test task is loaded in a script or console mode, and an external interface is completely simulated, so that a formal program code to be tested is invisible to the test, and a test case of a target program completely runs a real program code flow and a real time sequence, so that a formal program system code of the target program is unknown to the test, the system code can completely run according to an existing multi-core multi-process architecture mode, and the time sequence and the interface are completely consistent; and then, when the test is finished, in the test resetting step, the test task can be deleted and the initial state of the program system can be recovered by using the embodiment of the invention in a mode of script or console, so that although the off-line test is carried out, the test process of the continuous steps is carried out, the formal codes of the embedded program system are not influenced, and the authenticity of the test result is improved.
It should be noted that, for simplicity of description, the method embodiments are described as a series of acts or combination of acts, but those skilled in the art will recognize that the present invention is not limited by the illustrated order of acts, as some steps may occur in other orders or concurrently in accordance with the embodiments of the present invention. Further, those skilled in the art will appreciate that the embodiments described in the specification are presently preferred and that no particular act is required to implement the invention.
Example two
Referring to fig. 3, a block diagram of an embodiment of the offline testing apparatus based on a PowerPC multi-core processor according to the present invention is shown, and specifically includes the following modules:
a software code module 301, configured to determine a target program to be tested when the PowerPC multi-core processor is in an operating state of a multi-core multi-process and needs to perform an offline test;
the test module 302, where the test module 302 may further include a test loading sub-module 3021, a test execution sub-module 3022, and a test resetting sub-module 3033; wherein the content of the first and second substances,
the test loading submodule 3021 is configured to load a test task for the target program;
the test execution submodule 3022 is configured to extract a test case from the target program, and execute the test case using the simulation interface;
the test reset submodule 3023 is configured to end and delete the test task when the test case is executed.
In a preferred embodiment of the present invention, the test module 302 may further include the following sub-modules:
the test report acquisition submodule is used for acquiring a test report generated by executing the test case;
the judgment submodule is used for judging whether the test case is executed completely according to the test report, and calling the test reset submodule 3023 when the test case is executed completely; and when the test case is not completely executed, returning to the test execution submodule 3022.
In a preferred embodiment of the present invention, the task test loading submodule 3021 may further include the following units:
and the test task starting unit is used for loading the test task into the target program and starting the test task by reconfiguring the timed interrupt notification message of the test task.
In a preferred embodiment of the present invention, the task test loading submodule 3021 may further include the following units:
a test script obtaining unit, configured to obtain a test script of the target program;
the first test task loading unit is used for loading a test task to the target program by adopting the test script;
a console command acquisition unit for acquiring a console command of the target program;
and the second test task loading unit is used for loading the test task to the target program by adopting the console command.
In a preferred embodiment of the present invention, the test reset sub-module 3023 may further include the following units:
a first task ending unit, configured to end the test task;
a first task deleting unit, configured to delete the test task from the target program using the test script;
a second task ending unit, configured to end and delete the test task, including:
ending the test task;
and the second task deleting unit is used for deleting the test task from the target program by adopting the console command.
By applying the embodiment of the invention in practical application, the loading of the test module can be avoided when the test is not needed, so that the formal code of the embedded program system is not influenced; when a test is needed, in the test loading step, a test loading submodule loads a test module in a script or console mode and completely simulates an external interface, so that formal program system codes are unknown to the test, the test case of an induced target program is considered to be still in a test external environment, the test loading submodule is operated completely according to the existing multi-core multi-process architecture mode, the time sequence and the interface are completely consistent, the authenticity of the test environment is improved, the accuracy of a test result is also improved, in the test resetting step when the test case of the target program is executed, the test resetting submodule is adopted to remove the test module in the script or console mode and recover the initial state of the program system, although the test process of the off-line test is subjected to continuous steps, but also has no influence on formal codes of the embedded program system, so that the simulation unit and the verification unit can be integrated in a formal embedded program system platform.
For the device embodiment, since it is basically similar to the method embodiment, the description is simple, and for the relevant points, refer to the partial description of the method embodiment.
The embodiments in the present specification are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, apparatus, or computer program product. Accordingly, embodiments of the invention can take the form of an entirely hardware embodiment, an entirely program embodiment, or an embodiment combining program and hardware aspects. Furthermore, embodiments of the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
Embodiments of the present invention are described with reference to flowchart illustrations and/or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing terminal to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing terminal to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing terminal to cause a series of operational steps to be performed on the computer or other programmable terminal to produce a computer implemented process such that the instructions which execute on the computer or other programmable terminal provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While preferred embodiments of the present invention have been described, additional variations and modifications of these embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the embodiments of the invention.
Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or terminal that comprises the element.
The offline method based on the PowerPC multi-core processor and the offline device based on the PowerPC multi-core processor provided by the invention are described in detail, specific examples are applied in the text to explain the principle and the implementation mode of the invention, and the description of the above embodiments is only used for helping to understand the method and the core idea of the invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.

Claims (10)

1. An off-line testing method based on a PowerPC multi-core processor, wherein the PowerPC multi-core processor is provided with a simulation interface for completely simulating an external operating environment, and the method comprises the following steps:
when the PowerPC multi-core processor is in the running state of a multi-core multi-process and needs to be tested off line, determining a target program to be tested;
loading a test task for the target program;
extracting a test case from the target program;
executing the test case by adopting the simulation interface;
when the test case is completely executed, ending and deleting the test task;
wherein the step of ending and deleting the test task comprises:
and deleting the test task from the target program through the timing interruption notification message of the reconfiguration test task, and ending the test task.
2. The method of claim 1, wherein after the step of executing the test case using the simulation interface, the method further comprises:
acquiring a test report generated by executing the test case;
and judging whether the test case is completely executed according to the test report, and returning to the step of extracting the test case from the target program when the test case is not completely executed.
3. The method of claim 1 or 2, wherein the step of loading a test task for the target program comprises:
and loading the test task into the target program by reconfiguring the timed interrupt notification message of the test task, and starting the test task.
4. The method of claim 3, wherein the step of loading a test task for the target program further comprises:
acquiring a test script of the target program;
loading a test task on the target program by adopting the test script;
the step of ending and deleting the test task comprises:
ending the test task;
and deleting the test task from the target program by adopting the test script.
5. The method of claim 3, wherein the step of loading a test task for the target program further comprises:
acquiring a console command of the target program;
loading a test task to the target program by adopting the console command;
the step of ending and deleting the test task comprises:
ending the test task;
and deleting the test task from the target program by adopting the console command.
6. An off-line testing device based on a PowerPC multi-core processor, the PowerPC multi-core processor is provided with a simulation interface for completely simulating an external operating environment, and the device comprises a software code module and a testing module:
the software code module is used for determining a target program to be tested when the PowerPC multi-core processor is in the running state of a multi-core multi-process and needs to be tested off-line;
the test module comprises a test loading submodule, a test execution submodule and a test resetting submodule; wherein the content of the first and second substances,
the test loading submodule is used for loading a test task aiming at the target program;
the test execution submodule is used for extracting a test case from the target program and executing the test case by adopting the simulation interface;
the test reset submodule is used for finishing and deleting the test task when the test case is completely executed; wherein the ending and deleting the test task includes deleting the test task from the target program and ending the test task by reconfiguring a timer interrupt notification message of the test task.
7. The apparatus of claim 6, wherein the test module further comprises:
the test report acquisition submodule is used for acquiring a test report generated by executing the test case;
the judgment submodule is used for judging whether the test case is executed completely according to the test report and calling the test reset submodule when the test case is executed completely; and returning to the test execution submodule when the test case is not completely executed.
8. The apparatus of claim 6 or 7, wherein the test loading submodule comprises:
and the test task starting unit is used for loading the test task into the target program and starting the test task by reconfiguring the timed interrupt notification message of the test task.
9. The apparatus of claim 8, wherein the test load submodule further comprises:
a test script obtaining unit, configured to obtain a test script of the target program;
the first test task loading unit is used for loading a test task to the target program by adopting the test script;
the test reset sub-module comprises:
a first task ending unit, configured to end the test task;
and the first task deleting unit is used for deleting the test task from the target program by adopting the test script.
10. The apparatus of claim 8, wherein the test load submodule further comprises:
a console command acquisition unit for acquiring a console command of the target program;
the second test task loading unit is used for loading a test task to the target program by adopting the console command;
the test reset sub-module comprises:
the second task ending unit is used for ending the test task;
and the second task deleting unit is used for deleting the test task from the target program by adopting the console command.
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1932776A (en) * 2006-09-29 2007-03-21 上海科泰世纪科技有限公司 Automatic operating method for interface test in embedded operating system
CN101385008A (en) * 2006-03-14 2009-03-11 英特尔公司 A common analog interface for multiple processor cores
CN102331961A (en) * 2011-09-13 2012-01-25 华为技术有限公司 Method, system and dispatcher for simulating multiple processors in parallel
CN102681941A (en) * 2012-05-15 2012-09-19 北京理工大学 Extensible embedded simulation test system
CN105279007A (en) * 2014-07-10 2016-01-27 龙芯中科技术有限公司 Multi-core processor simulation method and apparatus

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101385008A (en) * 2006-03-14 2009-03-11 英特尔公司 A common analog interface for multiple processor cores
CN1932776A (en) * 2006-09-29 2007-03-21 上海科泰世纪科技有限公司 Automatic operating method for interface test in embedded operating system
CN102331961A (en) * 2011-09-13 2012-01-25 华为技术有限公司 Method, system and dispatcher for simulating multiple processors in parallel
CN102681941A (en) * 2012-05-15 2012-09-19 北京理工大学 Extensible embedded simulation test system
CN105279007A (en) * 2014-07-10 2016-01-27 龙芯中科技术有限公司 Multi-core processor simulation method and apparatus

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