CN115034165A - Chip simulation verification method, system, equipment and storage medium - Google Patents
Chip simulation verification method, system, equipment and storage medium Download PDFInfo
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- CN115034165A CN115034165A CN202210747628.2A CN202210747628A CN115034165A CN 115034165 A CN115034165 A CN 115034165A CN 202210747628 A CN202210747628 A CN 202210747628A CN 115034165 A CN115034165 A CN 115034165A
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Abstract
The invention discloses a chip simulation verification method, which comprises the following steps: generating a library file; performing simulation verification on the library file by using an EDA tool; judging whether a bug appears in the simulation verification process; responding to the vulnerability, and determining a module with the vulnerability according to log information; performing simulation verification on the library file by using the EDA tool again and downloading a waveform file of the module with the vulnerability; and debugging the library file based on the log information and the waveform file. The invention also discloses a system, a computer device and a readable storage medium. The scheme provided by the invention can improve the simulation verification efficiency. By using the method, the time consumed in the simulation verification process and the occupation of hardware resources can be greatly reduced, and the effects of shortening the whole research and development period of the chip and reasonably utilizing the hardware resources are achieved.
Description
Technical Field
The invention relates to the field of chips, in particular to a method, a system, equipment and a storage medium for chip simulation verification.
Background
In the process of chip development, how to use a scientific method as the basis of the dump waveform file so as to achieve the method for saving hardware resources and development time. Because the design needs to be verified and checked repeatedly in the chip verification, especially in the early stage of the chip verification, the iteration is not stopped, the time of the dump waveform occupies more than 70% of the time and more than 80% of the hardware resources, the waveform dump needs to be repeated every debug, a large amount of time and a large amount of hardware resources are consumed, the time and the hardware resource occupation consumed in the process can be greatly reduced, and the effects of shortening the whole research and development period of the chip and reasonably utilizing the hardware resources are achieved. The feasibility of the scheme is verified by using the method in the actual verification process.
The prior art has the following defects:
1. each time of simulation verification of all the dump waveform files occupies more than 80 percent of hardware resources
2. Each simulation verification is finished only after the whole system is simulated, and the time is more than 70%.
Disclosure of Invention
In view of the above, in order to overcome at least one aspect of the above problems, an embodiment of the present invention provides a method for verifying chip simulation, including:
generating a library file;
performing simulation verification on the library file by using an EDA tool;
judging whether a bug occurs in the simulation verification process;
responding to the vulnerability, and determining a module with the vulnerability according to log information;
performing simulation verification on the library file by using the EDA tool again and downloading a waveform file of the module with the vulnerability;
and debugging the library file based on the log information and the waveform file.
In some embodiments, generating the library file further comprises:
and compiling the chip design code and the environment module by utilizing the EDA tool to obtain the library file.
In some embodiments, debugging the library file based on the log information and the waveform file further comprises:
modifying the chip design code and the environment module based on the log information and the waveform file;
and compiling and simulating and verifying the modified chip design codes and the environment module by using the EDA tool again until all bugs are eliminated.
In some embodiments, further comprising:
and directly ending the simulation verification in response to no vulnerability.
Based on the same inventive concept, according to another aspect of the present invention, an embodiment of the present invention further provides a chip simulation verification system, including:
a generation module configured to generate a library file;
a verification module configured to perform simulation verification on the library file using an EDA tool;
the judging module is configured to judge whether a bug occurs in the simulation verification process;
the determining module is configured to respond to the vulnerability and determine the vulnerability according to log information;
the downloading module is configured to perform simulation verification on the library file by using the EDA tool again and download a waveform file of the module with the vulnerability;
a debugging module configured to debug the library file based on the log information and the waveform file.
In some embodiments, the generation module is further configured to:
and compiling the chip design code and the environment module by utilizing the EDA tool to obtain the library file.
In some embodiments, the debug module is further configured to:
modifying the chip design code and the environment module based on the log information and the waveform file;
and compiling and simulating and verifying the modified chip design codes and the environment module by using the EDA tool again until all bugs are eliminated.
In some embodiments, the system further comprises a termination module configured to:
and directly ending the simulation verification in response to no vulnerability.
Based on the same inventive concept, according to another aspect of the present invention, an embodiment of the present invention further provides a computer apparatus, including:
at least one processor; and
a memory storing a computer program operable on the processor, wherein the processor executes the program to perform the steps of:
generating a library file;
performing simulation verification on the library file by using an EDA tool;
judging whether a bug occurs in the simulation verification process;
responding to the occurrence of the vulnerability, and determining a module of the vulnerability according to log information;
performing simulation verification on the library file by using the EDA tool again and downloading a waveform file of the module with the vulnerability;
and debugging the library file based on the log information and the waveform file.
In some embodiments, generating the library file further comprises:
and compiling the chip design code and the environment module by utilizing the EDA tool to obtain the library file.
In some embodiments, debugging the library file based on the log information and the waveform file further comprises:
modifying the chip design code and the environment module based on the log information and the waveform file;
and compiling and simulating verification are carried out on the modified chip design codes and the environment module by means of the EDA tool again until all bugs are eliminated.
In some embodiments, further comprising:
and directly ending the simulation verification in response to no vulnerability.
Based on the same inventive concept, according to another aspect of the present invention, an embodiment of the present invention further provides a computer-readable storage medium storing a computer program which, when executed by a processor, performs the steps of:
generating a library file;
performing simulation verification on the library file by using an EDA tool;
judging whether a bug occurs in the simulation verification process;
responding to the vulnerability, and determining a module with the vulnerability according to log information;
performing simulation verification on the library file by using the EDA tool again and downloading a waveform file of the module with the vulnerability;
and debugging the library file based on the log information and the waveform file.
In some embodiments, generating the library file further comprises:
and compiling the chip design code and the environment module by utilizing the EDA tool to obtain the library file.
In some embodiments, debugging the library file based on the log information and the waveform file further comprises:
modifying the chip design code and the environment module based on the log information and the waveform file;
and compiling and simulating and verifying the modified chip design codes and the environment module by using the EDA tool again until all bugs are eliminated.
In some embodiments, further comprising:
and directly ending the simulation verification in response to no vulnerability.
The invention has one of the following beneficial technical effects: the scheme provided by the invention can improve the simulation verification efficiency. By using the method, the time consumed in the simulation verification process and the occupation of hardware resources can be greatly reduced, and the effects of shortening the whole research and development period of the chip and reasonably utilizing the hardware resources are achieved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the prior art descriptions will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic flow chart of a chip simulation verification method according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a chip emulation verification system according to an embodiment of the present invention;
FIG. 3 is a schematic structural diagram of a computer device provided in an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a computer-readable storage medium according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.
It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two entities with the same name but different names or different parameters, and it should be noted that "first" and "second" are merely for convenience of description and should not be construed as limitations of the embodiments of the present invention, and they are not described in any more detail in the following embodiments.
According to an aspect of the present invention, an embodiment of the present invention provides a method for verifying chip simulation, as shown in fig. 1, which may include the steps of:
s1, generating a library file;
s2, performing simulation verification on the library file by using an EDA tool;
s3, judging whether a bug occurs in the simulation verification process;
s4, responding to the vulnerability, and determining a module with the vulnerability according to log information;
s5, performing simulation verification on the library file by using the EDA tool again and downloading a waveform file of the module with the vulnerability;
s6, debugging the library file based on the log information and the waveform file.
The scheme provided by the invention can improve the simulation verification efficiency. By using the method, the time consumed in the simulation verification process and the occupation of hardware resources can be greatly reduced, and the effects of shortening the whole research and development period of the chip and reasonably utilizing the hardware resources are achieved.
In some embodiments, generating the library file further comprises:
and compiling the chip design code and the environment module by utilizing the EDA tool to obtain the library file.
In some embodiments, debugging the library file based on the log information and the waveform file further comprises:
modifying the chip design code and the environment module based on the log information and the waveform file;
and compiling and simulating and verifying the modified chip design codes and the environment module by using the EDA tool again until all bugs are eliminated.
In some embodiments, further comprising:
and directly ending the simulation verification in response to no vulnerability.
In some embodiments, a chip verification environment is provided by the ENV module, codes are designed for the chip by the RTL module, the RTL and the ENV are compiled into library files by the EDA tool, whether a waveform is downloaded or not is controlled after simulation verification of the database module by the wavedump module is started for the EDA tool, and ENV and RTL repair information is stored for each simulation verification by the debug module. The waveform is stored through the Debug across dump module, a simulation verifier carries out Debug in the module, and after Debug is finished, the simulation verifier returns to the ENV module to carry out re-simulation verification iteration.
The invention mainly realizes a method for improving the simulation verification efficiency. And (3) establishing a verification platform by a verifier, placing the whole verification platform in the ENV module, compiling the RTL code of the chip design and the ENV module through an EDA tool, and then generating a whole verified database, wherein all simulation verification processes are carried out based on the database. When the EDA tool verifies the database module each time, the database module passes through the wavedump module, the wavedump module judges, if bugs are not found in the whole verification process, the operation of a no dump waveform is automatically carried out, and the simulation is finished; if the bug occurs in the verification process, the bug information is transmitted to a debug module for analysis, the debug information including but not limited to wave dump info (the information includes information that dump waveform needs to be carried out after the bug) is added to the error point after analysis, the information is submitted to a debug across dump module for re-simulation verification and dump, and after the bug is solved, the modified RTL and ENV information are fed back to an ENV module for iteration again. Until the bug is completely cleared.
As described above, the method has the advantages that whether a large number of hardware resources are needed to be spent on the dump process of the waveform can be judged in advance in each simulation verification, even if bugs occur, the waveform information of the dumps can be acquired through the debug module, and then only the waveforms of the dump related modules need to be debugged, so that the simulation verification time is greatly shortened, the simulation verification efficiency is improved, and particularly, in the early stage of the simulation verification, when the bugs are more, considerable time and resources can be saved through multiple iterations, and the effect of improving the efficiency is achieved. The specific implementation flow of the scheme is as follows:
1. judging dumpwave for compiled database, if there is no bug, ending the simulation verification process, and entering a finish module
2. Finding the bug, transmitting log information to the bug info module for analysis, determining an error module by a verifier through the process, and storing waveform information needing dump
3. Carrying out simulation again aiming at the saved information, and saving the log record and the required waveform to a debug across wave module
4. Modifying corresponding RTL and ENV by analyzing waveform and log, and iterating by retry after modification until no bug appears
The invention mainly realizes a method for improving the simulation verification efficiency. The method can greatly reduce the time consumed in the process and the occupation of hardware resources, and achieves the effects of shortening the whole research and development period of the chip and reasonably utilizing the hardware resources. The feasibility of the scheme is verified by using the method in the actual verification process.
Based on the same inventive concept, according to another aspect of the present invention, an embodiment of the present invention further provides a chip simulation verification system 400, as shown in fig. 2, including:
a generating module 401 configured to generate a library file;
a verification module 402 configured to perform simulation verification on the library file using an EDA tool;
a judging module 403 configured to judge whether a bug occurs in the simulation verification process;
a determining module 404 configured to, in response to the vulnerability occurring, determine a module in which the vulnerability occurs according to log information;
a downloading module 405 configured to perform simulation verification on the library file by using the EDA tool again and download a waveform file of a module in which the vulnerability occurs;
a debugging module 406 configured to debug the library file based on the log information and the waveform file.
In some embodiments, the generation module 401 is further configured to:
and compiling the chip design codes and the environment module by using the EDA tool to obtain the library file.
In some embodiments, debug module 406 is further configured to:
modifying the chip design code and the environment module based on the log information and the waveform file;
and compiling and simulating and verifying the modified chip design codes and the environment module by using the EDA tool again until all bugs are eliminated.
In some embodiments, the system further comprises an end module configured to:
and directly ending the simulation verification in response to no vulnerability.
Based on the same inventive concept, according to another aspect of the present invention, as shown in fig. 3, an embodiment of the present invention further provides a computer apparatus 501, comprising:
at least one processor 520; and
a memory 510, the memory 510 storing a computer program 511 executable on the processor, the processor 520 executing the program to perform the steps of:
s1, generating a library file;
s2, performing simulation verification on the library file by using an EDA tool;
s3, judging whether a bug occurs in the simulation verification process;
s4, responding to the vulnerability, and determining a module with the vulnerability according to log information;
s5, performing simulation verification on the library file by using the EDA tool again and downloading a waveform file of the module with the vulnerability;
s6, debugging the library file based on the log information and the waveform file.
In some embodiments, generating the library file further comprises:
and compiling the chip design code and the environment module by utilizing the EDA tool to obtain the library file.
In some embodiments, debugging the library file based on the log information and the waveform file further comprises:
modifying the chip design code and the environment module based on the log information and the waveform file;
and compiling and simulating and verifying the modified chip design codes and the environment module by using the EDA tool again until all bugs are eliminated.
In some embodiments, further comprising:
and directly ending the simulation verification in response to no vulnerability.
Based on the same inventive concept, according to another aspect of the present invention, as shown in fig. 4, an embodiment of the present invention further provides a computer-readable storage medium 601, the computer-readable storage medium 601 stores a computer program 610, and the computer program 610 performs the following steps when executed by a processor:
s1, generating a library file;
s2, performing simulation verification on the library file by using an EDA tool;
s3, judging whether a bug occurs in the simulation verification process;
s4, responding to the vulnerability, and determining a module with the vulnerability according to log information;
s5, performing simulation verification on the library file by using the EDA tool again and downloading a waveform file of the module with the vulnerability;
s6, debugging the library file based on the log information and the waveform file.
In some embodiments, generating the library file further comprises:
and compiling the chip design code and the environment module by utilizing the EDA tool to obtain the library file.
In some embodiments, debugging the library file based on the log information and the waveform file further comprises:
modifying the chip design code and the environment module based on the log information and the waveform file;
and compiling and simulating and verifying the modified chip design codes and the environment module by using the EDA tool again until all bugs are eliminated.
In some embodiments, further comprising:
and directly ending the simulation verification in response to no vulnerability.
Finally, it should be noted that, as will be understood by those skilled in the art, all or part of the processes of the methods of the above embodiments may be implemented by a computer program, which may be stored in a computer-readable storage medium, and when executed, may include the processes of the embodiments of the methods described above.
Further, it should be appreciated that the computer-readable storage media (e.g., memory) herein can be either volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory.
Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as software or hardware depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the disclosed embodiments of the present invention.
The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.
The numbers of the embodiments disclosed in the embodiments of the present invention are merely for description, and do not represent the merits of the embodiments.
It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.
Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to these examples; within the idea of an embodiment of the invention, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of the embodiments of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements and the like that may be made without departing from the spirit or scope of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.
Claims (10)
1. A chip simulation verification method is characterized by comprising the following steps:
generating a library file;
performing simulation verification on the library file by using an EDA tool;
judging whether a bug occurs in the simulation verification process;
responding to the occurrence of the vulnerability, and determining a module of the vulnerability according to log information;
performing simulation verification on the library file by using the EDA tool again and downloading a waveform file of the module with the vulnerability;
and debugging the library file based on the log information and the waveform file.
2. The method of claim 1, wherein generating a library file further comprises:
and compiling the chip design codes and the environment module by using the EDA tool to obtain the library file.
3. The method of claim 2, wherein debugging the library file based on the log information and the waveform file further comprises:
modifying the chip design code and the environment module based on the log information and the waveform file;
and compiling and simulating verification are carried out on the modified chip design codes and the environment module by means of the EDA tool again until all bugs are eliminated.
4. The method of claim 1, further comprising:
and directly ending the simulation verification in response to no vulnerability.
5. A system for chip emulation verification, comprising:
a generation module configured to generate a library file;
a verification module configured to perform simulation verification on the library file using an EDA tool;
the judging module is configured to judge whether a bug occurs in the simulation verification process;
the determining module is configured to respond to the vulnerability and determine the vulnerability according to log information;
the download module is configured to perform simulation verification on the library file by using the EDA tool again and download a waveform file of the module with the vulnerability;
and the debugging module is configured to debug the library file based on the log information and the waveform file.
6. The system of claim 5, wherein the generation module is further configured to:
and compiling the chip design code and the environment module by utilizing the EDA tool to obtain the library file.
7. The system of claim 6, wherein the debugging module is further configured to:
modifying the chip design code and the environment module based on the log information and the waveform file;
and compiling and simulating and verifying the modified chip design codes and the environment module by using the EDA tool again until all bugs are eliminated.
8. The system of claim 5, further comprising an end module configured to:
and directly ending the simulation verification in response to no vulnerability.
9. A computer device, comprising:
at least one processor; and
memory storing a computer program operable on the processor, characterized in that the processor executes the program to perform the steps of the method according to any of claims 1-4.
10. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, is adapted to carry out the steps of the method according to any one of claims 1-4.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117077588A (en) * | 2023-10-16 | 2023-11-17 | 沐曦集成电路(上海)有限公司 | Hardware acceleration simulation debugging system |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117077588A (en) * | 2023-10-16 | 2023-11-17 | 沐曦集成电路(上海)有限公司 | Hardware acceleration simulation debugging system |
| CN117077588B (en) * | 2023-10-16 | 2024-01-23 | 沐曦集成电路(上海)有限公司 | Hardware acceleration simulation debugging system |
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