CN108540258B - Cyclic redundancy code checking method and device - Google Patents

Cyclic redundancy code checking method and device Download PDF

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CN108540258B
CN108540258B CN201710116437.5A CN201710116437A CN108540258B CN 108540258 B CN108540258 B CN 108540258B CN 201710116437 A CN201710116437 A CN 201710116437A CN 108540258 B CN108540258 B CN 108540258B
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crc
code
cyclic redundancy
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code block
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CN108540258A (en
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吴昊
刘涛
许进
王芳
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ZTE Corp
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0061—Error detection codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0061—Error detection codes
    • H04L1/0063—Single parity check

Abstract

The embodiment of the invention provides a method and a device for checking a cyclic redundancy code, wherein the checking method comprises the following steps: calculating a Cyclic Redundancy Check (CRC) remainder of each code block through a cyclic redundancy check sequence, wherein the code blocks are obtained by decomposing each transmission block in the cyclic redundancy check; and combining the obtained CRC remainders of each code block, and judging the receiving condition of the transmission block according to a combination result. The method can perform parallel check of the cyclic redundancy code, and improves the speed and efficiency of cyclic redundancy code check processing.

Description

Cyclic redundancy code checking method and device
Technical Field
The invention belongs to the field of communication, and particularly relates to a cyclic redundancy code checking method and device.
Background
Cyclic Redundancy Check (CRC) uses the principle of division and remainder to detect errors. In practical applications, the transmitting device calculates the CRC result and sends it to the receiving device along with the data. The receiving device recalculates the CRC based on the received data and compares it with the received CRC to determine whether the received data has errors.
The CRC can be obtained by using the negotiated polynomial B when the transmitting end and the receiving end check. Assuming that the receiving sequence after adding the CRC is a, if the remainder of dividing a by B is zero, it indicates that the data is correctly received; if the remainder of dividing A by B is not zero, then the data is erroneously received.
Most CRC algorithms are serial processing, but the serial processing speed is slow, and due to memory limitations, the entire received sequence is sometimes not available and the processing efficiency is low.
Disclosure of Invention
In view of this, embodiments of the present invention provide a method and an apparatus for cyclic redundancy check, which solve the problems of slow processing speed and low efficiency of the existing cyclic redundancy check.
To solve the above problem, an aspect of the embodiments of the present invention provides a method for checking a cyclic redundancy code, including:
calculating a Cyclic Redundancy Check (CRC) remainder of each code block through a cyclic redundancy check sequence, wherein the code blocks are obtained by decomposing each transmission block in the cyclic redundancy check;
and combining the obtained CRC remainders of each code block, and judging the receiving condition of the transmission block according to a combination result.
Optionally, calculating a CRC remainder for each code block by the cyclic redundancy check sequence includes:
dividing the transmission block added with the cyclic redundancy check sequence into a plurality of code blocks;
checking each code block by using a check matrix;
and if the code block meets the judgment rule of the check matrix, calculating the CRC remainder of the code block by using the cyclic redundancy check sequence.
Optionally, the check matrix is a low density parity check code LDPC check matrix.
Optionally, the judgment rule is that the product of the code block and the check matrix is zero.
Optionally, the CRC remainders obtained for each code block are combined, and the calculation formula is:
Figure BDA0001235733040000021
wherein, CRC [ N ]]The remainder operation of N and CRC is expressed, the transmission block is divided into c code blocks, and the size of each code block is d0，d1，……，dc-1P is parallelism, the value range is 1 to c, c is a positive integer,
Figure BDA0001235733040000022
f＝c mod p；
i is a variable in the summation formula, Ai(x) Polynomial expression for the ith code block, in particular
Figure BDA0001235733040000023
j is a variable in the summation formula, djIs the size of the jth code block, ajIs the jth coefficient;
Tefor CRC remainder of transmission block, T is obtained by iterative calculatione-1(x) To T2(x) The calculation formula of (2) is as follows:
Figure BDA0001235733040000024
wherein n is an integer ranging from 2 to (e-1) and includes 2 and (e-1), Qm(x) Is calculated by the formula
Figure BDA0001235733040000025
T1(x) The calculation formula of (2) is as follows:
Figure BDA0001235733040000026
optionally, the determining the receiving condition of the transport block according to the combination result includes:
if T ise(x) And zero, the CRC passes, and the data of the transmission block is correctly received.
An embodiment of the present invention further provides a cyclic redundancy check apparatus, including:
a calculation module: calculating a Cyclic Redundancy Check (CRC) remainder of each code block through a cyclic redundancy check sequence, wherein the code blocks are obtained by decomposing each transmission block in the cyclic redundancy check;
a checking module: and the method is used for combining the obtained remainders of each code block and judging the receiving condition of the transmission block according to the combination result.
Optionally, the calculation module comprises:
a dividing unit: the system is used for dividing the transmission block added with the cyclic redundancy check sequence into a plurality of code blocks;
a checking unit: for checking each code block with a check matrix;
a remainder calculation unit: and if the code block meets the judgment rule of the check matrix, calculating the CRC remainder of the code block by using the cyclic redundancy check sequence.
Optionally, the check unit includes a comparing subunit, configured to determine whether a product of the code block and the check matrix is zero.
Optionally, the verification module comprises:
the first calculating subunit calculates the formula as:
Figure BDA0001235733040000031
wherein, TeObtaining the remainder of CRC of the transmission block through iterative calculation;
the second calculation subunit is used for iterative calculation, and the calculation formula is as follows:
Figure BDA0001235733040000032
wherein the value range of n is an integer between 2 and (e-1), including 2 and (e-1);
and the third calculation subunit calculates the formula as follows:
Figure BDA0001235733040000033
wherein, CRC [ N ]]The remainder operation of N and CRC is expressed, the transmission block is divided into c code blocks, and the size of each code block is d0，d1，……，dc-1P is parallelism, the value range is 1 to c, c is a positive integer,
Figure BDA0001235733040000034
f＝c mod p；
Qm(x) Is calculated by the formula
Figure BDA0001235733040000035
i is a variable in the summation formula, Ai(x) Polynomial expression for the ith code block, in particular
Figure BDA0001235733040000036
Figure BDA0001235733040000037
j is a variable in the summation formula, djIs the size of the jth code block, ajIs the jth coefficient.
Optionally, the checking module includes a judging subunit: for if Te(x) And zero, the CRC passes, and the data of the transmission block is correctly received.
In summary, in the embodiments of the present invention, the cyclic redundancy check sequence is used to calculate the remainder of each code block after decomposition of each transmission block in the cyclic redundancy check, and the reception condition of the transmission block is determined according to the combination result of the obtained remainder of each code block, so that parallel check of the cyclic redundancy check can be performed, and the CRC processing speed and the CRC processing efficiency are improved.
Drawings
FIG. 1 is a flowchart of a CRC method according to an embodiment of the present invention;
FIG. 2 is another flowchart of a CRC method according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a crc apparatus according to an embodiment of the present invention.
Detailed Description
In order to make the technical problems, technical solutions and advantages of the present invention more apparent, the following detailed description is given with reference to the accompanying drawings and specific embodiments.
First embodiment
Referring to fig. 1, a flowchart of a cyclic redundancy check method according to an embodiment of the present invention is shown, including the following steps:
s101, calculating a Cyclic Redundancy Check (CRC) remainder of each code block through a CRC sequence, wherein the code blocks are obtained by decomposing each transmission block in the CRC.
In this embodiment, each Transport Block (TB) in the cyclic redundancy Code Check is decomposed into a plurality of Code blocks (Code blocks, CBs), a Low Density Parity Check Code (LDPC) Check matrix is used to Check whether each CB Block satisfies a Check matrix, and when a CB Block satisfies the Check matrix, a cyclic redundancy Code Check sequence is used to calculate a remainder of each Code Block.
It should be noted that, in this embodiment, when one CB block satisfies the check matrix, the CRC remainder of the CB block is calculated.
The transport block TB is a basic Unit for Data exchange between a physical layer and a Media Access Control (MAC) sublayer in a Data link layer, and one transport block is a Data block including a Protocol Data Unit (MAC PDU).
The low density parity check code is a linear error correcting code which can be defined by a sparse check matrix, and the check matrix is sparse, so the low density parity check code is called low density parity check code, namely, the elements of the check matrix are mostly zero except for a small part which is not zero.
The judgment rule is that the product of the code block and the check matrix is zero; the crc is a check bit added after the transmission block, and is used to detect whether the transmitted data is transmitted in error during reception.
S102, combining the CRC remainders of the acquired code blocks, and judging the receiving condition of the transmission block according to the combination result.
In this embodiment, when each code block satisfies the check matrix, the CRC remainder of each code block can be obtained, the obtained CRC remainders of each code block are combined, and whether the transmission block is correctly received is determined, where the specific calculation formula is:
Figure BDA0001235733040000051
Teobtained by iterative calculation for the remainder of the CRC of a transport block, Te-1(x) To T2(x) Are all iterative intermediate terms, where Te-1(x)To T2(x) The calculation formula of (2) is as follows:
Figure BDA0001235733040000052
T1(x) The calculation formula of the first term of iteration is as follows:
Figure BDA0001235733040000053
wherein the value range of n is an integer between 2 and (e-1), including 2 and (e-1).
The iterative formula that can be obtained from the above equation is:
Figure BDA0001235733040000054
wherein, CRC [ N ]]The remainder operation of N and CRC sequence is expressed, the transmission block is divided into c code blocks, and the size of each code block is d0，d1，......，dc-1P is parallelism, the value range is 1 to c, c is a positive integer, the value of p is the balance of speed and storage,
Figure BDA0001235733040000055
f＝c mod p；
Qm(x) Is calculated by the formula
Figure BDA0001235733040000056
i is a variable in the summation formula, Ai(x) Polynomial expression for the ith code block, in particular
Figure BDA0001235733040000057
Figure BDA0001235733040000058
i is a variable in the summation formula, djIs the size of the jth code block, ajIs the jth coefficient.
In this example, the power xCRC calculation can be obtained by looking up a table when Te(x) And zero, the CRC passes, and the data of the transmission block is correctly received.
In summary, in the embodiment, the cyclic redundancy check CRC remainder of each code block decomposed by each transmission block in the cyclic redundancy check is calculated through the cyclic redundancy check sequence, and the reception condition of the transmission block is determined according to the combination result performed by the obtained CRC remainder of each code block, so that the parallel check of the cyclic redundancy can be performed, and the speed and efficiency of the cyclic redundancy check processing are improved.
Second embodiment
Referring to fig. 2, another flowchart of a cyclic redundancy check method according to an embodiment of the present invention is shown, which includes the following steps:
s201, dividing the transmission block added with the cyclic redundancy check sequence into a plurality of code blocks.
In this embodiment, it is assumed that the length of the transmission block TB after adding the cyclic redundancy check sequence is N, and the polynomial expression of the transmission block TB after adding the cyclic redundancy check sequence is:
Figure BDA0001235733040000061
wherein alpha isN-1Is MSB (Most Significant Bit), α0Is LSB (Least Significant Bit), i is a variable in the summation formula, aiIs the ith coefficient.
In this embodiment, the polynomial expression of the crc sequence is:
Figure BDA0001235733040000062
then it is obtained:
CRC[A(x)]＝A(x)xM modB(x)
wherein, CRC [ A (x)]I.e. remainder operation between A (x) and the CRC sequence, M is the length of the CRC sequence, i is the variable in the summation formula, biIs as followsi coefficients.
In this embodiment, the information bits of the transport block are divided into c code blocks, each having a size d0，d1，……dc-1Then, then
Figure BDA0001235733040000063
A (x) is represented by
Figure BDA0001235733040000064
i is a variable in the summation formula, where Ai(x) Polynomial expressions for i code blocks, in particular
Figure BDA0001235733040000065
Figure BDA0001235733040000066
j is a variable in the summation formula, djIs the size of the jth code block, ajIs the jth coefficient.
Then according to the above formula one can get:
Figure BDA0001235733040000071
namely:
Figure BDA0001235733040000072
in this embodiment, the CRC operation of the transport block may be calculated by performing CRC operation on each code block and x power after the blocking, and a specific calculation formula is as described above.
And S202, checking each code block by using the check matrix.
In this embodiment, the check matrix is a low density parity check code LDPC check matrix, where the low density parity check code LDPC is a linear error correction code that can be defined by a sparse check matrix, and the check matrix is sparse, so the check matrix is called low density, that is, elements of the check matrix are mostly zero except for a small part of the elements that are not zero.
In this embodiment, if the product of the coding result of the code block and the check matrix is zero, the code block satisfies the determination rule of the check matrix, and if the product is not zero, the code block data does not satisfy the determination rule of the check matrix.
S203, judging whether the code block meets the judgment rule of the check matrix, if so, entering the step S204; otherwise, the flow ends.
The method comprises the steps of judging whether code blocks all meet the judgment rule of a check matrix, if all the code blocks meet the check matrix, the transmission block possibly meets the cyclic redundancy code check, and if any one code block does not meet the judgment rule of the check matrix, the transmission block cannot meet the cyclic redundancy code check, the process is finished, and the following steps are not required.
And S204, calculating the CRC remainder of the code block by using the cyclic redundancy check sequence.
In this embodiment, when the code block satisfies the check matrix, the CRC remainder of the code block is calculated by using the CRC sequence to obtain CRC [ a ]i(x)]The CRC remainder for each code block can be finally obtained.
And S205, combining the CRC remainders of the acquired code blocks, and judging the receiving condition of the transmission block according to a combination result.
In this embodiment, when each code block satisfies the check matrix, the CRC remainder of each code block can be obtained, the obtained CRC remainders of each code block are combined, and whether the transmission block is correctly received is determined, where the specific calculation formula is:
Figure BDA0001235733040000081
wherein, TeObtained by iterative calculation for the remainder of the CRC of a transport block, Te-1(x) To T2(x) Are all iterative intermediate terms, Te-1(x) To T2(x) The calculation formula of (2) is as follows:
Figure BDA0001235733040000082
T1(x) The calculation formula of (c) is:
Figure BDA0001235733040000083
wherein, T1(x) For the first term of the iteration, the value of n ranges from 2 to (e-1) and includes 2 and (e-1).
A specific iterative formula can be obtained from the above equation:
Figure BDA0001235733040000084
wherein, CRC [ N ]]The remainder operation of N and CRC is expressed, the transmission block is divided into c code blocks, and the size of each code block is d0，d1，……，dc-1P is parallelism, the value range is 1 to c, c is a positive integer, the value of p is the balance of speed and storage,
Figure BDA0001235733040000085
f＝c mod p；
Qm(x) Is calculated by the formula
Figure BDA0001235733040000086
i is a variable in the summation formula, Ai(x) Polynomial expression for the ith code block, in particular
Figure BDA0001235733040000087
Figure BDA0001235733040000088
j is a variable in the summation formula, djIs the size of the jth code block, ajIs the jth coefficient.
In this embodiment, the CRC calculation of x powers can be obtained by table lookup, Te(x) Is CRC [ A (x)]When T ise(x) And zero, the CRC passes, and the data of the transmission block is correctly received.
In summary, in the embodiment, the transmission block to which the cyclic redundancy check sequence is added is divided into a plurality of code blocks, each code block is checked by using the check matrix, when the code block satisfies the check matrix, the cyclic redundancy check sequence is used to calculate the CRC remainder of the code block, and the reception condition of the transmission block is determined according to the obtained combination result of the CRC remainders of each code block, so that parallel check of the cyclic redundancy can be performed, and the speed and efficiency of cyclic redundancy check processing are improved.
Third embodiment
Based on the same inventive concept, the embodiment of the present invention further provides a cyclic redundancy code checking apparatus, and since the principle of the apparatus for solving the problem is similar to the cyclic redundancy code checking method in fig. 1 to fig. 2 in the embodiment of the present invention, the implementation of the apparatus can refer to the implementation of the method, and the repeated parts are not described again.
Referring to fig. 3, a schematic structural diagram of a cyclic redundancy check apparatus according to an embodiment of the present invention is shown, where the cyclic redundancy check apparatus includes:
the calculation module 301: calculating a Cyclic Redundancy Check (CRC) remainder of each code block through a cyclic redundancy check sequence, wherein the code blocks are obtained by decomposing each transmission block in the cyclic redundancy check;
the verification module 302: and the CRC residue processing module is used for combining the obtained CRC residues of each code block and judging the receiving condition of the transmission block according to the combination result.
In this embodiment, the calculating module 301 includes:
division unit 3011: the device is used for dividing the transmission block added with the cyclic redundancy check sequence into a plurality of code blocks;
verification unit 3012: for checking each code block with a check matrix;
remainder calculation unit 3013: and the CRC residue of the code block is calculated by using the CRC sequence if the code block meets the check matrix.
In this embodiment, the check unit 3012 includes a comparing subunit, configured to determine whether a product of the code block and the check matrix is equal to zero, where when the product of the code block and the check matrix is equal to zero, the code block meets a determination rule of the check matrix, and when the product of the code block and the check matrix is not zero, the code block does not meet the determination rule of the check matrix.
In this embodiment, the checking module 302 includes:
the first calculating subunit calculates the formula as:
Figure BDA0001235733040000101
wherein, TeObtaining the CRC remainder of the transmission block through iterative calculation;
the second calculation subunit is used for iterative calculation, and the calculation formula is as follows:
Figure BDA0001235733040000102
wherein the value range of n is an integer between 2 and (e-1), including 2 and (e-1);
and the third calculation subunit calculates the formula as follows:
Figure BDA0001235733040000103
wherein, the transmission block is divided into c code blocks, and the size of each code block is d0，d1，……，dc-1P is parallelism, and the value range is 1 to c,
Figure BDA0001235733040000104
f＝c mod p；
Qm(x) Is calculated by the formula
Figure BDA0001235733040000105
i is a variable in the summation formula, Ai(x) Polynomial expression for the ith code block, in particular
Figure BDA0001235733040000106
Figure BDA0001235733040000107
j is a variable in the summation formula, djIs the size of the jth code block, ajIs the jth coefficient.
In this embodiment, the checking module 302 includes a determining subunit for determining if T is greater than Te(x) And zero, the CRC passes, and the data of the transmission block is correctly received.
To sum up, in this embodiment, the calculation module calculates the CRC remainder of each code block decomposed by each transmission block in the cyclic redundancy check by using the cyclic redundancy check sequence, the check module combines the obtained CRC remainders of each code block, and determines the reception condition of the transmission block according to the combination result, so that parallel check of the cyclic redundancy can be performed, and the speed and efficiency of cyclic redundancy check processing are improved.
It should be appreciated that reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
In various embodiments of the present invention, it should be understood that the sequence numbers of the above-mentioned processes do not mean the execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.
In the several embodiments provided in the present application, it should be understood that the disclosed method and terminal can be implemented in other manners. For example, the above-described terminal embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, terminals or units, and may be in an electrical, mechanical or other form.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may be separately included, or two or more units may be integrated into one unit. The integrated unit can be realized in a form of hardware, or in a form of hardware plus a software functional unit.
The integrated unit implemented in the form of a software functional unit may be stored in a computer readable storage medium. The software functional unit is stored in a storage medium and includes several instructions to enable a computer device (which may be a personal computer, a server, or a network device) to execute part of the steps of the voice broadcasting method in the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a portable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other media capable of storing program codes.
While the foregoing is directed to the preferred embodiment of the present invention, it will be appreciated by those skilled in the art that various changes and modifications may be made therein without departing from the principles of the invention as set forth in the appended claims.

Claims (9)

1. A method for cyclic redundancy check, the method comprising:
calculating a Cyclic Redundancy Check (CRC) remainder of each code block through a cyclic redundancy check sequence, wherein the code blocks are obtained after each transmission block is decomposed in the cyclic redundancy check;
combining the obtained CRC remainders of each code block, and judging the receiving condition of the transmission block according to a combination result;
combining the obtained CRC remainder of each code block, wherein a calculation formula is as follows:
Figure FDA0003562236550000011
wherein, CRC [ N ]]The remainder operation of N and CRC is expressed, the transmission block is divided into c code blocks, and the size of each code block is d0，d1，......dc-1C is a positive integer; p is parallelism and ranges from 1 to c;
Figure FDA0003562236550000016
f ═ c mod p; i is a variable in the summation formula, Ai(x) Polynomial expression for the ith code block, in particular
Figure FDA0003562236550000012
j is a variable in the summation formula, djIs the size of the jth code block, ajIs the jth coefficient;
Teobtained by iterative calculation for the CRC remainder of the transport block, Te-1(x) To T2(x) The calculation formula of (2) is as follows:
Figure FDA0003562236550000013
T1(x) The calculation formula of (2) is as follows:
Figure FDA0003562236550000014
wherein Q isk(x) Is calculated by the formula
Figure FDA0003562236550000015
The value range of n is an integer between 2 and (e-1), including 2 and (e-1).
2. The method of cyclic redundancy check according to claim 1, wherein the calculating the CRC remainder for each code block by a cyclic redundancy check sequence comprises:
dividing the transmission block added with the cyclic redundancy check sequence into a plurality of code blocks;
checking each code block by using a check matrix;
and if the code block meets the judgment rule of the check matrix, calculating the CRC remainder of the code block by using the cyclic redundancy check sequence.
3. A method of cyclic redundancy code checking according to claim 2, wherein the check matrix is a low density parity check code, LDPC, check matrix.
4. The method of claim 3, wherein the determination rule is that the product of the code block and the check matrix is zero.
5. The method as claimed in claim 4, wherein said determining the reception of the transport block according to the combination result comprises:
if Te(x) The CRC check passes with zero and the data of the transport block is correctly received.
6. A cyclic redundancy code checking apparatus, comprising:
a calculation module: the CRC remainder of each code block is calculated through the CRC sequence, wherein the code blocks are obtained after each transmission block is decomposed in the CRC;
a checking module: the CRC residue of each code block is obtained according to the CRC residue of each code block;
wherein the verification module comprises:
the first calculating subunit calculates the formula as:
Figure FDA0003562236550000021
wherein, TeObtaining the CRC remainder of the transmission block through iterative calculation;
the second calculation subunit is used for iterative calculation, and the calculation formula is as follows:
Figure FDA0003562236550000022
wherein the value range of n is an integer between 2 and (e-1), including 2 and (e-1);
and the third calculation subunit calculates the formula as follows:
Figure FDA0003562236550000023
wherein, CRC [ N ]]The remainder operation of N and CRC sequence is expressed, the transmission block is divided into c code blocks, and the size of each code block is d0，d1，......dc-1C is a positive integer, p is parallelism, and the value range is 1 to c,
Figure FDA0003562236550000025
f＝c mod p；
Qk(x) Is calculated by the formula
Figure FDA0003562236550000024
i is a variable in the summation formula, Ai(x) Polynomial expression for the ith code block, in particular
Figure FDA0003562236550000031
Figure FDA0003562236550000032
j is a variable in the summation formula, djIs the size of the jth code block, ajIs the jth coefficient.
7. The cyclic redundancy code verification apparatus of claim 6, wherein the calculation module comprises:
a dividing unit: the device is used for dividing the transmission block added with the cyclic redundancy check sequence into a plurality of code blocks;
a checking unit: for checking each code block with a check matrix;
a remainder calculation unit: and if the code block meets the judgment rule of the check matrix, calculating the CRC remainder of the code block by using the cyclic redundancy check sequence.
8. The crc apparatus of claim 7, wherein the checking unit comprises a comparing subunit configured to determine whether a product of the code block and the check matrix is zero.
9. The cyclic redundancy code verification apparatus of claim 8, wherein the verification module comprises a judgment subunit: for if Te(x) And zero, the CRC passes, and the data of the transmission block is correctly received.
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Publication number Priority date Publication date Assignee Title
CN110995394A (en) * 2019-11-30 2020-04-10 国网辽宁省电力有限公司锦州供电公司 Two-dimensional CRC (Cyclic redundancy check) method for data information

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1798014A (en) * 2004-12-20 2006-07-05 华为技术有限公司 Method for fixing frame through cyclic redundancy code
CN101383618A (en) * 2007-09-05 2009-03-11 中兴通讯股份有限公司 Encoding method for cyclic redundancy check code of transmission block
CN101689864A (en) * 2007-07-12 2010-03-31 三星电子株式会社 Methods and apparatus to compute CRC for multiple code blocks in a communication system
CN103378941A (en) * 2012-04-24 2013-10-30 马维尔国际有限公司 Cyclic redundancy checking method and modle for wireless communication system

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2004001701A1 (en) * 2002-06-20 2005-10-20 株式会社日立製作所 Sign arithmetic unit
EP2026470A1 (en) * 2007-08-17 2009-02-18 Panasonic Corporation Running cyclic redundancy check over coding segments
US8555148B2 (en) * 2007-09-18 2013-10-08 Samsung Electronics Co., Ltd. Methods and apparatus to generate multiple CRCs
CN102484484B (en) * 2009-08-25 2014-08-20 富士通株式会社 Transmitter, encoding device, receiver, and decoding device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1798014A (en) * 2004-12-20 2006-07-05 华为技术有限公司 Method for fixing frame through cyclic redundancy code
CN101689864A (en) * 2007-07-12 2010-03-31 三星电子株式会社 Methods and apparatus to compute CRC for multiple code blocks in a communication system
CN101383618A (en) * 2007-09-05 2009-03-11 中兴通讯股份有限公司 Encoding method for cyclic redundancy check code of transmission block
CN103378941A (en) * 2012-04-24 2013-10-30 马维尔国际有限公司 Cyclic redundancy checking method and modle for wireless communication system

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
"LTE-A系统中的turbo编码及其并行译码研究与实现";吴昌强;《中国优秀硕士学位论文全文数据库 信息科技辑》;20140115;全文 *
"R1-167901 Consideration on channel coding";ZTE;《3GPP tsg_ran\WG1_RL1》;20160820;全文 *

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