CN107239362B - Parallel CRC (Cyclic redundancy check) code calculation method and system - Google Patents

Parallel CRC (Cyclic redundancy check) code calculation method and system Download PDF

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CN107239362B
CN107239362B CN201710128854.1A CN201710128854A CN107239362B CN 107239362 B CN107239362 B CN 107239362B CN 201710128854 A CN201710128854 A CN 201710128854A CN 107239362 B CN107239362 B CN 107239362B
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梁利平
王志君
张笑铭
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Institute of Microelectronics of CAS
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Abstract

The application discloses a method and a system for calculating parallel CRC (cyclic redundancy check) codes, wherein the method for calculating the parallel CRC codes adopts a parameterized method, and realizes the purposes of changing parallelism and generating polynomials as required so as to improve the portability of the method for calculating the parallel CRC codes, and the parallel CRC codes adopt shift operation and XOR operation to solve the high power of a matrix in the traditional method for calculating the parallel CRC codes, thereby reducing the operation amount and reducing the calculation time by about 75% in comparison with direct calculation on an algorithm layer.

Description

Parallel CRC (Cyclic redundancy check) code calculation method and system
The present application claims priority of chinese patent application with the title "a method and system for calculating parallel CRC check code" filed by chinese patent office on 20/2/2017 with application number 201710089849.4, the entire contents of which are incorporated herein by reference.
Technical Field
The present application relates to the field of communications technologies, and in particular, to a method and a system for computing parallel CRC check codes.
Background
In data communication, in order to solve the problem of error detection in data communication, a check code with a certain number of bits is generally added after an information code to be transmitted to implement an error detection process. Among the numerous checking methods, Cyclic Redundancy Check (CRC) checking is widely used in the field of data communication technology due to its excellent error detection capability.
The basic idea of the CRC check is to attach a binary sequence CRC check code after the information code to be transmitted, generate a new information code and transmit the new information code to the receiving end. The CRC check code is required to be able to divide the generated new information code by a certain number selected by the transmitting end and the receiving end, the certain number is determined by a generator polynomial for generating the CRC check code, after the new information code arrives at the receiving end, the receiving end divides the received new information code by the certain number by "modulo-2 division", and if the result has no remainder, it indicates that the new information code has no error, and if the result has a remainder, it indicates that the information code has an error in the transmission process.
The calculation of the CRC is divided into a serial mode and a parallel mode, and the calculation method of the serial CRC can only calculate one bit of data to be generated each time; the parallel CRC code calculation method has a parallelism parameter, and can calculate the data to be generated with the parallelism bit number each time. In an actual application process, in order to improve the calculation efficiency, a parallel CRC check code calculation method is generally adopted to calculate the CRC check code. However, in the prior art, the calculation method of the parallel CRC check code is usually a table lookup method, that is, a specific check code table is generated according to a specific parallelism to perform table lookup, and this method needs to generate a new check code when the parallelism changes, so that the portability is low, and the parallelism and the generator polynomial cannot be changed as required.
Disclosure of Invention
In order to solve the technical problem, the invention provides a method and a system for calculating a parallel CRC code, so as to achieve the purpose of improving the portability of the method for calculating the parallel CRC code.
In order to achieve the technical purpose, the embodiment of the invention provides the following technical scheme:
a parallel CRC code calculation method is used for calculating data to be generated as dk-1dk-2dk-3…d0]The parallel CRC check code calculation method includes:
s101: obtaining a generator polynomial poly ═ pn-1pn-2pn-3…p0]And a degree of parallelism w;
s102: generating a first temporary matrix temp using the generator polynomial;
Figure GDA0002449828710000021
wherein the content of the first and second substances,
Figure GDA0002449828710000022
Figure GDA0002449828710000023
Figure GDA0002449828710000024
…
Figure GDA0002449828710000025
s103: generating a second temporary matrix using the generator polynomial
Figure GDA0002449828710000031
S104: generating an intermediate coefficient vector by using the first w bits of unprocessed data in the data to be generated
Figure GDA0002449828710000032
S105: and operating the intermediate coefficient vector and the first temporary matrix according to columns to obtain a first intermediate matrix
Figure GDA0002449828710000033
S106: sequentially carrying out reduction XOR operation on the column vectors of the first intermediate matrix according to columns to obtain a second intermediate matrix factor fn-1fn-2fn-3…f0]；
S107: performing AND operation on the second intermediate matrix and the column vectors in the second temporary matrix in a bit-by-bit sequence to obtain a third intermediate matrix
Figure GDA0002449828710000041
S108: the third intermediate momentPerforming bitwise XOR operation on all the columns of the array to obtain a check vector
Figure GDA0002449828710000042
Judging whether unprocessed data in the data to be generated is zero or not, and if yes, taking the check vector as a CRC (cyclic redundancy check) code of the data to be generated; and if not, updating the front n rows of the intermediate coefficient vector by using the check vector, updating the rear w rows of the intermediate coefficient vector by using the front w bits of unprocessed data in the data to be generated, and returning to the step of performing AND operation on the intermediate coefficient vector and the first temporary matrix according to columns to obtain a first intermediate matrix.
Optionally, step S108 includes:
performing bitwise XOR operation on all columns of the third intermediate matrix to obtain a check vector
Figure GDA0002449828710000043
Judging whether unprocessed data in the data to be generated is zero or not, and if yes, taking the check vector as a CRC (cyclic redundancy check) code of the data to be generated; if not, judging whether the number of bits of unprocessed data in the data to be generated is smaller than or equal to the parallelism, if not, returning to the step of performing AND operation on the intermediate coefficient vector and the first temporary matrix in a row to obtain a first intermediate matrix, if so, correcting the intermediate coefficient vector by using the unprocessed data in the data to be generated and the check vector, and returning to the step of performing AND operation on the intermediate coefficient vector and the first temporary matrix in a row to obtain the first intermediate matrix.
Optionally, the modifying the intermediate coefficient vector by using the unprocessed data in the data to be generated and the check vector includes:
giving the unprocessed data in the data to be generated to the last M rows of the intermediate coefficient vector in a reverse order, wherein the value of M is the same as the digit of the unprocessed data in the data to be generated;
assigning data in the check vector to lines from the reciprocal M +1 to the reciprocal M + n of the intermediate coefficient vector;
the first w-M rows of the intermediate coefficient vector are filled with zeros.
Optionally, the obtaining generates a polynomial poly ═ pn-1pn-2pn-3…p0]And after the parallelism w, before the generating the first temporary matrix temp by using the generator polynomial, the method further includes:
s1012: judging whether the obtained parallelism is greater than the sum of the number of the data bits to be generated and the number of the generating polynomial bits, if so, taking the sum of the number of the data bits to be generated and the number of the generating polynomial bits as the parallelism; if not, judging whether the acquired parallelism is less than 1, and if so, taking 1 as the parallelism.
A parallel CRC code calculation system is used for calculating data to be generated as dk-1dk-2dk-3…d0]The computation system of the parallel CRC check code comprises:
an obtaining module for obtaining a generator polynomial poly ═ pn-1pn-2pn-3…p0]And a degree of parallelism w;
a first temporary matrix generation module, configured to generate a first temporary matrix temp using the generator polynomial;
Figure GDA0002449828710000061
wherein the content of the first and second substances,
Figure GDA0002449828710000062
Figure GDA0002449828710000063
Figure GDA0002449828710000064
…
Figure GDA0002449828710000065
a second temporary matrix generation module for generating a second temporary matrix using the generator polynomial
Figure GDA0002449828710000066
An intermediate coefficient vector generating module, configured to generate an intermediate coefficient vector using the first w bits of unprocessed data in the data to be generated
Figure GDA0002449828710000071
A first intermediate matrix generation module, configured to perform an and operation on the intermediate coefficient vector and the first temporary matrix in rows to obtain a first intermediate matrix
Figure GDA0002449828710000072
A second intermediate matrix generation module, configured to perform reduction xor operation on the column vectors of the first intermediate matrix in sequence according to columns to obtain a second intermediate matrix factor [ f ]n-1fn-2fn-3…f0]；
A third intermediate matrix generation module, configured to perform bitwise and operation on the second intermediate matrix and the column vectors in the second temporary matrix in sequence to obtain a third intermediate matrix
Figure GDA0002449828710000073
A check vector generating module for performing bitwise XOR operation on all columns of the third intermediate matrix to obtain a check vector
Figure GDA0002449828710000081
Judging whether unprocessed data in the data to be generated is zero or not, and if yes, taking the check vector as a CRC (cyclic redundancy check) code of the data to be generated; if not, updating the middle node by using the check vectorAnd updating the last w rows of the intermediate coefficient vector by using the first w bits of unprocessed data in the data to be generated in the first n rows of the intermediate coefficient vector, and returning the updated w rows to the first intermediate matrix generation module.
Optionally, the check vector generation module is specifically configured to perform bitwise xor operation on all columns of the third intermediate matrix to obtain a check vector
Figure GDA0002449828710000082
Judging whether unprocessed data in the data to be generated is zero or not, and if yes, taking the check vector as a CRC (cyclic redundancy check) code of the data to be generated; if not, judging whether the number of bits of unprocessed data in the data to be generated is less than or equal to the parallelism, if not, returning to the first intermediate matrix generation module, if so, correcting the intermediate coefficient vector by using the unprocessed data in the data to be generated and the check vector, and returning to the first intermediate matrix generation module.
Optionally, the check vector generation module corrects the intermediate coefficient vector by using the unprocessed data in the data to be generated and the check vector, specifically, the correction is used for giving the unprocessed data in the data to be generated to the last M rows of the intermediate coefficient vector in a reverse order, and a value of M is the same as a bit number of the unprocessed data in the data to be generated;
assigning data in the check vector to lines from the reciprocal M +1 to the reciprocal M + n of the intermediate coefficient vector;
the first w-M rows of the intermediate coefficient vector are filled with zeros.
Optionally, the method further includes:
the parallelism correcting module is used for judging whether the obtained parallelism is greater than the sum of the number of the data bits to be generated and the number of the generating polynomial bits, and if so, taking the sum of the number of the data bits to be generated and the number of the generating polynomial bits as the parallelism; if not, judging whether the acquired parallelism is less than 1, and if so, taking 1 as the parallelism.
It can be seen from the foregoing technical solutions that the embodiments of the present invention provide a method and a system for calculating a parallel CRC check code, where the method for calculating a parallel CRC check code uses a parameterized method, and achieves the purpose of changing parallelism and generating a polynomial as needed, thereby improving portability of the method for calculating a parallel CRC check code, and the parallel CRC check code uses shift operation and xor operation to provide a solution of a high power of a matrix in a conventional method for calculating a parallel CRC check code, thereby reducing an amount of operation and reducing a calculation time by about 75% on an algorithm level compared with direct calculation.
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In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a schematic flowchart of a method for calculating a parallel CRC check code according to an embodiment of the present application;
fig. 2 is a schematic structural diagram of a computing system for parallel CRC check codes according to an embodiment of the present application;
fig. 3 is a schematic structural diagram of a parallel CRC check code computing system according to another embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
An embodiment of the present application provides a method for calculating a parallel CRC check code, as shown in fig. 1, where the method is used to calculate data to be generated as [ d ═ dk-1dk-2dk-3…d0]The parallel CRC check code calculation method includes:
s101: obtaining a generator polynomial poly ═ pn-1pn-2pn-3…p0]And a degree of parallelism w;
s102: generating a first temporary matrix temp using the generator polynomial;
Figure GDA0002449828710000101
wherein the content of the first and second substances,
Figure GDA0002449828710000102
Figure GDA0002449828710000103
Figure GDA0002449828710000104
…
Figure GDA0002449828710000105
specifically, the first temporary matrix generation method is to set the first value on the left of the last row to 1, and the values after this row are the high (n-1) bits of the generator polynomial (i.e., the binary representation of the first n-1 coefficients of the generator polynomial); the generation method of other rows of the first temporary matrix comprises the following steps: the first bit on the left of the next row (for example, for the second last row, the next row is the first last row) is bitwise anded with the high (n-1) bit of the generator polynomial, and the result is bitwise xored with the n-1 bit data of the next row except the first bit on the left, so that the result is n-1 bits of data from the left of the row, and the rightmost bit of data of the row is the leftmost bit of data of the next row of data of the row.
S103: generating a second temporary matrix using the generator polynomial
Figure GDA0002449828710000111
S104: generating an intermediate coefficient vector by using the first w bits of unprocessed data in the data to be generated
Figure GDA0002449828710000112
S105: and operating the intermediate coefficient vector and the first temporary matrix according to columns to obtain a first intermediate matrix
Figure GDA0002449828710000121
Figure GDA0002449828710000122
Figure GDA0002449828710000123
…
It should be noted that, in the first intermediate matrix,
Figure GDA0002449828710000124
s106: sequentially carrying out reduction XOR operation on the column vectors of the first intermediate matrix according to columns to obtain a second intermediate matrix factor fn-1fn-2fn-3…f0]；
It should be noted that, in the second intermediate matrix,
Figure GDA0002449828710000131
Figure GDA0002449828710000132
…
Figure GDA0002449828710000133
s107: performing AND operation on the second intermediate matrix and the column vectors in the second temporary matrix in a bit-by-bit sequence to obtain a third intermediate matrix
Figure GDA0002449828710000134
S108: performing bitwise XOR operation on all columns of the third intermediate matrix to obtain a check vector
Figure GDA0002449828710000135
Judging whether unprocessed data in the data to be generated is zero or not, and if yes, taking the check vector as a CRC (cyclic redundancy check) code of the data to be generated; and if not, updating the front n rows of the intermediate coefficient vector by using the check vector, updating the rear w rows of the intermediate coefficient vector by using the front w bits of unprocessed data in the data to be generated, and returning to the step of performing AND operation on the intermediate coefficient vector and the first temporary matrix according to columns to obtain a first intermediate matrix.
In the check-up vector,
Figure GDA0002449828710000141
based on the above embodiments, in one embodiment of the present application, the obtaining generates polynomial poly ═ pn-1pn-2pn-3…p0]And after the parallelism w, before the generating the first temporary matrix temp by using the generator polynomial, the method further includes:
s1012: judging whether the obtained parallelism is greater than the sum of the number of the data bits to be generated and the number of the generating polynomial bits, if so, taking the sum of the number of the data bits to be generated and the number of the generating polynomial bits as the parallelism; if not, judging whether the acquired parallelism is less than 1, and if so, taking 1 as the parallelism.
In the present embodiment, the purpose of adding step S1012 is to correct the abnormal parallelism of the input to avoid the error caused by the abnormal parallelism.
On the basis of the above embodiment, in a preferred embodiment of the present application, step S108 includes:
performing bitwise XOR operation on all columns of the third intermediate matrix to obtain a check vector
Figure GDA0002449828710000142
Judging whether unprocessed data in the data to be generated is zero or not, and if yes, taking the check vector as a CRC (cyclic redundancy check) code of the data to be generated; if not, judging whether the number of bits of unprocessed data in the data to be generated is smaller than or equal to the parallelism, if not, returning to the step of performing AND operation on the intermediate coefficient vector and the first temporary matrix in a row to obtain a first intermediate matrix, if so, correcting the intermediate coefficient vector by using the unprocessed data in the data to be generated and the check vector, and returning to the step of performing AND operation on the intermediate coefficient vector and the first temporary matrix in a row to obtain the first intermediate matrix.
Specifically, the modifying the intermediate coefficient vector by using the unprocessed data in the data to be generated and the check vector includes:
giving the unprocessed data in the data to be generated to the last M rows of the intermediate coefficient vector in a reverse order, wherein the value of M is the same as the digit of the unprocessed data in the data to be generated;
assigning data in the check vector to lines from the reciprocal M +1 to the reciprocal M + n of the intermediate coefficient vector;
the first w-M rows of the intermediate coefficient vector are filled with zeros.
Note that, the form of the intermediate coefficient vector after correction is shown as follows:
Figure GDA0002449828710000151
the third intermediate matrix obtained in the last operation process is shown as follows:
Figure GDA0002449828710000161
the check vector obtained in the last operation process is shown as follows:
Figure GDA0002449828710000162
wherein the content of the first and second substances,
Figure GDA0002449828710000163
based on the foregoing embodiment, in a specific embodiment of the present application, taking data 1011001 to be generated with a bit length of 7 as an example, a calculation method of the parallel CRC check code is examined, and it is assumed that a generated polynomial is g (x) ═ x4+x3+1, corresponding to a binary code of 1001 (omitting the most significant bit 1), really calculates 10110010000 (complementing the generator polynomial bit number 0 after the data to be generated). To characterize the method, a parallelism 7 is chosen that cannot be divided exactly, so it needs to be computed twice (7 bits of data to be generated, 4 bits of generator polynomial, their sum divided by the parallelism 7, the result rounded up to 2).
The first calculation 10110010000 (complementary to the generator polynomial bit number 0 after 1011001) has the upper 7 bits:
(1) the first temporary matrix temp is generated, and the last row of the matrix is the highest position 1 after the polynomial correspondence code 1001 is shifted right by one bit, and the result is 1100. The most significant bit of the penultimate behavior 1100 is ANDed with the generator polynomial to result in 1001, which is bitwise XOR' ed with the first three bits of the result 1001 shifted one bit circularly to the left of 1100 to result in 0001. The highest bit of 0001 in the third to last row is ANDed with the generator polynomial, resulting in 0000, which is bitwise XORed with the first three bits of 0010, which is a result of 0001 being shifted one bit to the left in a cyclic manner, resulting in 0010. And so on until a matrix of 11 rows and 4 columns is obtained:
Figure GDA0002449828710000171
(2) constructing a second temporary matrix
Figure GDA0002449828710000172
(3) Constructing an intermediate coefficient vector h, wherein the first 4 lines are 0 at the beginning, and the last 7 lines are the high 7 bits of data to be generated:
Figure GDA0002449828710000173
(4) and h and temp by column, yielding qand:
Figure GDA0002449828710000181
(5) the column vectors of qand are sequentially subjected to reduction xor, and 4 result values are obtained, and the factor is obtained [1011 ].
(6) And each bit of the factor and each column of the F are sequentially subjected to the AND operation to obtain
Figure GDA0002449828710000182
(7) Performing bitwise XOR on all columns of the sand to obtain a column vector
Figure GDA0002449828710000183
Is the calculation of the first 7 bits CRC of data 10110010000 (complementary to the generator polynomial bit number 0 after 1011001).
The lower 4 bits of the second calculation data 10110010000 (after 1011001 the complement of the generator polynomial bit number 0):
(8) modifying h, assigning the rest data to be calculated CRC code in the data to be generated to the last rows of the column vector, and then calculating the intermediate CRC result in the previous step
Figure GDA0002449828710000184
The row added to it, the last starting row is filled with zeros.
Figure GDA0002449828710000191
(9) And the h and temp are anded by row to generate qand.
Figure GDA0002449828710000192
(10) Reducing the column vectors of qand in sequence, and performing exclusive or to obtain 4 result values, to obtain: factor ═ 0101%
(11) And each bit of the factor and each column of F are sequentially subjected to AND operation to obtain
Figure GDA0002449828710000193
(12) Bitwise exclusive-or of all the columns of sand yields the final CRC calculation for a column vector that is data 10110010000 (after 1011001 the complement of the generator polynomial bits is 0):
Figure GDA0002449828710000194
the final calculation result is 1010, that is, the CRC check code of the data to be generated 1011001, and this value is substituted for the last 40 s of the data 10110010000 (after 1011001, the number of bits of the generator polynomial is complemented by 0), so that 10110011010 is obtained, the first seven bits are the information code, and the last four bits are the CRC check code.
Correspondingly, an embodiment of the present application further provides a computing system of a parallel CRC check code, as shown in fig. 2, configured to compute data to be generated as [ d ═ dk-1dk-2dk-3…d0]The computation system of the parallel CRC check code comprises:
an obtaining module 100 for obtaining a generator polynomial poly ═ pn-1pn-2pn-3…p0]And a degree of parallelism w;
a first temporary matrix generating module 200, configured to generate a first temporary matrix temp using the generator polynomial;
Figure GDA0002449828710000201
wherein the content of the first and second substances,
Figure GDA0002449828710000202
Figure GDA0002449828710000203
Figure GDA0002449828710000204
…
Figure GDA0002449828710000205
a second temporary matrix generation module 300 for generating a second temporary matrix using the generator polynomial
Figure GDA0002449828710000206
An intermediate coefficient vector generating module 400, configured to generate an intermediate coefficient vector by using the first w bits of unprocessed data in the data to be generated
Figure GDA0002449828710000211
A first intermediate matrix generation module 500, configured to perform an and operation on the intermediate coefficient vector and the first temporary matrix in rows to obtain a first intermediate matrix
Figure GDA0002449828710000212
A second intermediate matrix generating module 600, configured to perform reduction xor operation on the column vectors of the first intermediate matrix in sequence according to columns to obtain a second intermediate matrix factor ═ fn-1fn-2fn-3…f0]；
A third intermediate matrix generating module 700, configured to perform bitwise and operation on the second intermediate matrix and the column vectors in the second temporary matrix in sequence to obtain a third intermediate matrix
Figure GDA0002449828710000213
A check vector generating module 800, configured to perform bitwise xor operation on all columns of the third intermediate matrix to obtain a check vector
Figure GDA0002449828710000221
Judging whether unprocessed data in the data to be generated is zero or not, and if yes, taking the check vector as a CRC (cyclic redundancy check) code of the data to be generated; if not, the first n rows of the intermediate coefficient vector are updated by using the check vector, the last w rows of the intermediate coefficient vector are updated by using the first w bits of unprocessed data in the data to be generated, and the data is returned to the first intermediate matrix generation module 500.
It should be noted that, the first temporary matrix generation method is to set the first value on the left of the last row to 1, and the values after the row are the high (n-1) bits of the generator polynomial (i.e. the binary representation of the first n-1 coefficients of the generator polynomial); the generation method of other rows of the first temporary matrix comprises the following steps: the first bit on the left of the next row (for example, for the second last row, the next row is the first last row) is bitwise anded with the high (n-1) bit of the generator polynomial, and the result is bitwise xored with the n-1 bit data of the next row except the first bit on the left, so that the result is n-1 bits of data from the left of the row, and the rightmost bit of data of the row is the leftmost bit of data of the next row of data of the row.
Figure GDA0002449828710000231
Figure GDA0002449828710000232
…
In the first intermediate matrix, the first intermediate matrix is,
Figure GDA0002449828710000233
in the second intermediate matrix, the first intermediate matrix is,
Figure GDA0002449828710000234
Figure GDA0002449828710000235
…
Figure GDA0002449828710000236
in the check-up vector,
Figure GDA0002449828710000241
on the basis of the foregoing embodiment, in an embodiment of the present application, as shown in fig. 3, the calculation system of the CRC check code further includes:
a parallelism correcting module 900, configured to determine whether the obtained parallelism is greater than the sum of the number of bits of the data to be generated and the number of bits of the generator polynomial, and if so, take the sum of the number of bits of the data to be generated and the number of bits of the generator polynomial as the parallelism; if not, judging whether the acquired parallelism is less than 1, and if so, taking 1 as the parallelism.
In this embodiment, the purpose of adding the parallelism correcting module 900 is to correct the parallelism of the input abnormality, so as to avoid errors possibly caused by the acquired parallelism abnormality.
Based on the foregoing embodiment, in a preferred embodiment of the present application, the check vector generation module 800 is specifically configured to perform a bitwise xor operation on all columns of the third intermediate matrix to obtain a check vector
Figure GDA0002449828710000242
Judging whether unprocessed data in the data to be generated is zero or not, and if yes, determining that the unprocessed data is zeroThe check vector is used as a CRC check code of the data to be generated; if not, judging whether the number of bits of unprocessed data in the data to be generated is less than or equal to the parallelism, if not, returning to the first intermediate matrix generation module 500, if so, correcting the intermediate coefficient vector by using the unprocessed data in the data to be generated and the check vector, and returning to the first intermediate matrix generation module 500.
Specifically, the check vector generation module 800 corrects the intermediate coefficient vector by using the unprocessed data in the data to be generated and the check vector, specifically, the correction is used to assign the unprocessed data in the data to be generated to the last M rows of the intermediate coefficient vector in a reverse order, where a value of M is the same as a bit number of the unprocessed data in the data to be generated;
assigning data in the check vector to lines from the reciprocal M +1 to the reciprocal M + n of the intermediate coefficient vector;
the first w-M rows of the intermediate coefficient vector are filled with zeros.
Note that, the form of the intermediate coefficient vector after correction is shown as follows:
Figure GDA0002449828710000251
the third intermediate matrix obtained in the last operation process is shown as follows:
Figure GDA0002449828710000261
the check vector obtained in the last operation process is shown as follows:
Figure GDA0002449828710000262
wherein the content of the first and second substances,
Figure GDA0002449828710000263
on the basis of the above-mentioned embodiments, in a concrete implementation of the present applicationIn the embodiment, taking data to be generated 1011001 with a bit length of 7 as an example, the calculation system of the parallel CRC check code is checked, and it is assumed that a generator polynomial g (x) is x4+x3+1, corresponding to a binary code of 1001 (omitting the most significant bit 1), really calculates 10110010000 (complementing the generator polynomial bit number 0 after the data to be generated). To characterize the method, a parallelism 7 is chosen that cannot be divided exactly, so it needs to be computed twice (7 bits of data to be generated, 4 bits of generator polynomial, their sum divided by the parallelism 7, the result rounded up to 2).
The first calculation 10110010000 (complementary to the generator polynomial bit number 0 after 1011001) has the upper 7 bits:
(1) the first temporary matrix temp is generated, and the last row of the matrix is the highest position 1 after the polynomial correspondence code 1001 is shifted right by one bit, and the result is 1100. The most significant bit of the penultimate behavior 1100 is ANDed with the generator polynomial to result in 1001, which is bitwise XOR' ed with the first three bits of the result 1001 shifted one bit circularly to the left of 1100 to result in 0001. The highest bit of 0001 in the third to last row is ANDed with the generator polynomial, resulting in 0000, which is bitwise XORed with the first three bits of 0010, which is a result of 0001 being shifted one bit to the left in a cyclic manner, resulting in 0010. And so on until a matrix of 11 rows and 4 columns is obtained:
Figure GDA0002449828710000271
(2) constructing a second temporary matrix
Figure GDA0002449828710000272
(3) Constructing an intermediate coefficient vector h, wherein the first 4 lines are 0 at the beginning, and the last 7 lines are the high 7 bits of data to be generated:
Figure GDA0002449828710000273
(4) and h and temp by column, yielding qand:
Figure GDA0002449828710000281
(5) the column vectors of qand are sequentially subjected to reduction xor, and 4 result values are obtained, and the factor is obtained [1011 ].
(6) And each bit of the factor and each column of the F are sequentially subjected to the AND operation to obtain
Figure GDA0002449828710000282
(7) Performing bitwise XOR on all columns of the sand to obtain a column vector
Figure GDA0002449828710000283
Is the calculation of the first 7 bits CRC of data 10110010000 (complementary to the generator polynomial bit number 0 after 1011001).
The lower 4 bits of the second calculation data 10110010000 (after 1011001 the complement of the generator polynomial bit number 0):
(8) modifying h, assigning the rest data to be calculated CRC code in the data to be generated to the last rows of the column vector, and then calculating the intermediate CRC result in the previous step
Figure GDA0002449828710000284
The row added to it, the last starting row is filled with zeros.
Figure GDA0002449828710000291
(9) And the h and temp are anded by row to generate qand.
Figure GDA0002449828710000292
(10) Reducing the column vectors of qand in sequence, and performing exclusive or to obtain 4 result values, to obtain: factor ═ 0101%
(11) And each bit of the factor and each column of F are sequentially subjected to AND operation to obtain
Figure GDA0002449828710000293
(12) Bitwise exclusive-or of all the columns of sand yields the final CRC calculation for a column vector that is data 10110010000 (after 1011001 the complement of the generator polynomial bits is 0):
Figure GDA0002449828710000294
the final calculation result is 1010, that is, the CRC check code of the data to be generated 1011001, and this value is substituted for the last 40 s of the data 10110010000 (after 1011001, the number of bits of the generator polynomial is complemented by 0), so that 10110011010 is obtained, the first seven bits are the information code, and the last four bits are the CRC check code.
In summary, the embodiments of the present application provide a method and a system for calculating a parallel CRC check code, where the method for calculating the parallel CRC check code uses a parameterized method, and achieves the purpose of changing parallelism and generating a polynomial according to needs, thereby improving the portability of the method for calculating the parallel CRC check code, and the parallel CRC check code uses shift operation and xor operation to solve the high power of a matrix in a conventional method for calculating the parallel CRC check code, thereby reducing the amount of operation and reducing the calculation time by about 75% in comparison with direct calculation at an algorithm level.
Further, the parallel CRC check code calculation method provided by the embodiment of the application can realize the generation and the check of the CRC check code with any parallelism, and eliminates the specific limitation of the parallelism.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (8)

1. A parallel CRC code calculation method is characterized in that the method is used for calculating data to be generated as dk-1dk-2dk-3… d0]The parallel CRC check code calculation method includes:
s101: obtaining a generator polynomial poly ═ pn-1pn-2pn-3… p0]And a degree of parallelism w;
s102: generating a first temporary matrix temp using the generator polynomial;
Figure FDA0001239348570000011
wherein the content of the first and second substances,
Figure FDA0001239348570000012
s103: generating a second temporary matrix using the generator polynomial
Figure FDA0001239348570000013
S104: generating an intermediate coefficient vector by using the first w bits of unprocessed data in the data to be generated
Figure FDA0001239348570000021
S105: and operating the intermediate coefficient vector and the first temporary matrix according to columns to obtain a first intermediate matrix
Figure FDA0001239348570000022
S106: sequentially carrying out reduction XOR operation on the column vectors of the first intermediate matrix according to columns to obtain a second intermediate matrix factor fn-1fn-2fn-3… f0]；
S107: bitwise sequentially connecting the second intermediate matrix with the first intermediate matrixThe column vectors in the two temporary matrixes are ANDed to obtain a third intermediate matrix
Figure FDA0001239348570000023
S108: performing bitwise XOR operation on all columns of the third intermediate matrix to obtain a check vector
Figure FDA0001239348570000031
Judging whether unprocessed data in the data to be generated is zero or not, and if yes, taking the check vector as a CRC (cyclic redundancy check) code of the data to be generated; and if not, updating the front n rows of the intermediate coefficient vector by using the check vector, updating the rear w rows of the intermediate coefficient vector by using the front w bits of unprocessed data in the data to be generated, and returning to the step of performing AND operation on the intermediate coefficient vector and the first temporary matrix according to columns to obtain a first intermediate matrix.
2. The method of claim 1, wherein step S108 comprises:
performing bitwise XOR operation on all columns of the third intermediate matrix to obtain a check vector
Figure FDA0001239348570000032
Judging whether unprocessed data in the data to be generated is zero or not, and if yes, taking the check vector as a CRC (cyclic redundancy check) code of the data to be generated; if not, judging whether the number of bits of unprocessed data in the data to be generated is smaller than or equal to the parallelism, if not, returning to the step of performing AND operation on the intermediate coefficient vector and the first temporary matrix in a row to obtain a first intermediate matrix, if so, correcting the intermediate coefficient vector by using the unprocessed data in the data to be generated and the check vector, and returning to the step of performing AND operation on the intermediate coefficient vector and the first temporary matrix in a row to obtain the first intermediate matrix.
3. The method according to claim 2, wherein the modifying the intermediate coefficient vector using the unprocessed data of the data to be generated and the check vector comprises:
giving the unprocessed data in the data to be generated to the last M rows of the intermediate coefficient vector in a reverse order, wherein the value of M is the same as the digit of the unprocessed data in the data to be generated;
assigning data in the check vector to lines from the reciprocal M +1 to the reciprocal M + n of the intermediate coefficient vector;
the first w-M rows of the intermediate coefficient vector are filled with zeros.
4. The method of claim 1, wherein the obtaining a generator polynomial poly ═ pn-1pn-2pn-3… p0]And after the parallelism w, before the generating the first temporary matrix temp by using the generator polynomial, the method further includes:
s1012: judging whether the obtained parallelism is greater than the sum of the number of the data bits to be generated and the number of the generating polynomial bits, if so, taking the sum of the number of the data bits to be generated and the number of the generating polynomial bits as the parallelism; if not, judging whether the acquired parallelism is less than 1, and if so, taking 1 as the parallelism.
5. A parallel CRC check code calculation system is characterized in that the parallel CRC check code calculation system is used for calculating data to be generated as dk-1dk-2dk-3… d0]The computation system of the parallel CRC check code comprises:
an obtaining module for obtaining a generator polynomial poly ═ pn-1pn-2pn-3… p0]And a degree of parallelism w;
a first temporary matrix generation module, configured to generate a first temporary matrix temp using the generator polynomial;
Figure FDA0001239348570000051
wherein the content of the first and second substances,
Figure FDA0001239348570000052
a second temporary matrix generation module for generating a second temporary matrix using the generator polynomial
Figure FDA0001239348570000053
An intermediate coefficient vector generating module, configured to generate an intermediate coefficient vector using the first w bits of unprocessed data in the data to be generated
Figure FDA0001239348570000061
A first intermediate matrix generation module, configured to perform an and operation on the intermediate coefficient vector and the first temporary matrix in rows to obtain a first intermediate matrix
Figure FDA0001239348570000062
A second intermediate matrix generation module, configured to perform reduction xor operation on the column vectors of the first intermediate matrix in sequence according to columns to obtain a second intermediate matrix factor [ f ]n-1fn-2fn-3… f0]；
A third intermediate matrix generation module, configured to perform bitwise and operation on the second intermediate matrix and the column vectors in the second temporary matrix in sequence to obtain a third intermediate matrix
Figure FDA0001239348570000063
A check vector generating module for performing bitwise XOR operation on all columns of the third intermediate matrix to obtain a check vector
Figure FDA0001239348570000071
Judging whether unprocessed data in the data to be generated is zero or not, and if yes, taking the check vector as the data to be generatedA CRC check code for the data; if not, updating the front n rows of the intermediate coefficient vector by using the check vector, updating the rear w rows of the intermediate coefficient vector by using the front w bits of unprocessed data in the data to be generated, and returning to the first intermediate matrix generation module.
6. The system of claim 5, wherein the check vector generation module is specifically configured to perform a bitwise XOR operation on all columns of the third intermediate matrix to obtain a check vector
Figure FDA0001239348570000072
Judging whether unprocessed data in the data to be generated is zero or not, and if yes, taking the check vector as a CRC (cyclic redundancy check) code of the data to be generated; if not, judging whether the number of bits of unprocessed data in the data to be generated is less than or equal to the parallelism, if not, returning to the first intermediate matrix generation module, if so, correcting the intermediate coefficient vector by using the unprocessed data in the data to be generated and the check vector, and returning to the first intermediate matrix generation module.
7. The system according to claim 6, wherein the check vector generation module modifies the intermediate coefficient vector by using unprocessed data in the data to be generated and the check vector, specifically, to assign an inverted order of the unprocessed data in the data to be generated to a last M rows of the intermediate coefficient vector, where a value of M is the same as a bit number of the unprocessed data in the data to be generated;
assigning data in the check vector to lines from the reciprocal M +1 to the reciprocal M + n of the intermediate coefficient vector;
the first w-M rows of the intermediate coefficient vector are filled with zeros.
8. The system of claim 5, further comprising:
the parallelism correcting module is used for judging whether the obtained parallelism is greater than the sum of the number of the data bits to be generated and the number of the generating polynomial bits, and if so, taking the sum of the number of the data bits to be generated and the number of the generating polynomial bits as the parallelism; if not, judging whether the acquired parallelism is less than 1, and if so, taking 1 as the parallelism.
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