CN108268676B - Verification method and device for pin multiplexing - Google Patents
Verification method and device for pin multiplexing Download PDFInfo
- Publication number
- CN108268676B CN108268676B CN201611261750.XA CN201611261750A CN108268676B CN 108268676 B CN108268676 B CN 108268676B CN 201611261750 A CN201611261750 A CN 201611261750A CN 108268676 B CN108268676 B CN 108268676B
- Authority
- CN
- China
- Prior art keywords
- module
- pin
- function
- name
- functional
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/333—Design for testability [DFT], e.g. scan chain or built-in self-test [BIST]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention relates to the technical field of integrated circuits, and discloses a method and a device for verifying pin multiplexing. The pin multiplexing verification method is used for carrying out pin multiplexing verification on an integrated circuit chip, the integrated circuit chip comprises a pin multiplexing module and at least one functional module, a pin multiplexing design table is generated according to a preset rule, the preset rule defines that the pin multiplexing design table comprises a pin name of the pin multiplexing module, a functional name and a functional direction of the at least one functional module, and the functional name comprises a name of the functional module and a signal name connected with the pin multiplexing module; running a script tool according to the pin name, the function name and the function direction to form a connection file for representing signal connection between the pin and at least one function module; signals between the pins and at least one functional module in the connection file are verified by adding excitation according to the function direction, verification information and excitation do not need to be manually filled, and the multiplexing verification time of the pins can be shortened.
Description
Technical Field
The present invention relates to the field of integrated circuit technologies, and in particular, to a method and an apparatus for verifying pin multiplexing.
Background
At present, the flow of verifying a pin multiplexing (muxpin) module is divided into three parts, firstly, a pin multiplexing design table is converted into a muxpin verification table, according to the verification requirement, each verification function mode (case) needs an independent verification table, and the related information of the pin multiplexing design table is sequentially filled into the verification tables. Second, since the muxpin pin in each case needs to be connected to the corresponding pin inside the module, and the pin multiplexing in the normal function (normal) mode needs to be connected to 4 different modules, possibly corresponding to the input or output of the module, or corresponding to the input and output enable three signals at the same time, the path of the corresponding module signal and the signal name corresponding to the module should be filled in the verification table, and the function selection signal, direction, initial value, etc. also need to be filled in the pin multiplexing design table. Thirdly, generating corresponding verification cases for the verification tables by the scripts in sequence.
However, in the process of implementing the invention, the inventor finds that: the existing muxpin has 224 pins and 16 functional modes, each functional mode needs to fill corresponding information of each pin in a verification table, wherein in the conventional functional mode, 4 functions can be selected from one pin, corresponding to 4 different signals, and each pin multiplexing signal simultaneously corresponds to three signals of input, output and enable in an internal module. A lot of repeated work is done when the verification table is filled in, which is very tedious.
The general pin multiplexing verification only verifies an output pin of a pin multiplexing module, signals from the output pin of the pin multiplexing module to a functional module need to be verified additionally, if internal signals need to be verified, the signals multiplexed by the pins need to be connected to the signals of the functional module, but in the design process, a plurality of signal names need to be modified in different degrees, so that the signal names of the functional module cannot be completely corresponding to the signal names of the functional module; and the signal names of some intellectual property core (IP core) modules cannot correspond to the signal names of the pin multiplexing design. It takes a lot of time to look up these signals and their corresponding names when filling out the verification table.
In addition, if there is signal modification in the verification process, a large number of verification table modifications are involved, and the corresponding signal of each functional mode needs to be modified and then verified again, so that unnecessary errors are easily caused.
Disclosure of Invention
The embodiment of the invention aims to provide a method and a device for verifying pin multiplexing, which do not need to fill verification information and excitation artificially and can reduce the pin multiplexing verification time.
In order to solve the above technical problem, an embodiment of the present invention provides a pin multiplexing verification method for performing pin multiplexing verification on an integrated circuit chip, where the integrated circuit chip includes a pin multiplexing module and at least one functional module, and includes: generating a pin multiplexing design table according to a preset rule, wherein the preset rule defines that the pin multiplexing design table comprises a pin name of a pin multiplexing module, a function name realized by at least one function module and a corresponding function direction, and the function name comprises a name of the function module and a signal name connected with the pin multiplexing module; running a script tool according to the pin name, the function name and the function direction to form a connection file for representing the connection of the signal between the pin and at least one function module; and verifying the connection of the signal between the pin and the at least one functional module in the connection file according to the added excitation of the functional direction.
The embodiment of the present invention further provides a pin multiplexing verification apparatus, which is used for performing pin multiplexing verification on an integrated circuit chip, where the integrated circuit chip includes a pin multiplexing module and at least one functional module, and includes: the table establishing module is used for generating a pin multiplexing design table according to a preset rule, wherein the preset rule defines that the pin multiplexing design table comprises a pin name of the pin multiplexing module, a function name realized by at least one function module and a corresponding function direction, and the function name comprises a name of the function module and a signal name connected with the pin multiplexing module; the connection generation module is connected with the table establishment module and used for running a script tool according to the pin name, the function name and the function direction to form a connection file for representing the connection of signals between the pin and at least one function module; and the verification module is connected with the connection generation module and used for verifying the connection of the signal between the pin and the at least one functional module in the connection file according to the added excitation of the functional direction.
Compared with the prior art, the method and the device have the advantages that the pin multiplexing design table is generated according to the preset rule, wherein the preset rule defines that the pin multiplexing design table comprises the pin name of the pin multiplexing module, the function name realized by at least one function module and the corresponding function direction, and the function name comprises the name of the function module and the signal name connected with the pin multiplexing module; running a script tool according to the pin name, the function name and the function direction to form a connection file for representing the connection of the signal between the pin and at least one function module; the method and the device have the advantages that the connection of the signals between the pins and at least one functional module in the connection file is verified by adding the excitation according to the function direction, verification information and excitation do not need to be filled in manually, and the multiplexing verification time of the pins can be shortened.
In addition, running the script tool according to the pin name, the function name and the function direction to form a connection file for representing the connection of the signal between the pin and the at least one function module includes: the absolute path of the function module is obtained by analyzing the name of the function module through the script tool, the signals can be connected to corresponding signals of different function modules through analyzing the information in the pin multiplexing design table, and the signal levels and the information do not need to be filled in manually.
In addition, running the script tool according to the pin name, the function name and the function direction to form a connection file for representing the connection of the signal between the pin and the at least one function module, further comprises: processing the signal names according to a preset rule to generate a plurality of signal names of the functional module and a plurality of signal names of the corresponding pin multiplexing module, distinguishing a plurality of signals of the pin multiplexing module from a plurality of signals connected with the functional module,
in addition, verifying the connection of signals between a pin and at least one functional module in a connection file according to the addition of stimuli in the functional direction comprises: when the function direction is output, adding excitation at one side of the function module to verify a signal of an output port of the pin multiplexing module; when the function direction is input, adding excitation at an input port of the pin multiplexing module, and verifying a signal of a functional module port; when the function direction is bidirectional, the enable signal is controlled, the function direction is respectively adjusted to be input or output and verified, excitation can be automatically added according to the function direction, manual input excitation is not needed, manual errors are reduced, the multiplexing verification time of pins is shortened, and verification is more reliable and efficient.
Drawings
FIG. 1 is a schematic diagram of an integrated circuit chip according to a first embodiment of the present invention;
FIG. 2 is a flow chart of a pin multiplexing verification method according to a first embodiment of the present invention;
FIG. 3 is a schematic diagram of pin multiplexing implemented according to the verification method of pin multiplexing in FIG. 2;
FIG. 4 is a schematic diagram of connections obtained according to the pin multiplexing verification method of FIG. 2;
fig. 5 is a schematic structural diagram of a pin multiplexing verification apparatus according to a second embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, it will be appreciated by those of ordinary skill in the art that numerous technical details are set forth in order to provide a better understanding of the present application in various embodiments of the present invention. However, the technical solution claimed in the present application can be implemented without these technical details and various changes and modifications based on the following embodiments.
The first embodiment of the invention relates to a pin reuse verification method. The pin multiplexing verification method is used for pin multiplexing verification of an integrated circuit chip, and the integrated circuit chip comprises a pin multiplexing module and at least one functional module. Specifically, as shown in fig. 1, the integrated circuit chip includes: the device comprises a functional module 1, a functional module 2, a functional module 3, a functional module 4, a pin multiplexing module and a multiplexing output module. The pin multiplexing module corresponds to the multiplexing of one or several pins in an integrated circuit chip. As can be seen from fig. 1, one pin can multiplex 4 functions, each of which can be set to an input, an output, or both, one function at a time being selected for connection to an output port. Of course, in other embodiments of the present invention, any pin may only multiplex one or more of the 4 functions, and is not limited herein. In addition, the integrated circuit chip may include a plurality of functional modes, such as a normal functional mode, a test functional mode, and the like. The functions realized by different functional mode pins are different, and the multiplexing of the pins is also different.
As shown in fig. 2, the pin multiplexing verification method includes:
step S10: and generating a pin multiplexing design table according to a preset rule, wherein the preset rule defines the pin multiplexing design table to comprise a pin name of the pin multiplexing module, a function name realized by at least one function module and a corresponding function direction, and the function name comprises a name of the function module and a signal name connected with the pin multiplexing module.
In the embodiment of the invention, the signal of the pin multiplexing module and the signal of the corresponding functional module can be connected according to the functional name. Since the absolute path of the function module needs to be defined in the environment in the process, the absolute path of the function module can be acquired by analyzing the name of the function module through the script tool, so that the macro definition of the corresponding function module can be generated by analyzing the name of the function module, the path and the specific signal name of the corresponding function module can be represented, and then the pin multiplexing module can be connected with the corresponding function module by connecting signals.
In addition, because only one function name corresponding to one function module in the pin multiplexing design table is provided, and there may be a plurality of signals connected to the pin multiplexing module, for example, the signals may include input signals, output signals and enable signals, at this time, the signal names may be processed according to the preset rule to generate a plurality of signal names of the function module and a plurality of signal names of the corresponding pin multiplexing module, so as to distinguish different signals of the same function module. For example, three signals corresponding to a signal name dp _ rbdp _ data connected to the pin multiplexing block are' U _ chip _ dp. Wherein,' U _ chip _ DP is an absolute path of a functional block defined in an environment, and rdp _ data _ in, rdp _ data _ out, and rdp _ data _ en are three signal names generated according to a preset rule, and sequentially connect the generated three signals to an input, an output, and an enable of a corresponding pin of the pin multiplexing block.
In the normal functional mode, a pin multiplexing design table is shown in table 1, in which a pin number (Gpio No.) is 1 and a pin name (ballname) is RFCKEN, and the pin can multiplex functions 1 and 3 without functions corresponding to functions 2 and 4 and need not be filled in. The function name of function 1 is ddrpwr _ rf _ osc _ en, and the corresponding function direction is O, indicating output. Function 3 has the function name gpio [1] with direction I/O, indicating both input and output.
TABLE 1 Pin multiplexing design Table
The pin multiplexing structure formed according to the pin multiplexing design table shown in table 1 is shown in fig. 3. The pin multiplexing module can be represented by a pin name, and the name ddrpwr of the function module 1 is obtained from the function name ddrpwr _ rf _ osc _ en of the function 1, and the name gpio of the function module 3 is obtained from the function name gpio [1] of the function 3. The RFCKEN pin does not have the corresponding functions of the multiplexing function 2 and the multiplexing function 4, and the function module 2 and the function module 4 are empty (null) and do not need to be changed.
In the embodiment of the invention, 224 pins of the integrated circuit chip and four functions of each pin can be processed according to the preset rule.
Step S11: and running the script tool according to the pin name, the function name and the function direction to form a connection file for representing the connection of the signal between the pin and the at least one function module.
In step S11, the preset rule defines that the function name includes the name of the function module and the name of the signal connected to the pin multiplexing module. Taking table 1 as an example, the function name of function 1 is broken down into two parts according to the first dashed line, the former part is the name of function module 1, and the latter part is the name of the signal connected to the pin multiplexing module. The output signal of function 1 of pin RFCKEN is connected to the rf _ soc _ en signal of the functional module ddrpwr, the name ddrpwr of which is macro-defined in the environment, directly defining the path hierarchy of the module, i.e. the absolute path. Rf _ soc _ en is then directed out to mux _ out 1. Meanwhile, the input, output and enable signals of function 3 of the connection pin RFCKEN to the functional module gpio are connected with mux _ in3, mux _ out3 and mux _ en3 signals, respectively. For function block gpio, the signal for function 3 is automatically connected to the corresponding signal for that function block gpio by the scripting tool, i.e., input signal connected to gpio _ in [1], output signal connected to gpio _ out [1], enable signal connected to gpio _ ddr [1 ].
It is contemplated that an integrated circuit chip may include multiple functional modes, and that different functional mode pins may implement different functions and different multiplexing of pins may be used. Thus, in the embodiment of the invention, for a plurality of functional modes of the integrated circuit chip, the script tool is operated according to the pin name, the functional name and the functional direction to form a plurality of connection files respectively representing the connection between the pin corresponding to the functional mode and at least one functional module. Specifically, the script tool presets the pin multiplexing information required in each functional mode, and then the script tool is run to form a plurality of connection files respectively connected with the pins corresponding to the functional modes and at least one functional module according to the pin names and the functional names acquired from the pin multiplexing design table.
In the embodiment of the invention, the signal of the pin multiplexing module can be automatically decomposed into different functional modes according to the pin multiplexing design table, and the signal of the pin multiplexing module is connected to corresponding signals of different functional modules by analyzing the information in the pin multiplexing design table, so that the signal of each pin multiplexing module does not need to be manually searched and filled in the level of the signal of the functional module. When the information of the pin multiplexing module is modified, signals corresponding to each functional module do not need to be modified, and only the script tool needs to be operated again according to the pin multiplexing design table, so that the connection file of the pin multiplexing module and the functional module in the modified functional mode can be directly generated, and human errors can be reduced.
Step S12: and verifying signals between the pins and the at least one functional module in the connection file according to the added excitation of the functional direction.
In step S12, stimuli are automatically added by the scripting tool for different functional modes according to the functional directions in the pin multiplexing design table. Specifically, when the function direction is output, adding excitation at one side of the function module to verify a signal of an output port of the pin multiplexing module; when the function direction is input, adding excitation at an input port of the pin multiplexing module, and verifying a signal of a functional module port; and when the function direction is bidirectional, controlling the enabling signal, respectively adjusting the function direction to be input or output, and verifying. Therefore, when verification is carried out, a verification table does not need to be filled in, and the verification time can be saved; and according to the whole path from the pin multiplexing module to the functional module signal, the test vector is automatically generated by directly analyzing the pin multiplexing design table without filling any excitation during verification, and the automatic verification of the pin multiplexing is completed.
Referring to fig. 4, continuing with the normal functional mode as an example, with function 1 oriented as output, a high level is applied to mux _ out1 to check if the signal value at output port pout is 1, and then a low level is applied to mux _ out1 to continue to detect if the signal value at output port pout is 0. If the functional direction is input, excitation is applied to the input port pin on the multiplexing output module side, whether the signal mux _ in of the functional module port is a corresponding value or not is detected, and whether the data is correct or not is detected. The direction in function 3 is bidirectional, and the state of the function direction is adjusted by controlling the enable signal, so that the function direction is tested as input and output respectively. Mux _ en3 is first set to 1, then the stimulus is applied to mux _ out3 to detect the signal value at the output port pout, mux _ en3 is then set to 0, the stimulus is applied to Pin, and the data value is detected as correct at the module side mux _ in 3. And automatically connecting pins needing to be added with excitation according to the function direction through a script tool.
According to the connection file generated in the step S11, according to the method, the pins of each pin multiplexing module are sequentially verified, and when the pin multiplexing module designed with an update or a project is changed, only the script tool needs to be re-run to generate a verification function mode corresponding to the new design, thereby realizing the verification of the pin multiplexing, without any manual modification, reducing the possibility of errors caused by modifying a large number of signals manually, making the verification more reliable, and making the verification more efficient.
The steps of the above methods are divided for clarity, and the implementation may be combined into one step or split some steps, and the steps are divided into multiple steps, so long as the steps contain the same logical relationship, which is within the protection scope of the present patent; it is within the scope of the patent to add insignificant modifications to the algorithms or processes or to introduce insignificant design changes to the core design without changing the algorithms or processes.
A second embodiment of the present invention relates to a pin multiplexing verification apparatus for performing pin multiplexing verification on an integrated circuit chip, where the integrated circuit chip includes a pin multiplexing module and at least one functional module. The pin multiplexing module corresponds to the multiplexing of one or several pins in an integrated circuit chip. One pin may multiplex 4 functions, each of which may be set to an input, an output, or both, one function at a time being selected for connection to an output port. Of course, in other embodiments of the present invention, any pin may only multiplex one or more of the 4 functions, and is not limited herein. In addition, the integrated circuit chip may include a plurality of functional modes, such as a normal functional mode, a test functional mode, and the like. The functions realized by different functional mode pins are different, and the multiplexing of the pins is also different.
As shown in fig. 5, the pin multiplexing verification apparatus includes: the system comprises a table establishing module, a connection generating module and a verification module. The table establishing module is used for generating a pin multiplexing design table according to a preset rule, wherein the preset rule defines that the pin multiplexing design table comprises a pin name of the pin multiplexing module, a function name realized by at least one function module and a corresponding function direction, and the function name comprises a name of the function module and a signal name connected with the pin multiplexing module. The connection generation module is connected with the table establishment module and used for running a script tool according to the pin name, the function name and the function direction to form a connection file used for representing the connection of signals between the pin and at least one function module. The verification module is connected with the connection generation module and used for verifying signals between the pins and the at least one functional module in the connection file according to the added excitation of the functional direction.
In the embodiment of the invention, the table building module can connect the signal of the pin multiplexing module and the signal of the corresponding functional module according to the functional name. In the process, the absolute path of the function module needs to be defined in the environment, so the absolute path of the function module can be obtained by analyzing the name of the function module through a script tool, and thus, the macro definition of the corresponding function module can be generated by analyzing the name of the function module through the table establishing module, the macro definition represents the path and the specific signal name of the corresponding function module, and then the pin multiplexing module can be connected with the corresponding function module by connecting signals.
In addition, because only one function name corresponding to one function module in the pin multiplexing design table is provided, and there may be a plurality of signals connected to the pin multiplexing module, for example, the signals may include input signals, output signals and enable signals, at this time, the signal names may be processed according to the preset rule to generate a plurality of signal names of the function module and a plurality of signal names of the corresponding pin multiplexing module, so as to distinguish different signals of the same function module.
And only filling the function name and the function direction corresponding to the function multiplexed by the pin multiplexing module in the pin multiplexing design table, and leaving blank and not filling the function not available in the pin multiplexing module. In the embodiment of the invention, 224 pins of the integrated circuit chip and four functions of each pin can be processed according to the preset rule.
In the embodiment of the present invention, the preset rule defines the function name to include a name of the function module and a name of a signal connected to the pin multiplexing module. Specifically, the function name of any function is decomposed into two parts according to a first underline, the former part is the name of the function module, and the latter part is the name of the signal connected with the pin multiplexing module. The names of the function modules are macro definitions in the environment, and directly define the path hierarchy of the modules, namely the absolute paths of the function modules.
It is contemplated that an integrated circuit chip may include multiple functional modes, and that different functional mode pins may implement different functions and different multiplexing of pins may be used. Thus, in an embodiment of the present invention, the connection generation module is configured to: and aiming at a plurality of functional modes, running a script tool according to the pin name, the functional name and the functional direction to form a plurality of connection files respectively representing the connection between the pin corresponding to the functional mode and at least one functional module. Specifically, the connection generation module presets the pin multiplexing information required in each functional mode through the script tool, and then can run the script tool according to the pin names acquired from the pin multiplexing design table and the functional names to form a plurality of connection files in which the pins corresponding to the functional modes are connected with at least one functional module.
In the embodiment of the invention, the connection generation module can be automatically decomposed into different functional modes according to the pin multiplexing design table through a script tool, and the signals of the pin multiplexing module are connected to the corresponding signals of different functional modules by analyzing the information in the pin multiplexing design table, so that the signals of each pin multiplexing module do not need to be manually searched and filled in the level of the signals of the functional modules. When the information of the pin multiplexing module is modified, signals corresponding to each functional module do not need to be modified, and only the connection generation module needs to operate the script tool again according to the pin multiplexing design table, so that the connection files of the pin multiplexing module and the functional modules in the modified functional mode can be directly generated, and human errors can be reduced.
In an embodiment of the invention, the verification module automatically adds stimuli for different functional modes according to the functional directions in the pin multiplexing design table through a scripting tool. Specifically, the verification module is to: when the function direction is output, adding excitation at one side of the function module to verify a signal of an output port of the pin multiplexing module; when the function direction is input, adding excitation at an input port of the pin multiplexing module, and verifying a signal of a functional module port; and when the function direction is bidirectional, controlling the enabling signal, respectively adjusting the function direction to be input or output, and verifying. Therefore, when the verification module performs verification, a verification table does not need to be filled in, and the verification time can be saved; and according to the whole path from the pin multiplexing module to the functional module signal, the test vector is automatically generated by directly analyzing the pin multiplexing design table without filling any excitation during verification, and the automatic verification of the pin multiplexing is completed.
The verification module verifies the pins of each pin multiplexing module in sequence according to the connection file generated by the connection generation module, when the pin multiplexing module designed with an update or a project is changed, only a script tool needs to be operated again to generate a verification function mode corresponding to a new design, the pin multiplexing verification is realized, any manual modification is not needed, the possibility of errors caused by modifying a large number of signals manually is reduced, the verification is more reliable, and the verification is more efficient.
It should be understood that this embodiment is an example of the apparatus corresponding to the first embodiment, and may be implemented in cooperation with the first embodiment. The related technical details mentioned in the first embodiment are still valid in this embodiment, and are not described herein again in order to reduce repetition. Accordingly, the related-art details mentioned in the present embodiment can also be applied to the first embodiment.
It should be noted that each module referred to in this embodiment is a logical module, and in practical applications, one logical unit may be one physical unit, may be a part of one physical unit, and may be implemented by a combination of multiple physical units. In addition, in order to highlight the innovative part of the present invention, elements that are not so closely related to solving the technical problems proposed by the present invention are not introduced in the present embodiment, but this does not indicate that other elements are not present in the present embodiment.
It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples for carrying out the invention, and that various changes in form and details may be made therein without departing from the spirit and scope of the invention in practice.
Claims (8)
1. A pin multiplexing verification method is used for pin multiplexing verification of an integrated circuit chip, the integrated circuit chip comprises a pin multiplexing module and at least one functional module, and the pin multiplexing verification method is characterized by comprising the following steps:
generating a pin multiplexing design table according to a preset rule, wherein the preset rule defines that the pin multiplexing design table comprises a pin name of the pin multiplexing module, a function name realized by the at least one function module and a corresponding function direction, and the function name comprises a name of the function module and a signal name connected with the pin multiplexing module;
running a script tool according to the pin name, the function name and the function direction to form a connection file for representing the connection of signals between the pin and at least one function module;
adding excitation according to the function direction to verify signals between the pins and at least one functional module in the connection file;
wherein, the verifying the signal between the pin and the at least one functional module in the connection file according to the adding of the stimulus to the functional direction specifically comprises:
when the function direction is output, adding the excitation at one side of the function module to verify a signal of an output port of the pin multiplexing module;
when the function direction is input, adding the excitation at the input port of the pin multiplexing module to verify the signal of the port of the function module;
and when the function direction is bidirectional, controlling an enabling signal, respectively adjusting the function direction to be input or output and verifying.
2. The method for verifying pin multiplexing according to claim 1, wherein said executing a script tool according to the pin name, the function name and the function direction to form a connection file for representing a connection of a signal between the pin and at least one function module comprises: and analyzing the name of the functional module through the script tool to obtain the absolute path of the functional module.
3. The method for verifying pin multiplexing according to claim 1, wherein the running a script tool according to the pin name, the function name and the function direction to form a connection file representing a connection of a signal between the pin and at least one function module further comprises: and processing the signal names according to the preset rule to generate a plurality of signal names of the functional module and a plurality of corresponding signal names of the pin multiplexing module.
4. The method of claim 1, wherein the integrated circuit chip comprises a plurality of functional modes, and wherein executing a scripting tool according to the pin name, the function name, and the function direction to form a connection file representing the connection of the signals between the pins and at least one functional module comprises:
and aiming at the plurality of functional modes, running the script tool according to the pin names, the functional names and the functional directions to form a plurality of connection files respectively representing the connection between the pins corresponding to the functional modes and at least one functional module.
5. A pin multiplexing verification device for performing pin multiplexing verification on an integrated circuit chip, wherein the integrated circuit chip comprises a pin multiplexing module and at least one functional module, the pin multiplexing verification device comprises:
the table establishing module is used for generating a pin multiplexing design table according to a preset rule, wherein the preset rule defines that the pin multiplexing design table comprises a pin name of the pin multiplexing module, a function name realized by the at least one function module and a corresponding function direction, and the function name comprises a name of the function module and a signal name connected with the pin multiplexing module;
the connection generating module is connected with the table establishing module and used for running a script tool according to the pin name, the function name and the function direction to form a connection file for representing the connection of signals between the pin and at least one function module;
a verification module, configured to verify a signal between the pin and the at least one functional module in the connection file according to the function direction addition excitation, where the verifying the signal between the pin and the at least one functional module in the connection file according to the function direction addition excitation specifically includes: when the function direction is output, adding the excitation at one side of the function module to verify a signal of an output port of the pin multiplexing module; when the function direction is input, adding the excitation at the input port of the pin multiplexing module to verify the signal of the port of the function module; and when the function direction is bidirectional, controlling an enabling signal, respectively adjusting the function direction to be input or output and verifying.
6. The pin multiplexing verification apparatus according to claim 5, wherein the connection generation module is further configured to: and analyzing the name of the functional module through the script tool to obtain the absolute path of the functional module.
7. The pin multiplexing verification apparatus according to claim 5, wherein the connection generation module is further configured to: and processing the signal names according to the preset rule to generate a plurality of signal names of the functional module and a plurality of corresponding signal names of the pin multiplexing module.
8. The pin multiplexing verification apparatus of claim 5, wherein the integrated circuit chip comprises a plurality of functional modes, and the connection generation module is configured to:
and aiming at the plurality of functional modes, running the script tool according to the pin names, the functional names and the functional directions to form a plurality of connection files respectively representing the connection between the pins corresponding to the functional modes and at least one functional module.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611261750.XA CN108268676B (en) | 2016-12-30 | 2016-12-30 | Verification method and device for pin multiplexing |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611261750.XA CN108268676B (en) | 2016-12-30 | 2016-12-30 | Verification method and device for pin multiplexing |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108268676A CN108268676A (en) | 2018-07-10 |
| CN108268676B true CN108268676B (en) | 2021-06-01 |
Family
ID=62755083
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201611261750.XA Active CN108268676B (en) | 2016-12-30 | 2016-12-30 | Verification method and device for pin multiplexing |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108268676B (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111665432B (en) * | 2020-05-22 | 2022-10-25 | 中国人民解放军国防科技大学 | Verification method, device, equipment and storage medium for chip pin multiplexing module |
| CN112380160A (en) * | 2020-11-13 | 2021-02-19 | 广东青云计算机科技有限公司 | Device and method for realizing dynamic reconfiguration of pin function in processor |
| CN112818616B (en) * | 2021-01-15 | 2024-03-12 | 珠海泰芯半导体有限公司 | Pin naming method, register excitation source adding method and electronic device |
| CN116227427B (en) * | 2023-03-03 | 2024-05-07 | 南京金阵微电子技术有限公司 | Verification method, verification device, medium and electronic equipment |
| CN116737632A (en) * | 2023-06-13 | 2023-09-12 | 珠海市凌珑宇芯科技有限公司 | Chip pin function multiplexing circuit generation method, computer device and storage medium |
Family Cites Families (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1560914A (en) * | 2004-02-19 | 2005-01-05 | 中国科学院计算技术研究所 | Plug and play chip testing vector generating circuit and method |
| US7519879B2 (en) * | 2004-04-26 | 2009-04-14 | Agilent Technologies, Inc. | Apparatus and method for dynamic in-circuit probing of field programmable gate arrays |
| CN1677576A (en) * | 2005-02-01 | 2005-10-05 | 苏州超锐微电子有限公司 | Method for realizing memory data check using look-up function instruction |
| US8089960B2 (en) * | 2007-01-31 | 2012-01-03 | Hewlett-Packard Development Company, L.P. | Highly flexible and efficient MAC to PHY interface |
| CN100570591C (en) * | 2007-09-29 | 2009-12-16 | 中兴通讯股份有限公司 | Terminal chip pin multiplexing device |
| US8422465B2 (en) * | 2007-12-17 | 2013-04-16 | Electronics And Telecommunications Research Institute | Transmitter and receiver for high throughput wireless communication system using multiple antenna, method thereof, and digital intermediate frequency transmission signal processing method for the same |
| CN102169160B (en) * | 2010-02-08 | 2015-09-16 | 无锡中星微电子有限公司 | A kind of demo plant of pin multiplexing of integrated circuit and verification method |
| CN103136138B (en) * | 2011-11-24 | 2015-07-01 | 炬力集成电路设计有限公司 | Chip, chip debugging method and communication method for chip and external devices |
| US8689357B2 (en) * | 2012-05-19 | 2014-04-01 | Freescale Semiconductor, Inc. | Tamper detector for secure module |
| CN103066872B (en) * | 2013-01-17 | 2015-06-17 | 矽力杰半导体技术(杭州)有限公司 | Integration switch power supply controller and switch power supply using the same |
| CN103246631B (en) * | 2013-05-16 | 2016-01-13 | 北京工业大学 | A kind of pin multiplexing method for improving pin utilization rate and circuit |
| CN104270127A (en) * | 2014-09-16 | 2015-01-07 | 四川和芯微电子股份有限公司 | Pin multiplexing circuit of SOC |
| CN105068950A (en) * | 2015-07-24 | 2015-11-18 | 深圳市微纳集成电路与系统应用研究院 | Pin multiplexing system and method |
-
2016
- 2016-12-30 CN CN201611261750.XA patent/CN108268676B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN108268676A (en) | 2018-07-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108268676B (en) | Verification method and device for pin multiplexing | |
| US9495492B1 (en) | Implementing synchronous triggers for waveform capture in an FPGA prototyping system | |
| US20080306722A1 (en) | Logic verification system | |
| US20160062861A1 (en) | Method for connecting an input/output interface of a testing device equipped for testing a control unit | |
| CN111381148A (en) | System and method for realizing chip test | |
| CN101303708A (en) | Method and apparatus for encoding code for multiplexing chip pins | |
| CN104834591A (en) | Method and system for testing AUTOSAR software component | |
| CN110162340B (en) | ID configuration method of series circuit, series circuit and related equipment | |
| GB2514402A (en) | Method and test environment for testing an integrated circuit | |
| US7913002B2 (en) | Test apparatus, configuration method, and device interface | |
| US5642363A (en) | Method and apparatus for testing of electronic assemblies | |
| CN108319516A (en) | A kind of test system and test method | |
| US7610535B2 (en) | Boundary scan connector test method capable of fully utilizing test I/O modules | |
| CN104330685A (en) | Connection check-up method and connection check-up device | |
| KR100974669B1 (en) | A built off self test circuit system or a pattern generating system that have look up table and a method for outputting test data for device under test using the system | |
| CN116629195A (en) | Integrated circuit simulation verification platform | |
| CN115017864A (en) | Authentication method, authentication apparatus, electronic device, and computer-readable storage medium | |
| US8122416B2 (en) | Arrangement verification apparatus | |
| US9753087B2 (en) | Method for testing a multi-chip system or a single chip and system thereof | |
| KR20180060675A (en) | Apparatus and method for testing input/output signals and software performance of electric device | |
| CN108155979B (en) | Detection equipment | |
| US6119256A (en) | Apparatus for testing a fixed logic value interconnection between integrated circuits | |
| US6530046B1 (en) | Circuit, semiconductor device and method for enhancing test efficiency of function modules | |
| US11988710B2 (en) | Test methods, tester, load board and test system | |
| CN115794510A (en) | Verification platform, verification method and storage medium of wireless communication physical layer |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |