CN116737632A - Chip pin function multiplexing circuit generation method, computer device and storage medium - Google Patents
Chip pin function multiplexing circuit generation method, computer device and storage medium Download PDFInfo
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Abstract
The invention provides a chip pin function multiplexing circuit generating method, a computer device and a storage medium, wherein the chip pin function multiplexing circuit generating method comprises the following steps: setting a function pin mapping table and a function signal mapping table, wherein the function pin mapping table comprises a pin name, a function multiplexing number and a multiplexing function name, and the function signal mapping table comprises a multiplexing function name, a pin control signal name and a pin control signal setting; acquiring a multiplexing function name corresponding to each pin according to the function pin mapping table, searching the function signal mapping table by taking the multiplexing function name as an index, and acquiring all control definitions of each pin; and the driving logic circuit is used for generating all basic control signals of each pin by preset logic according to the total control definition of each pin. The method for generating the chip pin function multiplexing circuit can facilitate the allocation and the later modification of pin multiplexing.
Description
Technical Field
The invention relates to the technical field of chip pin multiplexing, in particular to a method for generating a chip pin function multiplexing circuit, a computer device applying the method for generating the chip pin function multiplexing circuit and a computer readable storage medium applying the method for generating the chip pin function multiplexing circuit.
Background
With the development of chip technology, the integration level of the chip is higher, the functions supported by the chip are more and more complex, more and more interface signals need to be led out to chip pins from functional modules in the chip, but the number of the chip pins is limited, so that multiplexing processing is needed to IO pins of the chip.
The existing method is that an IO multiplexing table for the SOC chip is established according to a preset rule, then the IO multiplexing table is read, and multiplexing codes of each port in the SOC chip are automatically generated according to the read contents; and finally, writing the multiplexing code into the SOC chip to update the IO pin multiplexing module in the SOC chip so as to realize the IO pin multiplexing function of the multiplexing module. Thereby avoiding the problems of easy error and high labor cost when the IO pin is reused in the prior art; and even if the multiplexing function is modified in the middle stage, the IO pin multiplexing module in the chip can be updated only by correspondingly modifying the multiplexing table and reading the modified IO multiplexing table, so that the labor cost and efficiency of IO multiplexing are greatly reduced. However, in this method, the IO multiplexing table needs to fill in the function name multiplexed by each pin, and the attribute of the current pin is marked by adding a suffix to the function name, so that the labor cost of filling is still very high, and the filling personnel needs to know each function name and its corresponding control signal, which is not beneficial to the later modification operation.
Disclosure of Invention
The first object of the present invention is to provide a method for generating a chip pin function multiplexing circuit, which can facilitate the allocation and the later modification of pin multiplexing.
It is a second object of the present invention to provide a computer apparatus that can facilitate the assignment and post-modification of pin reuse.
It is a third object of the present invention to provide a computer readable storage medium that can facilitate allocation and post-modification of pin reuse.
In order to achieve the first object, the method for generating a chip pin function multiplexing circuit according to the present invention includes: setting a function pin mapping table and a function signal mapping table, wherein the function pin mapping table comprises a pin name, a function multiplexing number and a multiplexing function name, the pin name is a row label of the function pin mapping table, the function multiplexing number is a column label of the function pin mapping table, the row and column number where the multiplexing function name is located represents the multiplexing number of the multiplexing function at a pin, the function signal mapping table comprises a multiplexing function name, a pin control signal name and a pin control signal setting, the multiplexing function name is a row label of the function signal mapping table, the pin control signal name is a column label of the function signal mapping table, and the pin control signal setting represents how the multiplexing function processes control signals of multiplexing pins; acquiring a multiplexing function name corresponding to each pin according to the function pin mapping table, searching the function signal mapping table by taking the multiplexing function name as an index, and acquiring all control definitions of each pin; and the driving logic circuit is used for generating all basic control signals of each pin by preset logic according to the total control definition of each pin.
According to the scheme, the chip pin function multiplexing circuit generation method disclosed by the invention is used for processing the mapping relation between functions and pins and the mapping relation between functions and control signals separately, so that the problems that errors are easy to occur and the labor cost is high when IO pin multiplexing is realized in the prior art are avoided, and when the multiplexing function of the pins is modified, only the names of the multiplexing functions are needed to be modified, so that the labor cost of IO multiplexing design is greatly reduced and the working efficiency is improved.
In a further aspect, the step of setting the function pin mapping table and the function signal mapping table includes: the same multiplexing function name appears in different pin names and different multiplexing numbers and/or in different multiplexing numbers of the same pin name.
Therefore, the same multiplexing function name can be repeatedly used in the mapping table, and the same multiplexing function name appears in different multiplexing numbers of the same pin name, so that the same group of function signals can be favorably kept consistent with the multiplexing numbers of the same group of functions when the same group of function signals need to be distributed to different pins.
In a further aspect, the step of setting the function pin mapping table and the function signal mapping table includes: the same group of functional signals are allocated to the same multiplexing number of different pins.
Therefore, the same group of functional signals are distributed to the same multiplexing number of different pins, so that the readability can be improved, and the rapid positioning during later modification is facilitated.
In a further aspect, the step of setting the function pin mapping table and the function signal mapping table includes: each pin is provided with the same number of functional multiplex numbers.
Therefore, each pin is provided with the same number of function multiplexing numbers, so that the configuration mode of each pin can be unified, and simplification and automatic generation of a circuit are facilitated. For example, each pin has a 3-bit register to configure the selection multiplexing number, and then a 3-8 decoder is uniformly used to generate the function enabling signal. When the pin function allocation is adjusted, the pin function allocation is also simplified, and only functions are added in the corresponding numbered cells.
In a further scheme, the pin control signals include basic control signals and extension control signals, wherein the extension control signals represent how to extend the processing mode of the basic control signals.
Therefore, the pin control signals comprise basic control signals and extension control signals, which is beneficial to improving the expansibility of the function multiplexing and avoiding control confusion.
In a further aspect, the step of generating, with the preset logic, the driving logic of all the basic control signals of each pin according to all the control definitions of each pin includes: the driving logic of each basic control signal is driven by a plurality of enabled multiplexing function selection logic OR; the extended control signal and multiplexing function select logic AND drive.
Therefore, the multiplexing function selection logic OR driving enables only one multiplexing function at the same time, and the expansion control signal and the multiplexing function selection logic AND driving can avoid the control confusion of the multiplexing function.
In a further aspect, the step of searching the function signal mapping table with the multiplexing function name as an index includes: traversing the function signal mapping table, judging whether the multiplexing function name of the current index exists or not, and if not, sending prompt information.
Therefore, the multiplexing function name of the current index is searched through traversing the function signal mapping table, and when the multiplexing function name of the current index does not exist, the user can be prompted to modify.
In order to achieve the second object of the present invention, the present invention provides a computer apparatus including a processor and a memory, the memory storing a computer program, the computer program implementing the steps of the above-described method for generating a chip pin function multiplexing circuit when executed by the processor.
In order to achieve the third object of the present invention, a computer readable storage medium is provided, on which a computer program is stored, which when executed by a controller, implements the steps of the above-described method for generating a chip pin function multiplexing circuit.
Drawings
Fig. 1 is a flowchart of an embodiment of a method for generating a chip pin function multiplexing circuit according to the present invention.
Fig. 2 is a schematic diagram of a functional pin mapping table in an embodiment of a method for generating a chip pin function multiplexing circuit according to the present invention.
Fig. 3 is a schematic diagram of a functional signal mapping table in an embodiment of a method for generating a chip pin function multiplexing circuit according to the present invention.
The invention is further described below with reference to the drawings and examples.
Detailed Description
The method for generating the chip pin function multiplexing circuit is an application program applied to a computer device and is used for generating the chip pin function multiplexing circuit.
The chip pin function multiplexing circuit generating method embodiment comprises the following steps:
as shown in fig. 1, in this embodiment, when the method for generating the chip pin function multiplexing circuit is in operation, step S1 is executed first, and a function pin mapping table and a function signal mapping table are set. In order to facilitate automatic generation of the chip pin function multiplexing circuit, a function pin mapping table and a function signal mapping table are set so as to automatically generate a driving logic circuit according to the pin function multiplexing relation according to the function pin mapping table and the function signal mapping table.
In this embodiment, the function pin mapping table includes a pin name, a function multiplexing number and a multiplexing function name, the pin name is a row label of the function pin mapping table, the function multiplexing number is a column label of the function pin mapping table, and the row and column number where the multiplexing function name is located represents the multiplexing number of the pin. For example, referring to fig. 2, PA0 to PA1 are pin names, F1 to F7 are function multiplexing numbers, din, dout, spi _sck, and the like are multiplexing function names. The function signal mapping table comprises a multiplexing function name, a pin control signal name and a pin control signal setting, wherein the multiplexing function name is a row label of the function signal mapping table, the pin control signal name is a column label of the function signal mapping table, and the pin control signal setting indicates how the multiplexing function processes control signals of multiplexing pins. For example, referring to fig. 3, din, iic_sda, etc. are multiplexing function names, IE, OE, etc. are pin control signal names, Y, N, iic _sda_oe, etc. are pin control signal settings. In this embodiment, the pin control signal includes a basic control signal and an extension control signal, where the extension control signal indicates how to extend the processing manner of the basic control signal. As in fig. 3, IE, OE, AE, PU, PD and OD are basic control signals, IND, SIN, SOUT, IEC, OEC and AEC are extended control signals.
In this embodiment, the step of setting the function pin mapping table and the function signal mapping table includes: the same multiplexing function name appears in different pin names and different multiplexing numbers and/or in different multiplexing numbers of the same pin name. For example, in fig. 2, the multiplexing function name spi_cs appears in the multiplexing number F8 corresponding to the pin name PA0, and also appears in the multiplexing numbers F3 and F4 corresponding to the pin name PA 4. The same multiplexing function name can be repeatedly used in the mapping table, and the same multiplexing function name appears in different multiplexing numbers of the same pin name, so that the multiplexing numbers of the same group of functions are kept consistent when the same group of function signals need to be distributed to different pins. For example, the multiplexing function names sci_sck, sci_mosi, sci_miso and sci_cs are a group, and when the multiplexing function names are allocated, the group of multiplexing function names are allocated to the same multiplexing number, so that the searching and positioning are facilitated when the multiplexing function names are modified.
In this embodiment, the step of setting the function pin mapping table and the function signal mapping table further includes: the same group of functional signals are allocated to the same multiplexing number of different pins. The same group of functional signals are distributed to the same multiplexing number of different pins, so that the readability can be improved, and the rapid positioning during later modification is facilitated. In this embodiment, the same set of functional signals refers to different signals of the same functional module. For example, different signals of the SPI module: the functional module names and signal names are underlined for spe_sck, spe_mosi, spe_miso, and spe_cs, with spe being the module name and sck being the signal name.
In this embodiment, the step of setting the function pin mapping table and the function signal mapping table includes: each pin is provided with the same number of functional multiplex numbers. The number of the function multiplexing numbers can be set as required, and in this embodiment, the number of the function multiplexing numbers is 8. The same number of function multiplexing numbers are arranged on each pin, so that the configuration mode of each pin can be unified, and simplification and automatic generation of a circuit are facilitated. For example, each pin has a 3-bit register to configure the select function multiplexing number, and then a 3-8 decoder is uniformly used to generate the function enable signal. When the pin function allocation is adjusted, the pin function allocation is also simplified, and only functions are added in the corresponding numbered cells.
After setting the function pin mapping table and the function signal mapping table, executing step S2, obtaining the multiplexing function name corresponding to each pin according to the function pin mapping table, searching the function signal mapping table by using the multiplexing function name as an index, and obtaining all control definitions of each pin. After the automation script is run, the pin mapping table is read, the multiplexing function name corresponding to each pin is confirmed, the function signal mapping table is traversed according to the multiplexing function names, the pin control signal names and the pin control signal settings corresponding to the multiplexing function names are indexed, and therefore all control definitions of each pin are obtained. For example, after confirming the multiplexing function name din of the pin PA0 from the pin mapping table, the pin control signal names IE, OE, AE, PU, PD, OD, IND, SIN, SOUT, IEC, OEC and the pin control signal settings of the AEC are found to be Y, N, N, N, N, N, L, din, N, N, N, N in sequence according to the multiplexing function name din, where "Y" indicates that control is required, and "N" is selected to indicate that control is not required.
In addition, in this embodiment, the step of searching the function signal mapping table with the multiplexing function name as an index includes: traversing the function signal mapping table, judging whether the multiplexing function name of the current index exists or not, and if not, sending prompt information. And searching the multiplexing function name of the current index by traversing the function signal mapping table, and prompting a user to modify when the multiplexing function name of the current index does not exist, so that the efficiency is improved.
After obtaining all control definitions of each pin, step S3 is executed, and according to all control definitions of each pin, the driving logic circuit of all basic control signals of each pin is generated by preset logic. The generation of the driving logic circuit according to the control definition of the pins is a technology well known to those skilled in the art, and will not be described here. In this embodiment, the step of generating the driving logic of all basic control signals of each pin with the preset logic according to all control definitions of each pin includes: the drive logic of each basic control signal is driven by one or more enabled multiplexing function selection logic OR; the extended control signal and multiplexing function select logic AND drive. The multiplexing function selects logic OR driving, so that only one multiplexing function of the multiplexing function is enabled at the same time, and the expansion control signal and the multiplexing function select logic AND driving indicate that the multiplexing function and the expansion control signal need to act simultaneously to realize the functions of the pins, thereby avoiding the confusion of multiplexing function control.
As can be seen from the above, the method for generating the chip pin function multiplexing circuit of the present invention separately processes the mapping relation between functions and pins and the mapping relation between functions and control signals, thereby avoiding the problems of easy error and high labor cost in the IO pin multiplexing implementation in the prior art, and when the multiplexing function of pins is modified, only the names of the multiplexing functions need to be understood, so that the labor cost of the IO multiplexing design is greatly reduced and the working efficiency is improved.
Computer apparatus embodiment:
the computer device of the present embodiment includes a controller, and the controller implements the steps in the above-described embodiment of the method for generating the chip pin function multiplexing circuit when executing the computer program.
For example, a computer program may be split into one or more modules, one or more modules stored in a memory and executed by a controller to perform the present invention. One or more modules may be a series of computer program instruction segments capable of performing particular functions to describe the execution of a computer program in a computer device.
Computer devices may include, but are not limited to, controllers, memories. Those skilled in the art will appreciate that a computer apparatus may include more or fewer components, or may combine certain components, or different components, e.g., a computer apparatus may also include input and output devices, network access devices, buses, etc.
For example, the controller may be a central processing unit (Central Processing Unit, CPU), but may also be other general purpose controllers, digital signal controllers (Digital Signal Processor, DSP), application specific integrated circuits (Application Specific Integrated Circuit, ASIC), off-the-shelf programmable gate arrays (Field Programmable Gate Array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or the like. The general controller may be a microcontroller or the controller may be any conventional controller or the like. The controller is the control center of the computer device and connects the various parts of the entire computer device using various interfaces and lines.
The memory may be used to store computer programs and/or modules, and the controller implements various functions of the computer device by running or executing the computer programs and/or modules stored in the memory, and invoking data stored in the memory. For example, the memory may mainly include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function, and the like. In addition, the memory may include high-speed random access memory, and may also include non-volatile memory, such as a hard disk, memory, plug-in hard disk, smart Media Card (SMC), secure Digital (SD) Card, flash Card (Flash Card), at least one disk storage device, flash memory device, or other volatile solid-state storage device.
Computer-readable storage medium embodiments:
the modules integrated with the computer apparatus of the above embodiments may be stored in a computer-readable storage medium if implemented in the form of software functional units and sold or used as a stand-alone product. With such understanding, implementing all or part of the flow of the above-described chip pin function multiplexing circuit generation method embodiment may also be accomplished by instructing the relevant hardware by a computer program, which may be stored in a computer-readable storage medium, and which, when executed by a controller, may implement the steps of the above-described chip pin function multiplexing circuit generation method embodiment. Wherein the computer program comprises computer program code, which may be in the form of source code, object code, executable files or in some intermediate form, etc. The storage medium may include: any entity or device capable of carrying computer program code, a recording medium, a U disk, a removable hard disk, a magnetic disk, an optical disk, a computer Memory, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), an electrical carrier signal, a telecommunications signal, a software distribution medium, and so forth. It should be noted that the content of the computer readable medium can be appropriately increased or decreased according to the requirements of the jurisdiction's jurisdiction and the patent practice, for example, in some jurisdictions, the computer readable medium does not include electrical carrier signals and telecommunication signals according to the jurisdiction and the patent practice.
It should be noted that the foregoing is only a preferred embodiment of the present invention, but the design concept of the present invention is not limited thereto, and any insubstantial modifications made to the present invention by using the concept fall within the scope of the present invention.
Claims (9)
1. A method for generating a chip pin function multiplexing circuit is characterized by comprising the following steps: comprising the following steps:
setting a function pin mapping table and a function signal mapping table, wherein the function pin mapping table comprises a pin name, a function multiplexing number and a multiplexing function name, the pin name is a row label of the function pin mapping table, the function multiplexing number is a column label of the function pin mapping table, the row column number where the multiplexing function name is located represents the multiplexing number of the multiplexing function name in a pin, the function signal mapping table comprises a multiplexing function name, a pin control signal name and a pin control signal setting, the multiplexing function name is a row label of the function signal mapping table, the pin control signal name is a column label of the function signal mapping table, and the pin control signal setting represents how a multiplexing function processes a control signal of a multiplexing pin;
acquiring the multiplexing function name corresponding to each pin according to the function pin mapping table, searching the function signal mapping table by taking the multiplexing function name as an index, and acquiring all control definitions of each pin;
and the driving logic circuit is used for generating all basic control signals of each pin by preset logic according to the total control definition of each pin.
2. The method for generating a chip pin function multiplexing circuit according to claim 1, wherein:
the step of setting the function pin mapping table and the function signal mapping table includes:
the same multiplexing function name appears in different pin names and different multiplexing numbers and/or in different multiplexing numbers of the same pin name.
3. The method for generating a chip pin function multiplexing circuit according to claim 1, wherein:
the step of setting the function pin mapping table and the function signal mapping table includes:
the same group of functional signals are allocated to the same multiplexing number of different pins.
4. The method for generating a chip pin function multiplexing circuit according to claim 1, wherein:
the step of setting the function pin mapping table and the function signal mapping table includes:
each pin is provided with the same number of function multiplexing numbers.
5. The chip pin function multiplexing circuit generating method according to any one of claims 1 to 4, wherein:
the pin control signals comprise basic control signals and expansion control signals, wherein the expansion control signals represent how to expand the processing modes of the basic control signals.
6. The method for generating a chip pin function multiplexing circuit according to claim 5, wherein:
the step of generating the driving logic of all basic control signals of each pin with preset logic according to the total control definition of each pin comprises the following steps:
the driving logic circuit of each basic control signal is driven by a plurality of enabled multiplexing function selection logic OR;
the extended control signal and the multiplexing function select logic AND drive.
7. The chip pin function multiplexing circuit generating method according to any one of claims 1 to 4, wherein:
the step of searching the function signal mapping table by taking the multiplexing function name as an index comprises the following steps:
and traversing the function signal mapping table, judging whether the multiplexing function name of the current index exists or not, and if not, sending prompt information.
8. A computer apparatus comprising a processor and a memory, characterized in that: the memory stores a computer program which, when executed by the processor, implements the steps of the chip pin function multiplexing circuit generation method according to any one of claims 1 to 7.
9. A computer-readable storage medium having stored thereon a computer program, characterized by: the computer program when executed by a controller implements the steps of the chip pin function multiplexing circuit generation method according to any one of claims 1 to 7.
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