CN108153373B - Baseband data generation method and generation system with any sampling rate - Google Patents
Baseband data generation method and generation system with any sampling rate Download PDFInfo
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Abstract
The invention relates to a baseband data generating method and a generating system with any sampling rate, which are realized by adopting a baseband data generating system, wherein the baseband data generating system comprises an FPGA, a digital-to-analog conversion module and a level processing module, the FPGA generates sine wave signals according to the code rate, the frequency division coefficient and the frequency multiplication coefficient of baseband signals, the filtered sine wave signals are used as an input clock of the FPGA to generate clock signals with the frequency same as the code rate value of the baseband signals, and uniform output of the baseband data is realized.
Description
Technical Field
The invention relates to a baseband data generation method and a baseband data generation system with any sampling rate, and belongs to the field of signal processing.
Background
In the existing signal sampling design, in order to adapt to the requirement of continuously variable data code rate, one method is to change the sampling rate of the DAC by adopting reconfiguration parameters according to the code rate of transmission data, so that the number of sampling points is fixed and unchanged, and the method is complex to realize, is limited by a hardware platform and has low practicability; the other method is to adopt an interpolation filter to carry out fractional multiple interpolation, and the method has complex design and large consumption of hardware resources when the data code rate is high, and cannot be widely applied.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides a baseband data generation method with any sampling rate.
It is another object of the present invention to provide a baseband data generating system of an arbitrary sampling rate.
The above purpose of the invention is mainly realized by the following technical scheme:
a baseband data generating method with any sampling rate is realized by adopting a baseband data generating system, the baseband data generating system comprises an FPGA, a digital-to-analog conversion module and a level processing module, and the specific realizing method comprises the following steps:
step (1), FPGA according to the code rate R of the baseband signalbAnd a first frequency division coefficient D and a first frequency multiplication coefficient M, the generated frequency being f1And sending the sine wave signal to a digital-to-analog conversion module, wherein the frequency f is1Satisfy Q1≤f1≤Q2Wherein Q is1、Q2Are respectively the frequency f1Lower and upper limit values of;
step (2), the digital-to-analog conversion module enables the frequency received from the FPGA to be f1The sine wave signal is converted into an analog signal from a digital signal, and the analog signal is sent to a level processing module;
step (3), the level processing module receives the frequency f from the digital-to-analog conversion module1The analog signal of (2) is filtered, and the frequency after filtering is f1The analog signal of (a) is used as an input clock of the FPGA;
step (4), the frequency output by the FPGA receiving level processing module is f1According to a second frequency division coefficient D 'and a second frequency multiplication coefficient M', and the frequency isf1Generating a clock signal of frequency f2And satisfies the frequency f2Value of (d) and code rate R of baseband signalbThe values of (A) are the same; the FPGA is f according to the frequency2The clock signal of (2) collects the baseband signal and outputs the baseband signal outwards.
In the above method for generating baseband data at any sampling rate, in step (1), the FPGA may generate the code rate R according to the baseband signalbAnd a first frequency division coefficient D and a first frequency multiplication coefficient M, the generated frequency being f1The sine wave signal of (2) is specifically as follows:
(1.1) the code rate R of the FPGA according to the baseband signalbAnd a first frequency division coefficient D and a first frequency multiplication coefficient M, calculating the frequency f of the sine wave signal1The concrete formula is as follows:
(1.2) frequency f according to sine wave signal1And a reference clock frequency f0And calculating the step quantity FCW of the NCO, wherein the specific formula is as follows:
wherein: n is NCO digit;
(1.3) frequency f of generation of FCW according to the amount of NCO stepping1A sine wave signal of (1).
In the above method for generating baseband data at an arbitrary sampling rate, the frequency f in the step (1)1F is less than or equal to 10MHz1≤20MHz。
In the above baseband data generating method with any sampling rate, in the step (4), the frequency output by the FPGA reception level processing module is f1According to a second frequency division coefficient D 'and a second frequency multiplication coefficient M', and said frequency is f1Generating a clock signal of frequency f2Of a clock signal of, wherein the frequency f2Calculated by the following formula:
in the above baseband data generation method with any sampling rate, in the step (4), the FPGA generates the frequency f through the phase-locked loop2The clock signal of (2).
In the above baseband data generating method with any sampling rate, the FPGA includes a coefficient generating module, a sine wave signal generating module, a clock signal generating module, and a baseband signal generating module, where:
a coefficient generation module: generating a first frequency division coefficient D and a first frequency multiplication coefficient M, and outputting the first frequency division coefficient D and the first frequency multiplication coefficient M to a sine wave signal generation module; generating a second frequency dividing coefficient D 'and a second frequency multiplying coefficient M' and outputting the second frequency dividing coefficient D 'and the second frequency multiplying coefficient M' to a clock signal generating module;
the sine wave signal generation module: receiving a first frequency division coefficient D and a first frequency multiplication coefficient M output by the coefficient generation module according to the code rate R of the baseband signalbCalculating the frequency f of the sine wave signal1The concrete formula is as follows:
according to the frequency f of the sine-wave signal1And a reference clock frequency f0And calculating the step quantity FCW of the NCO, wherein the specific formula is as follows:
wherein: n is NCO digit;
the frequency of generation of FCW is f according to the step quantity of NCO1The sine wave signal of (1); outputting the sine wave signal to a digital-to-analog conversion module;
a clock signal generation module: the second frequency dividing coefficient D 'and the second frequency doubling coefficient M' output by the receiving coefficient generating module, and the frequency output by the receiving level processing module is f1Generating a clock signal of frequency f2Outputs the clock signal to the baseband signal generating module and satisfies the frequency f2Value of (d) and code rate R of baseband signalbAre the same, wherein the frequency f2Calculated by the following formula:
a baseband signal generation module: the frequency of the output of the receiving clock signal generating module is f2According to said frequency f2The clock signal of (2) collects the baseband signal and outputs the baseband signal outwards.
In the above method for generating baseband data at an arbitrary sampling rate, the first frequency-division coefficient D is equal to the second frequency-division coefficient M ', and the first frequency-division coefficient M is equal to the second frequency-division coefficient D'.
In the method for generating baseband data at any sampling rate, the specific method for generating the first frequency division coefficient D and the first frequency multiplication coefficient M by the FPGA in step (1) is as follows:
(1.1) order M0＝1；
(1.2) order
i＝0、1、2……；
(1.3) if B-A>1, then M ═ Mi(ii) a Entering the step (1.5);
(1.4) if B-A is less than or equal to 1, then adding Mi+1 assignment to MiAnd returning to the step (1.2);
and (1.5) D is B rounded down.
In the above baseband data generation method with any sampling rate, in the step (4), the FPGA generates the second frequency division coefficient D 'to take the value as the first frequency multiplication coefficient M, and the second frequency multiplication coefficient M' takes the value as the first frequency division coefficient D.
A baseband data generation system with any sampling rate comprises an FPGA, a digital-to-analog conversion module and a level processing module, wherein:
FPGA: code rate R from baseband signalbAnd a first frequency division coefficient D and a first frequency multiplication coefficient M, the generated frequency being f1And the sine wave signal is converted into a sine wave signalSending the frequency f to a digital-to-analog conversion module1Satisfy Q1≤f1≤Q2Wherein Q is1、Q2Are respectively the frequency f1Lower and upper limit values of; the frequency of the output of the receiving level processing module is f1According to a second frequency division coefficient D 'and a second frequency multiplication coefficient M', and said frequency is f1Generating a clock signal of frequency f2And satisfies the frequency f2Value of (d) and code rate R of baseband signalbThe values of (A) are the same; according to said frequency being f2The clock signal of the system is collected and the baseband signal is output outwards;
a digital-to-analog conversion module: frequency f to be received from FPGA1The sine wave signal is converted into an analog signal from a digital signal, and the analog signal is sent to a level processing module;
the level processing module: frequency f to be received from the D/A conversion module1The analog signal of (2) is filtered, and the frequency after filtering is f1As an input clock to the FPGA.
In the above baseband data generating system with any sampling rate, the FPGA includes a coefficient generating module, a sine wave signal generating module, a clock signal generating module, and a baseband signal generating module, where:
a coefficient generation module: generating a first frequency division coefficient D and a first frequency multiplication coefficient M, and outputting the first frequency division coefficient D and the first frequency multiplication coefficient M to a sine wave signal generation module; generating a second frequency dividing coefficient D 'and a second frequency multiplying coefficient M' and outputting the second frequency dividing coefficient D 'and the second frequency multiplying coefficient M' to a clock signal generating module;
the sine wave signal generation module: receiving a first frequency division coefficient D and a first frequency multiplication coefficient M output by the coefficient generation module according to the code rate R of the baseband signalbCalculating the frequency f of the sine wave signal1The concrete formula is as follows:
according to the frequency f of the sine-wave signal1And a reference clock frequency f0Step of calculating NCOThe feed quantity FCW is specifically defined as follows:
wherein: n is NCO digit;
the frequency of generation of FCW is f according to the step quantity of NCO1The sine wave signal of (1); outputting the sine wave signal to a digital-to-analog conversion module;
a clock signal generation module: the second frequency dividing coefficient D 'and the second frequency doubling coefficient M' output by the receiving coefficient generating module, and the frequency output by the receiving level processing module is f1Generating a clock signal of frequency f2Outputs the clock signal to the baseband signal generating module and satisfies the frequency f2Value of (d) and code rate R of baseband signalbAre the same, wherein the frequency f2Calculated by the following formula:
a baseband signal generation module: the frequency of the output of the receiving clock signal generating module is f2According to said frequency f2The clock signal of (2) collects the baseband signal and outputs the baseband signal outwards.
Compared with the prior art, the invention has the advantages that:
(1) the FPGA generates sine wave signals according to the code rate of the baseband signals, the frequency division coefficient and the frequency multiplication coefficient, the filtered sine wave signals are used as input clocks of the FPGA to generate clock signals with the frequency being the same as the code rate of the baseband signals, and uniform output of baseband data is achieved.
(2) The invention calculates the output signal clock in real time according to the signal code rate, not only can meet the requirement of continuously variable code rate, but also is suitable for a system with higher transmission data code rate.
(3) The invention realizes the generation of the sine wave signal after frequency division and frequency multiplication through the NCO, not only has high precision frequency, but also has simple realization method, and reduces the complexity of system realization.
(4) The invention consumes less hardware resources, can effectively overcome the limitation of a hardware platform in the prior art, and reduces the cost.
(5) The invention provides a method for generating the frequency division coefficient and the frequency multiplication coefficient, and realizes the dynamic configuration of the frequency division coefficient and the frequency multiplication coefficient;
(6) the method and the system for generating the baseband data are suitable for systems which have wide code rate range and high code rate and need accurate sampling, such as high-speed data transmission systems and the like, and particularly have few sampling points for transmitting the data.
Drawings
FIG. 1 is a schematic diagram illustrating the principle of the method for generating baseband data at an arbitrary sampling rate according to the present invention;
fig. 2 is a structural diagram of a baseband data generating system with an arbitrary sampling rate according to the present invention.
Detailed Description
The invention is described in further detail below with reference to the following figures and specific examples:
fig. 1 is a schematic diagram showing a principle of a baseband data generating method of any sampling rate of the present invention, and fig. 2 is a structural composition diagram showing a baseband data generating system of any sampling rate of the present invention, the baseband data generating method of any sampling rate of the present invention is implemented by a baseband data generating system, the baseband data generating system includes an FPGA, a digital-to-analog conversion module and a level processing module, and the specific implementation method includes the following steps:
step (1), FPGA according to the code rate R of the baseband signalbAnd a first frequency division coefficient D and a first frequency multiplication coefficient M, the generated frequency being f1And sending the sine wave signal to a digital-to-analog conversion module, wherein the frequency f is1Satisfy Q1≤f1≤Q2Wherein Q is1、Q2Are respectively the frequency f1Lower and upper limit values of; frequency f in the embodiment of the present invention1F is less than or equal to 10MHz1≤20MHz。
Wherein: code rate R of FPGA according to baseband signalbAnd a first frequency division coefficient D and a first frequency multiplication coefficient M, the generated frequency being f1The sine wave signal of (2) is specifically as follows:
(1.1) the code rate R of the FPGA according to the baseband signalbAnd a first frequency division coefficient D and a first frequency multiplication coefficient M, calculating the frequency f of the sine wave signal1The concrete formula is as follows:
(1.2) frequency f according to sine wave signal1And a reference clock frequency f0And calculating the step quantity FCW of the NCO, wherein the specific formula is as follows:
wherein: n is NCO digit;
(1.3) generating a frequency f by looking up a phase amplitude table according to the step quantity FCW of the NCO1A sine wave signal of (1).
The specific method for generating the first frequency division coefficient D and the first frequency multiplication coefficient M by the FPGA comprises the following steps:
(1.1) order M0＝1；
(1.2) order
i＝0、1、2……；
(1.3) if B-A>1, then M ═ Mi(ii) a Entering the step (1.5);
(1.4) if B-A is less than or equal to 1, then adding Mi+1 assignment to MiInstant Mi＝Mi+1, return to step (1.2);
and (1.5) D is B, rounding down, and finishing.
For example: if when M is presenti＝M0When it is satisfied with B-A>1, then M ═ Mi＝M0D is B rounded down when 1, otherwise, let M1＝M0+1 ═ 2, and Mi＝M1Substituted into public in step (1.2)Calculated in the formula, if B-A is satisfied>1, then M ═ Mi＝M1D is B rounded downward as 2; otherwise, let M2＝M1+1 ═ 3, and Mi＝M2And substituting into the formula in the step (1.2) to calculate … …, and so on.
Step (2), the digital-to-analog conversion module enables the frequency received from the FPGA to be f1The sine wave signal is converted into an analog signal from a digital signal, and the analog signal is sent to the level processing module.
Step (3), the level processing module receives the frequency f from the digital-to-analog conversion module1The analog signal of (2) is filtered, and the frequency after filtering is f1The analog signal of (2) is output to a global clock pin of the FPGA to be used as an input clock of the FPGA.
Step (4), the frequency output by the FPGA receiving level processing module is f1According to a second frequency division coefficient D 'and a second frequency multiplication coefficient M', and said frequency is f1By a phase-locked loop, generating a clock signal of frequency f2And satisfies the frequency f2Value of (d) and code rate R of baseband signalbThe values of (A) are the same; the FPGA is f according to the frequency2The clock signal of (2) collects the baseband signal and outputs the baseband signal outwards.
In the invention, the FPGA generates a second frequency division coefficient D 'which takes the value as a first frequency multiplication coefficient M, and the second frequency multiplication coefficient M' takes the value as the first frequency division coefficient D.
Wherein the frequency f2Calculated by the following formula:
as shown in fig. 1, the FPGA includes a coefficient generation module, a sine wave signal generation module, a clock signal generation module, and a baseband signal generation module, wherein:
a coefficient generation module: generating a first frequency division coefficient D and a first frequency multiplication coefficient M, and outputting the first frequency division coefficient D and the first frequency multiplication coefficient M to a sine wave signal generation module; generating a second frequency dividing coefficient D 'and a second frequency multiplying coefficient M' and outputting the second frequency dividing coefficient D 'and the second frequency multiplying coefficient M' to a clock signal generating module;
sine wave signal generation module (NCO included): receiving a first frequency division coefficient D and a first frequency multiplication coefficient M output by the coefficient generation module according to the code rate R of the baseband signalbCalculating the frequency f of the sine wave signal1The concrete formula is as follows:
according to the frequency f of the sine-wave signal1And a reference clock frequency f0And calculating the step quantity FCW of the NCO, wherein the specific formula is as follows:
wherein: n is NCO digit;
the frequency of generation of FCW is f according to the step quantity of NCO1The sine wave signal of (1); outputting the sine wave signal to a digital-to-analog conversion module;
a clock signal generation module: the second frequency dividing coefficient D 'and the second frequency doubling coefficient M' output by the receiving coefficient generating module, and the frequency output by the receiving level processing module is f1Generating a clock signal of frequency f2Outputs the clock signal to the baseband signal generating module and satisfies the frequency f2Value of (d) and code rate R of baseband signalbAre the same, wherein the frequency f2Calculated by the following formula:
a baseband signal generation module: the frequency of the output of the receiving clock signal generating module is f2According to said frequency f2The clock signal of (2) collects the baseband signal and outputs the baseband signal outwards.
The baseband data generating system with any sampling rate comprises an FPGA, a digital-to-analog conversion module and a level processing module, wherein:
FPGA: code rate R from baseband signalbAnd a first frequency division coefficient D and a first frequency multiplication coefficient M, the generated frequency being f1And sending the sine wave signal to a digital-to-analog conversion module, wherein the frequency f is1Satisfy Q1≤f1≤Q2Wherein Q is1、Q2Are respectively the frequency f1Lower and upper limit values of; the frequency of the output of the receiving level processing module is f1According to a second frequency division coefficient D 'and a second frequency multiplication coefficient M', and said frequency is f1Generating a clock signal of frequency f2And satisfies the frequency f2Value of (d) and code rate R of baseband signalbThe values of (A) are the same; according to said frequency being f2The clock signal of the system is collected and the baseband signal is output outwards;
a digital-to-analog conversion module: frequency f to be received from FPGA1The sine wave signal is converted into an analog signal from a digital signal, and the analog signal is sent to a level processing module;
the level processing module: frequency f to be received from the D/A conversion module1The analog signal of (2) is filtered, and the frequency after filtering is f1As an input clock to the FPGA.
The FPGA comprises a coefficient generation module, a sine wave signal generation module, a clock signal generation module and a baseband signal generation module, wherein:
a coefficient generation module: generating a first frequency division coefficient D and a first frequency multiplication coefficient M, and outputting the first frequency division coefficient D and the first frequency multiplication coefficient M to a sine wave signal generation module; generating a second frequency dividing coefficient D 'and a second frequency multiplying coefficient M' and outputting the second frequency dividing coefficient D 'and the second frequency multiplying coefficient M' to a clock signal generating module;
the sine wave signal generation module: receiving a first frequency division coefficient D and a first frequency multiplication coefficient M output by the coefficient generation module according to the code rate R of the baseband signalbCalculating the frequency f of the sine wave signal1The concrete formula is as follows:
according to the sineFrequency f of wave signal1And a reference clock frequency f0And calculating the step quantity FCW of the NCO, wherein the specific formula is as follows:
wherein: n is NCO digit;
generating a frequency f by looking up a phase-amplitude table based on the step quantity FCW of the NCO1The sine wave signal of (1); and outputting the sine wave signal to a digital-to-analog conversion module.
A clock signal generation module: the second frequency dividing coefficient D 'and the second frequency doubling coefficient M' output by the receiving coefficient generating module, and the frequency output by the receiving level processing module is f1Generating a clock signal of frequency f2Outputs the clock signal to the baseband signal generating module and satisfies the frequency f2Value of (d) and code rate R of baseband signalbAre the same, wherein the frequency f2Calculated by the following formula:
a baseband signal generation module: the frequency of the output of the receiving clock signal generating module is f2According to said frequency f2The clock signal of (2) collects the baseband signal and outputs the baseband signal outwards.
Example (b):
in this embodiment, the code rate R of the input signalbSet to 299Mbps, reference clock frequency f0Setting the number of NCO digits to be 32 digits at 150Mbps, calculating the frequency division coefficient D to be 20, the frequency multiplication coefficient M to be 1, and the NCO step quantity FCW to be
With NCO generating a frequency of f1After the sine wave signal of 14.95MHz is output from DAC, the sine wave signal is input from FPGA global clock pin after passing through level processing module, and is used as FPGA input clock, according to the clock signal, the FPGA is equipped with the sine wave signalSetting the frequency multiplication coefficient M to be 20 and the frequency division coefficient D to be 1 to obtain the frequency f2299MHz clock signal, using frequency f2The baseband signal is generated by the 299MHz clock signal, so that the uniform output of the signal can be realized.
The invention adopts the baseband data generation method for changing the clock of the output signal according to the signal code rate, realizes the uniform output of signals with different code rates, realizes the code rate range of 1kbps to 300Mbps, has simple whole realization process, saves resources and improves the communication performance of the system. The method is realized by engineering, is applied to a plurality of projects such as high-speed data transmission and the like, and obtains good application effect.
The above description is only for the best mode of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention.
Those skilled in the art will appreciate that those matters not described in detail in the specification are well known in the art.
Claims (10)
1. A baseband data generation method with any sampling rate is characterized in that: the method is realized by adopting a baseband data generation system, the baseband data generation system comprises an FPGA, a digital-to-analog conversion module and a level processing module, and the specific realization method comprises the following steps:
step (1), FPGA according to the code rate R of the baseband signalbAnd a first frequency division coefficient D and a first frequency multiplication coefficient M, the generated frequency being f1And sending the sine wave signal to a digital-to-analog conversion module, wherein the frequency f is1Satisfy Q1≤f1≤Q2Wherein Q is1、Q2Are respectively the frequency f1Lower and upper limit values of;
step (2), the digital-to-analog conversion module enables the frequency received from the FPGA to be f1The sine wave signal is converted into an analog signal from a digital signal, and the analog signal is sent to a level processing module;
step (ii) of(3) The level processing module receives the frequency f from the digital-to-analog conversion module1The analog signal of (2) is filtered, and the frequency after filtering is f1The analog signal of (a) is used as an input clock of the FPGA;
step (4), the frequency output by the FPGA receiving level processing module is f1According to a second frequency division coefficient D 'and a second frequency multiplication coefficient M', and said frequency is f1Generating a clock signal of frequency f2And satisfies the frequency f2Value of (d) and code rate R of baseband signalbThe values of (A) are the same; the FPGA is f according to the frequency2The clock signal of the system is collected and the baseband signal is output outwards;
the first frequency multiplication coefficient M is equal to the second frequency multiplication coefficient M ', and the first frequency multiplication coefficient M is equal to the second frequency multiplication coefficient D'.
2. The method of generating baseband data at an arbitrary sampling rate according to claim 1, wherein: the code rate R of the FPGA according to the baseband signal in the step (1)bAnd a first frequency division coefficient D and a first frequency multiplication coefficient M, the generated frequency being f1The sine wave signal of (2) is specifically as follows:
(1.1) the code rate R of the FPGA according to the baseband signalbAnd a first frequency division coefficient D and a first frequency multiplication coefficient M, calculating the frequency f of the sine wave signal1The concrete formula is as follows:
(1.2) frequency f according to sine wave signal1And a reference clock frequency f0And calculating the step quantity FCW of the NCO, wherein the specific formula is as follows:
wherein: n is NCO digit;
(1.3) frequency f of generation of FCW according to the amount of NCO stepping1A sine wave signal of (1).
3. The method of generating baseband data at an arbitrary sampling rate according to claim 1, wherein: frequency f in the step (1)1F is less than or equal to 10MHz1≤20MHz。
4. The method of generating baseband data at an arbitrary sampling rate according to claim 1, wherein: the frequency output by the FPGA receiving level processing module in the step (4) is f1According to a second frequency division coefficient D 'and a second frequency multiplication coefficient M', and said frequency is f1Generating a clock signal of frequency f2Of a clock signal of, wherein the frequency f2Calculated by the following formula:
5. the method of generating baseband data at an arbitrary sampling rate according to claim 4, wherein: the FPGA in the step (4) generates the frequency f through the phase-locked loop2The clock signal of (2).
6. The method for generating baseband data at an arbitrary sampling rate according to any one of claims 1 to 5, comprising: the FPGA comprises a coefficient generation module, a sine wave signal generation module, a clock signal generation module and a baseband signal generation module, wherein:
a coefficient generation module: generating a first frequency division coefficient D and a first frequency multiplication coefficient M, and outputting the first frequency division coefficient D and the first frequency multiplication coefficient M to a sine wave signal generation module; generating a second frequency dividing coefficient D 'and a second frequency multiplying coefficient M' and outputting the second frequency dividing coefficient D 'and the second frequency multiplying coefficient M' to a clock signal generating module;
the sine wave signal generation module: receiving a first frequency division coefficient D and a first frequency multiplication coefficient M output by the coefficient generation module according to the code rate R of the baseband signalbCalculating the frequency f of the sine wave signal1The concrete formula is as follows:
according to the frequency f of the sine-wave signal1And a reference clock frequency f0And calculating the step quantity FCW of the NCO, wherein the specific formula is as follows:
wherein: n is NCO digit;
the frequency of generation of FCW is f according to the step quantity of NCO1The sine wave signal of (1); outputting the sine wave signal to a digital-to-analog conversion module;
a clock signal generation module: the second frequency dividing coefficient D 'and the second frequency doubling coefficient M' output by the receiving coefficient generating module, and the frequency output by the receiving level processing module is f1Generating a clock signal of frequency f2Outputs the clock signal to the baseband signal generating module and satisfies the frequency f2Value of (d) and code rate R of baseband signalbAre the same, wherein the frequency f2Calculated by the following formula:
a baseband signal generation module: the frequency of the output of the receiving clock signal generating module is f2According to said frequency f2The clock signal of (2) collects the baseband signal and outputs the baseband signal outwards.
7. The method for generating baseband data at an arbitrary sampling rate according to any one of claims 1 to 5, comprising: the specific method for generating the first frequency division coefficient D and the first frequency multiplication coefficient M by the FPGA in the step (1) is as follows:
(1.1) order M0＝1；
(1.2) order
(1.3) if B-A>1, then M ═ Mi(ii) a Entering the step (1.5);
(1.4) if B-A is less than or equal to 1, then adding Mi+1 assignment to MiAnd returning to the step (1.2);
and (1.5) D is B rounded down.
8. The method of generating baseband data at an arbitrary sampling rate according to claim 7, wherein: and (4) generating a second frequency division coefficient D 'by the FPGA to be a first frequency multiplication coefficient M, wherein the second frequency multiplication coefficient M' is a first frequency division coefficient D.
9. An arbitrary sampling rate baseband data generation system, characterized by: including FPGA, digital-to-analog conversion module and level processing module, wherein:
FPGA: code rate R from baseband signalbAnd a first frequency division coefficient D and a first frequency multiplication coefficient M, the generated frequency being f1And sending the sine wave signal to a digital-to-analog conversion module, wherein the frequency f is1Satisfy Q1≤f1≤Q2Wherein Q is1、Q2Are respectively the frequency f1Lower and upper limit values of; the frequency of the output of the receiving level processing module is f1According to a second frequency division coefficient D 'and a second frequency multiplication coefficient M', and said frequency is f1Generating a clock signal of frequency f2And satisfies the frequency f2Value of (d) and code rate R of baseband signalbThe values of (A) are the same; according to said frequency being f2The clock signal of the system is collected and the baseband signal is output outwards;
a digital-to-analog conversion module: frequency f to be received from FPGA1The sine wave signal is converted into an analog signal from a digital signal, and the analog signal is sent to a level processing module;
the level processing module: frequency f to be received from the D/A conversion module1The analog signal of (2) is filtered, and the frequency after filtering is f1The analog signal of (a) is used as an input clock of the FPGA;
the first frequency multiplication coefficient M is equal to the second frequency multiplication coefficient M ', and the first frequency multiplication coefficient M is equal to the second frequency multiplication coefficient D'.
10. The arbitrary-sample-rate baseband data generation system according to claim 9, wherein: the FPGA comprises a coefficient generation module, a sine wave signal generation module, a clock signal generation module and a baseband signal generation module, wherein:
a coefficient generation module: generating a first frequency division coefficient D and a first frequency multiplication coefficient M, and outputting the first frequency division coefficient D and the first frequency multiplication coefficient M to a sine wave signal generation module; generating a second frequency dividing coefficient D 'and a second frequency multiplying coefficient M' and outputting the second frequency dividing coefficient D 'and the second frequency multiplying coefficient M' to a clock signal generating module;
the sine wave signal generation module: receiving a first frequency division coefficient D and a first frequency multiplication coefficient M output by the coefficient generation module according to the code rate R of the baseband signalbCalculating the frequency f of the sine wave signal1The concrete formula is as follows:
according to the frequency f of the sine-wave signal1And a reference clock frequency f0And calculating the step quantity FCW of the NCO, wherein the specific formula is as follows:
wherein: n is NCO digit;
the frequency of generation of FCW is f according to the step quantity of NCO1The sine wave signal of (1); outputting the sine wave signal to a digital-to-analog conversion module;
a clock signal generation module: the second frequency dividing coefficient D 'and the second frequency doubling coefficient M' output by the receiving coefficient generating module, and the frequency output by the receiving level processing module is f1Generating a clock signal of frequency f2Outputs the clock signal to the baseband signal generating module and satisfies the frequency f2Value of (d) and code rate R of baseband signalbAre the same, wherein the frequency f2Calculated by the following formula:
a baseband signal generation module: the frequency of the output of the receiving clock signal generating module is f2According to said frequency f2The clock signal of (2) collects the baseband signal and outputs the baseband signal outwards.
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