CN108063663B - Video encryption transmission method, device and system - Google Patents
Video encryption transmission method, device and system Download PDFInfo
- Publication number
- CN108063663B CN108063663B CN201711377177.3A CN201711377177A CN108063663B CN 108063663 B CN108063663 B CN 108063663B CN 201711377177 A CN201711377177 A CN 201711377177A CN 108063663 B CN108063663 B CN 108063663B
- Authority
- CN
- China
- Prior art keywords
- bytes
- video
- encryption
- byte
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/001—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols using chaotic signals
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L63/00—Network architectures or network communication protocols for network security
- H04L63/04—Network architectures or network communication protocols for network security for providing a confidential data exchange among entities communicating through data packet networks
- H04L63/0428—Network architectures or network communication protocols for network security for providing a confidential data exchange among entities communicating through data packet networks wherein the data content is protected, e.g. by encrypting or encapsulating the payload
Landscapes
- Engineering & Computer Science (AREA)
- Computer Security & Cryptography (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Two-Way Televisions, Distribution Of Moving Picture Or The Like (AREA)
Abstract
The invention discloses a video encryption transmission method, which detects an identification bit corresponding to a byte in each pixel of a video in an HDMI format; only encrypting R bytes, G bytes and B bytes in each pixel and sending the encrypted R bytes, G bytes and B bytes to a receiving end, inserting the extended data for restoring the video format into the video data after the video data is received by the receiving end, and performing chaotic decryption on the video data inserted with the extended data; the R byte, the G byte, the B byte and the byte marking the extended data in each pixel correspond to different identification bits, and the bytes are detected, encrypted or decrypted according to the identification bits. Therefore, the data volume of the video data in the transmission process is reduced, the congestion of a transmission channel is avoided, and the transmission efficiency and the processing efficiency of the video data are improved. Accordingly, the video encryption transmission device, the video encryption transmission system, the video encryption transmission equipment and the computer readable storage medium disclosed by the invention also have the technical effects.
Description
Technical Field
The present invention relates to the field of data transmission technologies, and in particular, to a video encryption transmission method, apparatus, system, device, and computer-readable storage medium.
Background
With the development of video technology, video making, transmission and display technology is changing day by day, and the ornamental performance and comfort of the video are greatly improved.
However, as the image quality of video images is continuously improved, the data amount of the video images is also continuously increased, which brings certain challenges to video transmission. At present, each pixel of a video in the HDMI format at least includes four bytes, and if the video is encrypted by using the chaos theory during transmission, the communication security is greatly improved, but the real-time performance of transmission still needs to be improved. At present, people mainly research chaotic secret communication through numerical simulation, and videos have the characteristics of large data volume and strong real-time performance compared with voices and images, and easily block a transmission channel in the transmission process, so that the transmission efficiency is influenced, and the video is blocked.
Therefore, how to improve the transmission efficiency of video data is a problem to be solved by those skilled in the art.
Disclosure of Invention
The invention aims to provide a video encryption transmission method, a video encryption transmission device, a video encryption transmission system, video encryption transmission equipment and a computer readable storage medium, so as to improve the transmission efficiency of video data.
In order to achieve the above purpose, the embodiment of the present invention provides the following technical solutions:
a video encryption transmission method, comprising:
detecting an identification bit corresponding to a byte in each pixel of the video in the HDMI format;
when the identification bit corresponding to the byte is detected to be the enabling encryption, carrying out chaotic encryption on the byte corresponding to the enabling encryption identification bit;
transmitting video data containing a preset number of encrypted bytes to a receiving end so that the receiving end inserts extended data for recovering a video format into the video data, and performing chaotic decryption on the video data after the extended data is inserted;
wherein each pixel of the video comprises: the device comprises R bytes, G bytes, B bytes and bytes for marking extended data, wherein identification bits corresponding to the R bytes, the G bytes and the B bytes are encryption or decryption enabling, and identification bits corresponding to the bytes for marking the extended data are encryption or decryption forbidding.
The chaos decryption of the video data inserted with the extended data includes:
and when the receiving end detects that the identification bit corresponding to the byte in the video data inserted with the extended data is the enable decryption, performing chaotic decryption on the byte corresponding to the enable decryption identification bit.
Wherein, the transmitting the video data containing the preset number of encrypted bytes to the receiving end includes:
video data containing 1446 encrypted bytes is transmitted to the receiving end.
Before transmitting the video data containing 1446 encrypted bytes to the receiving end, the method further includes:
and storing the video data containing 1446 encrypted bytes into a preset buffer by using a VDMA module.
A video encryption transmission apparatus comprising:
the detection module is used for detecting an identification bit corresponding to a byte in each pixel of the video in the HDMI format;
the encryption module is used for carrying out chaotic encryption on the bytes corresponding to the enabled encryption identification bits when the identification bits corresponding to the bytes are detected to be enabled for encryption;
the device comprises an execution module, a receiving end and a processing module, wherein the execution module is used for transmitting video data containing a preset number of encrypted bytes to the receiving end so that the receiving end inserts extended data for recovering a video format into the video data and chaotically decrypts the video data inserted with the extended data;
wherein each pixel of the video comprises: the device comprises R bytes, G bytes, B bytes and bytes for marking extended data, wherein identification bits corresponding to the R bytes, the G bytes and the B bytes are encryption or decryption enabling, and identification bits corresponding to the bytes for marking the extended data are encryption or decryption forbidding.
Wherein the execution module is specifically configured to:
and when the receiving end detects that the identification bit corresponding to the byte in the video data inserted with the extended data is the enable decryption, performing chaotic decryption on the byte corresponding to the enable decryption identification bit.
Wherein the execution module is specifically configured to:
video data containing 1446 encrypted bytes is transmitted to the receiving end.
A video encryption transmission system comprising:
the device comprises a sending end, a receiving end and a processing end, wherein the sending end is used for detecting an identification bit corresponding to a byte in each pixel of the video in the HDMI format; when the identification bit corresponding to the byte is detected to be the enabling encryption, carrying out chaotic encryption on the byte corresponding to the enabling encryption identification bit; transmitting video data containing a preset number of encrypted bytes to a receiving end;
the receiving end is used for inserting the extended data for recovering the video format into the video data and performing chaotic decryption on the video data inserted with the extended data;
wherein each pixel of the video comprises: the device comprises R bytes, G bytes, B bytes and bytes for marking extended data, wherein identification bits corresponding to the R bytes, the G bytes and the B bytes are encryption or decryption enabling, and identification bits corresponding to the bytes for marking the extended data are encryption or decryption forbidding.
A video encryption transmission apparatus comprising:
a memory for storing a computer program;
a processor configured to implement the steps of the video encryption transmission method according to any one of the above items when executing the computer program.
A computer-readable storage medium having stored thereon a computer program which, when executed by a processor, carries out the steps of a video encryption transmission method as claimed in any one of the preceding claims.
According to the above scheme, the video encryption transmission method provided by the embodiment of the invention comprises the following steps: detecting an identification bit corresponding to a byte in each pixel of the video in the HDMI format; when the identification bit corresponding to the byte is detected to be the enabling encryption, carrying out chaotic encryption on the byte corresponding to the enabling encryption identification bit; transmitting video data containing a preset number of encrypted bytes to a receiving end so that the receiving end inserts extended data for recovering a video format into the video data, and performing chaotic decryption on the video data after the extended data is inserted; wherein each pixel of the video comprises: the device comprises R bytes, G bytes, B bytes and bytes for marking extended data, wherein identification bits corresponding to the R bytes, the G bytes and the B bytes are encryption or decryption enabling, and identification bits corresponding to the bytes for marking the extended data are encryption or decryption forbidding.
The method comprises the steps of detecting identification bits corresponding to bytes in each pixel of the video in the HDMI format; and only the bytes corresponding to the encryption enabling identification bits are subjected to chaotic encryption and transmitted, namely only the R bytes, the G bytes and the B bytes in each pixel are encrypted and transmitted to a receiving end, after the receiving end receives the video data, the receiving end inserts the extended data for recovering the video format into the video data, and performs chaotic decryption on the video data inserted with the extended data. Therefore, the data volume of the video data in the transmission process is reduced, the congestion of a transmission channel is avoided, and meanwhile, the transmission efficiency and the processing efficiency of the video data are improved.
Accordingly, the video encryption transmission device, the video encryption transmission system, the video encryption transmission equipment and the computer-readable storage medium provided by the embodiment of the invention also have the technical effects.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a flowchart of a video encryption transmission method according to an embodiment of the present invention;
fig. 2 is a flow chart of another video encryption transmission method according to the embodiment of the present invention;
fig. 3 is a schematic diagram of a video transmission system designed based on the video encryption transmission method provided by the embodiment of the invention;
fig. 4 is a schematic diagram of a video encryption transmission apparatus according to an embodiment of the present invention;
fig. 5 is a schematic diagram of a video encryption transmission system according to an embodiment of the present invention;
fig. 6 is a schematic diagram of a video encryption transmission apparatus according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The embodiment of the invention discloses a video encryption transmission method, a video encryption transmission device, a video encryption transmission system, video encryption transmission equipment and a computer readable storage medium, which are used for improving the transmission efficiency of video data.
Referring to fig. 1, an embodiment of the present invention provides a video encryption transmission method, including:
s101, detecting an identification bit corresponding to a byte in each pixel of the video in the HDMI format;
each pixel of the video comprises: the device comprises R bytes, G bytes, B bytes and bytes for marking extended data, wherein identification bits corresponding to the R bytes, the G bytes and the B bytes are encryption or decryption enabling, and identification bits corresponding to the bytes for marking the extended data are encryption or decryption forbidding.
Note that each pixel of the video in the HDMI format includes: the byte marking method comprises the following steps of R bytes, G bytes, B bytes and bytes for marking extended data, wherein each byte corresponds to different identification bits, and the identification bits can be preset according to needs. For example: presetting the identification bits corresponding to the R byte, the G byte and the B byte to be 1 constantly to indicate that encryption or decryption is enabled; the identification bit corresponding to the byte for marking the extended data is preset to be 0 constantly, which indicates that encryption or decryption is forbidden. Wherein, the identification bit occupies 1 byte; the extension data is all-zero extension data.
S102, when the identification bit corresponding to the byte is detected to be the enabling encryption, carrying out chaotic encryption on the byte corresponding to the enabling encryption identification bit;
specifically, when it is detected that the identification bit corresponding to the byte is enabled for encryption, a preset chaotic encryption algorithm may be used to perform chaotic encryption on the byte corresponding to the enabled encryption identification bit.
For example, the following chaotic encryption equation is adopted to perform chaotic encryption on the bytes corresponding to the encryption-enabled identification bits:
x, Y, Z are state variables, and o (k) is an encrypted video sequence, and its mathematical expression is:
wherein the key parameter aijThe size of (ij ═ 1, 2, 3) is:
and performing chaotic encryption on the R byte, the G byte and the B byte in each pixel by using the chaotic encryption equation, thereby realizing the encryption of the video data.
S103, transmitting the video data containing a preset number of encrypted bytes to a receiving end so that the receiving end inserts extended data for recovering a video format into the video data, and performing chaotic decryption on the video data after the extended data is inserted;
correspondingly, transmitting the video data containing the preset number of encrypted bytes to a receiving end, inserting the extended data for recovering the video format into the video data after the receiving end receives the video data, and performing chaotic decryption on the video data inserted with the extended data.
Specifically, the decryption equation corresponding to the chaotic encryption equation is as follows:
wherein k is 1, 2, 3, mkAnd
for the original video signal and the decrypted video signal, skAnd
a key sequence iteratively generated for an encryption equation and a decryption equation.
Under condition of matching key parameters, i.e.
It indicates that the decryption was successful, otherwise the decryption failed.
As can be seen, in the video encryption transmission method provided by this embodiment, the identification bit corresponding to the byte in each pixel of the video in the HDMI format is detected; and only the bytes corresponding to the encryption enabling identification bits are subjected to chaotic encryption and transmitted, namely only the R bytes, the G bytes and the B bytes in each pixel are encrypted and transmitted to a receiving end, after the receiving end receives the video data, the receiving end inserts the extended data for recovering the video format into the video data, and performs chaotic decryption on the video data inserted with the extended data. Therefore, the data volume of the video data in the transmission process is reduced, the congestion of a transmission channel is avoided, and meanwhile, the transmission efficiency and the processing efficiency of the video data are improved.
The embodiment of the invention discloses another video encryption transmission method, and compared with the previous embodiment, the technical scheme is further explained and optimized in the embodiment.
Referring to fig. 2, another video encryption transmission method provided in the embodiment of the present invention includes:
s201, detecting an identification bit corresponding to a byte in each pixel of the video in the HDMI format;
s202, when the identification bit corresponding to the byte is detected to be the enabling encryption, carrying out chaotic encryption on the byte corresponding to the enabling encryption identification bit;
s203, storing the video data containing 1446 encrypted bytes into a preset buffer area by adopting a VDMA module;
based on the above embodiment, before transmitting the video data containing 1446 encrypted bytes to the receiving end, the method further includes: and storing the video data containing 1446 encrypted bytes into a preset buffer by using a VDMA module.
Specifically, if the SOC platform and the AXIS protocol are used to implement video transmission, before transmitting video data, the VDMA module is used to store the video data containing 1446 encrypted bytes into a preset buffer, so that the processing efficiency of the video data can be effectively improved, and the transmission of the video data is facilitated.
S204, transmitting the video data containing 1446 encrypted bytes to a receiving end, so that the receiving end inserts extended data for recovering a video format into the video data, and chaotically decrypts the video data into which the extended data is inserted.
Based on the above embodiment, the transmitting the video data including the preset number of encrypted bytes to the receiving end includes: video data containing 1446 encrypted bytes is transmitted to the receiving end.
Specifically, in the case of the system hardware platform implemented by the SOC platform and the AXIS protocol, 1446 encrypted bytes are transmitted, so that the transmission efficiency reaches an optimal value.
As can be seen, in the video encryption transmission method provided by this embodiment, the identification bit corresponding to the byte in each pixel of the video in the HDMI format is detected; only the bytes corresponding to the encryption enabling identification bits are subjected to chaotic encryption, namely only the R bytes, the G bytes and the B bytes in each pixel are encrypted, the video data containing 1446 encrypted bytes are stored in a preset buffer area by adopting a VDMA (virtual disk access memory) module and transmitted to a receiving end, after the receiving end receives the video data, the receiving end inserts extension data for recovering the video format into the video data, and the video data inserted with the extension data are subjected to chaotic decryption. Therefore, the data volume of the video data in the transmission process is reduced, the congestion of a transmission channel is avoided, and meanwhile, the transmission efficiency and the processing efficiency of the video data are improved.
Based on any of the above embodiments, it should be noted that the performing chaotic decryption on the video data inserted with the extension data includes: and when the receiving end detects that the identification bit corresponding to the byte in the video data inserted with the extended data is the enable decryption, performing chaotic decryption on the byte corresponding to the enable decryption identification bit.
Specifically, according to a set chaotic encryption algorithm and a corresponding chaotic decryption algorithm, when a receiving end detects that an identification bit corresponding to a byte in the video data inserted with the extended data is enabled for decryption, the byte corresponding to the enabled decryption identification bit is subjected to chaotic decryption.
Based on any of the above embodiments, the following video transmission system can be designed by using the video encryption transmission method provided by the present invention:
referring to fig. 3, fig. 3 is a video transmission system designed based on the video encryption transmission method provided by the present invention, and the video transmission system includes: a sending end and a receiving end; wherein, the sending end includes: video acquisition, video display, video data encryption and video encryption data's transmission etc. the receiving terminal includes: video reception, video restoration, video decryption, video display and the like.
Specifically, the specific working process of the sending end is as follows: video data are collected through a camera, the collected video data are stored in a first buffer area through a first VDMA module and then transmitted to a first HDMI controller and displayed through an HDMI display; the second VDMA module transmits the video data in the first buffer area to the chaotic encryption module for chaotic encryption, and then the video data are stored in a second buffer area; the CPU1 in the ARM dual-core processor of the sending end extracts the encrypted video data to the first OCM, and the CPU2 in the ARM dual-core processor of the sending end sends the encrypted video data in the OCM to the receiving end through the network.
Specifically, the specific working process of the receiving end is as follows: the CPU0 in the ARM dual-core processor at the receiving end receives the encrypted video data to the second OCM, meanwhile, the CPU1 in the ARM dual-core processor at the receiving end inserts the extended data for recovering the video format into the encrypted video data, and stores the encrypted video with the inserted extended data to a third buffer area; the third VDMA module transmits the video data stored in the third buffer area to the chaotic decryption module for chaotic decryption, and stores the decrypted video data in a fourth buffer area; and the fourth VDMA module transmits the decrypted video in the fourth buffer to the HDMI display for displaying.
The video transmission system is realized based on SOC and AXIS protocols, video acquisition, HDMI display, chaotic encryption, chaotic decryption and the like are realized through an FPGA, and the AXIS protocols are adopted among modules for data interaction. When the keys of the sending end and the receiving end are matched, the receiving end correctly decrypts and displays, and decryption fails under the mismatch condition.
The video transmission system is designed by adopting an SOC embedded platform and an AXIS interface protocol, wherein a main control chip of the SOC platform is a programmable SOC chip ZYNQ 0702 of Xilinx company, and an ARM Cortex A9 processor and an FPGA logic gate are arranged on the chip. The AXIS protocol is an industry-level standard defined by ARM corporation, and seamless compatibility can be realized between ip (intelligent performance) modules having such interface protocols.
The video in the system adopts an HDMI format, each pixel comprises 4 bytes including R bytes, G bytes, B bytes and an extension byte, wherein the extension byte controls the transparency of the video, and the R bytes, the G bytes and the B bytes control the display content of the video. The video is carried out in a frame unit and in a pixel stream mode in the transmission process of the VDMA; the video is processed in units of frames and in the form of byte streams in the process of encryption and decryption. The pixel stream is formed by arranging the video images from top to bottom and from left to right, and the data bus is 4 bytes; the byte stream is obtained by performing serial-to-parallel conversion on each pixel on the basis of a pixel stream, and the data bus is 1 byte.
Specifically, the chaotic encryption module only encrypts R bytes, G bytes and B bytes of the video, and simultaneously reserves the extended bytes to form a frame of encrypted video with the HDMI format. For this reason, the extraction operation of R byte, G byte and B byte must be performed before transmission. The ARM processor only sends R bytes, G bytes and B bytes in the encrypted video, and in order to improve efficiency, the extraction and sending operations are designed to be executed in parallel by the ARM dual-core processor through two independent threads. The CPU1 performs an extraction operation of RGB bytes, and the CPU0 performs a transmission operation of RGB bytes. And data sharing is performed between the dual-core processors by adopting on-Chip low-delay OCM (on Chip memory). The receiving end also realizes the functions of receiving and interpolation in an ARM dual-core parallel mode. The CPU0 on the transmitting side performs reception of the encrypted video, the CPU1 performs interpolation of the extension bytes, and the interpolation operation restores the encrypted video data to the HDMI format. The chaotic decryption module only performs decryption processing on R bytes, G bytes and B bytes in the video, and finally obtains a frame of decrypted video in the HDMI format. Through the cooperative implementation of FPGA and ARM software and hardware, the transmission capacity of one fourth is reduced, the encryption time consumption is reduced, and the real-time performance of the system is effectively improved. The encryption scheme is different from the full encryption scheme, the encryption scheme has small encryption time consumption, and the data transmission quantity in the system is reduced.
A sending end and a receiving end of a hardware environment of the system are connected with a route through gigabit Ethernet interfaces RJ45 to form a local area network, IP addresses are respectively configured to be 192.168.1.100 and 192.168.1.101, a platform adopts HDMI interfaces for display, parallel interfaces are adopted for completing video acquisition, and a USB is adopted for completing program downloading.
In the software environment of the system, a vivado 2014.4.1 development tool is installed under a Win7 operating system and used for FPGA design, and an SDK development tool with the same version is installed and used for ARM software development. The method comprises the steps of generating a bitstream file through FPGA design, generating an elf file through software programming, downloading the bitstream file firstly, and then downloading the elf file to finish the starting of the system.
Each buffer in the system can store 3 frames of video at the same time, and the frame buffer capacity is 1.2288MB under the condition that the video definition is 640 × 480. Each VDMA module in the FPGA implements access and transfer of buffer video by the VDMA module by configuring its row register MM2S _ HSIZE, column register MM2S _ VSIZE, and pointer register S2MM _ START _ ADDRESS for the read and write channels. The video access and transmission process involves frame synchronization and read-write synchronization control. Frame synchronization means that the VDMA module can correctly judge the boundary of a video frame; the read-write synchronization refers to a timing relationship that a read-write channel of the VDMA module should maintain when operating the same buffer, and requires that the operation of the read channel should lag behind that of the write channel by at least one frame buffer to prevent read-write collision of the frame buffers. The VDMA frame synchronization has two modes, tuser and fsync, the synchronization in tuser mode is triggered and controlled by an AXIS protocol signal tuser, and the synchronization in fsync mode is triggered and controlled by an external pulse signal. The read channels of 1-4 of the VDMA module adopt tuser mode, and the write channels adopt fsync mode. The VDMA read-write synchronization has two modes of a dynamic master mode and a dynamic slave mode, when the read-write channel operates the same buffer, the write channel is configured to be the dynamic master mode, and the read channel is configured to be the dynamic slave mode. The read and write channels operating the same buffer have to be configured in a read and write synchronous mode, in particular between the first VDMA write channel and the second VDMA read channel, and between the third VDMA write channel and the fourth VDMA read channel further pointer signals need to be connected.
The ARM dual-core processor executes two independent threads in parallel and carries out data sharing through an on-chip low-latency OCM memory. Under the trigger of the fsync signal, the original video in the first buffer area enters the chaotic encryption module through the second VDMA to form an encrypted video, and the encrypted video is stored in the second buffer area. CPU1 extracts the encrypted video and stores it in OCM as a packet of 1446 encrypted bytes. The CPU0 loops through reading and transmitting packets at the OCM.
The input end and the output end of the chaotic encryption module and the chaotic decryption module are communicated by adopting an AXIS interface protocol. The input end protocol signal comprises four input signals of tvalid, tdata, tuser and tlast and a tready output signal; the output end has four input signals of tvalid, tdata, tuser and tlast and a tready input signal. When the tvalid signal at the output terminal is equal to the linear signal at the input terminal, tdata, tuser, tlast signals are transmitted between modules, and otherwise, the transmission is suspended. Tdata is used as a video signal and has a bus width of 4 bytes, tuser and tlast are pulse signals and respectively identify frame synchronization and line synchronization, when tuser is 1, the first pixel of a current tdata data bus transmission video frame is represented, and similarly, when tlast is 1, the last pixel of a video line is represented.
And the chaotic encryption module and the chaotic decryption module are both provided with parallel multi-channel and assembly line structures. The parallel channels include a synchronization signal tuser & tlast channel, a serial data signal datax channel, a data identification signal flagx channel, and a counter carry signal coutx channel, where x represents the number of stages of the pipeline. the pipeline stages of tuser & tlast and datax channels are 6, and the pipeline stages of flagx and coutx channels are 3. The pipeline signal transitions to the next stage triggered by the rising edge of the system clock. | A The full signal is a pipelined global enable signal! When full is 1, the pipeline is enabled to work normally. flag is a validity flag signal of the video data datax, and when flag is 1, encryption and decryption processing of datax is enabled.
The chaotic encryption module and the chaotic decryption module both have serial-parallel conversion structures. The function of converting parallel to serial is realized through a selector and a counter in the 1 st-stage running water; the serial-to-parallel function is realized through a shift register in the 3 rd to 6 th pipelines. The 1-out-of-4 selector is a 4-byte input 1-byte output, and the select signal Q _ sel is controlled by a 2-bit count value. The carry signal cout0 is output with a delay to meet the timing requirements between the parallel channels.
The encryption or decryption operation of the video data is implemented using the coutx carry signal. The coutx carry signal is used as an enable signal of the encryption or decryption equation submodule, has a cycle period of 4 clocks, and keeps constant output with 3 clocks being high level and 1 clock being low level. The R byte, the G byte, the B byte, and the extension byte are kept chronologically corresponding to coutx ═ 1 and coutx ═ 0, respectively, so that the encryption or decryption equation submodule encrypts or decrypts only the R byte, the G byte, and the B byte, and keeps the extension byte directly output.
ARM dual cores of a sending end and a receiving end run in parallel and independently, and OCM is used as a data sharing area. Three buffers with the size of 1446 bytes are allocated in each OCM, and three identification variables with the size of 1 bit are set. When the identification variable is 1, the buffer area is in a readable state; when the flag variable is 0, it indicates that the buffer is in a writable state. The identification variables are inverted after the OCM operations are completed by CPU1 and CPU 0. And the software processing speed is improved by dual-core parallel processing.
The AXIS interface comprises three parts, namely a FIFO memory, a protocol interface and a pipeline interface. Wherein the FIFO memory deviceMemory cell having 34 bits and 2n-1The storage space of (2). The memory cell is synthesized from the protocol signals tdata, tuser, tlast, and the like. Increasing n is beneficial to increasing the speed but not beneficial to saving resources, and when n is selected to be 11, 1024 storage units are obtained.
The protocol interface realizes AXIS protocol function and data communication by reading addresses rd _ ptr [ n:0 ] of FIFO]And write address wr _ ptr [ n:0 ]]And implementing logic operation to obtain corresponding handshake signals tvalid and tready. Wherein the effective space of the read/write address is 2n-1The nth bit is used only for logic operations and not as an address signal. When rd _ ptr [ n:0 ]]Is equal to wr _ ptr [ n:0 ]]When the FIFO memory is in an empty state and the tread is equal to 1, the FIFO memory is ready to receive; when tvalid is equal to 0, no data output is indicated; when rd _ ptr [ n:0 ] is satisfied]Not equal to wr _ ptr [ n:0 ]]And rd _ ptr [ n-1:0 ]]Equal to wr _ ptr [ n-1:0]When the FIFO memory is in a full state; when tready is equal to 0, it means that reception is stopped: when tvalid is equal to 1, data output is indicated; when rd _ ptr [ n-1:0 ] is satisfied]Not equal to wr _ ptr [ n-1:0 ]]The FIFO memory is in a non-empty and non-full state. The full flag signal full of the memory is obtained through the inverse operation! The full signal serves as a global enable signal for the pipeline.
The pipeline interface enables data communication between the memory and the pipeline. The dataout signal output by the memory in fig. 6 is split and then enters the datax channel and tuser & tlast channel, and the validity flag signal flag0 enters the flagx channel. When flag1 is equal to 1, the flag signal enables the encryption equation and the decryption equation to process the original video data; when flag1 is equal to 0, no processing is performed. The datain signal input by the memory is formed by combining the signals of a datax channel and a tuser & tlast channel. The datain signal is stored when the validity flag signal flag3 is equal to 1, the carry signal cout3 is equal to 1, and the memory full flag signal full is equal to 0, are satisfied.
In the following, a video encryption transmission apparatus according to an embodiment of the present invention is introduced, and a video encryption transmission apparatus described below and a video encryption transmission method described above may be referred to each other.
Referring to fig. 4, an embodiment of the present invention provides a video encryption transmission apparatus, including:
a detection module 401, configured to detect an identification bit corresponding to a byte in each pixel of a video in an HDMI format;
the encryption module 402 is configured to perform chaotic encryption on the bytes corresponding to the enabled encryption identification bits when it is detected that the identification bits corresponding to the bytes are enabled for encryption;
an execution module 403, configured to transmit video data including a preset number of encrypted bytes to a receiving end, so that the receiving end inserts extension data for recovering a video format into the video data, and performs chaotic decryption on the video data into which the extension data is inserted;
wherein each pixel of the video comprises: the device comprises R bytes, G bytes, B bytes and bytes for marking extended data, wherein identification bits corresponding to the R bytes, the G bytes and the B bytes are encryption or decryption enabling, and identification bits corresponding to the bytes for marking the extended data are encryption or decryption forbidding.
Wherein the execution module is specifically configured to:
and when the receiving end detects that the identification bit corresponding to the byte in the video data inserted with the extended data is the enable decryption, performing chaotic decryption on the byte corresponding to the enable decryption identification bit.
Wherein the execution module is specifically configured to:
video data containing 1446 encrypted bytes is transmitted to the receiving end.
In the following, a video encryption transmission system according to an embodiment of the present invention is introduced, and a video encryption transmission system described below and a video encryption transmission method and apparatus described above may be referred to each other.
Referring to fig. 5, an embodiment of the present invention provides a video encryption transmission system, including:
a transmitting end 501, configured to detect an identification bit corresponding to a byte in each pixel of a video in an HDMI format; when the identification bit corresponding to the byte is detected to be the enabling encryption, carrying out chaotic encryption on the byte corresponding to the enabling encryption identification bit; transmitting video data containing a preset number of encrypted bytes to a receiving end;
a receiving end 502, configured to insert extended data for recovering a video format into the video data, and perform chaotic decryption on the video data into which the extended data is inserted;
wherein each pixel of the video comprises: the device comprises R bytes, G bytes, B bytes and bytes for marking extended data, wherein identification bits corresponding to the R bytes, the G bytes and the B bytes are encryption or decryption enabling, and identification bits corresponding to the bytes for marking the extended data are encryption or decryption forbidding.
In the following, a video encryption transmission device according to an embodiment of the present invention is introduced, and a video encryption transmission device described below and a video encryption transmission method, apparatus, and system described above may be referred to each other.
Referring to fig. 6, an embodiment of the present invention provides a video encryption transmission apparatus, including:
a memory 601 for storing a computer program;
a processor 602, configured to implement the steps of the video encryption transmission method according to any of the embodiments described above when executing the computer program.
In the following, a computer-readable storage medium according to an embodiment of the present invention is introduced, and a computer-readable storage medium described below and a video encryption transmission method, apparatus, system, and device described above may be referred to each other.
A computer-readable storage medium having stored thereon a computer program which, when executed by a processor, carries out the steps of a video encryption transmission method as claimed in any of the embodiments above.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A method for encrypted transmission of video, comprising:
detecting an identification bit corresponding to a byte in each pixel of the video in the HDMI format;
when the identification bit corresponding to the byte is detected to be the enabling encryption, carrying out chaotic encryption on the byte corresponding to the enabling encryption identification bit;
transmitting video data containing a preset number of encrypted bytes to a receiving end so that the receiving end inserts extended data for recovering a video format into the video data, and performing chaotic decryption on the video data after the extended data is inserted;
wherein each pixel of the video comprises: the device comprises R bytes, G bytes, B bytes and bytes for marking extended data, wherein identification bits corresponding to the R bytes, the G bytes and the B bytes are encryption or decryption enabling, and identification bits corresponding to the bytes for marking the extended data are encryption or decryption forbidding.
2. The video encryption transmission method according to claim 1, wherein the performing chaotic decryption on the video data inserted with the extension data comprises:
and when the receiving end detects that the identification bit corresponding to the byte in the video data inserted with the extended data is the enable decryption, performing chaotic decryption on the byte corresponding to the enable decryption identification bit.
3. The method for encrypted video transmission according to claim 1, wherein the transmitting video data containing a predetermined number of encrypted bytes to a receiving end comprises:
video data containing 1446 encrypted bytes is transmitted to the receiving end.
4. The method for video encryption transmission according to claim 3, wherein before transmitting the video data containing 1446 encrypted bytes to the receiving end, the method further comprises:
and storing the video data containing 1446 encrypted bytes into a preset buffer by using a VDMA module.
5. A video encryption transmission apparatus, comprising:
the detection module is used for detecting an identification bit corresponding to a byte in each pixel of the video in the HDMI format;
the encryption module is used for carrying out chaotic encryption on the bytes corresponding to the enabled encryption identification bits when the identification bits corresponding to the bytes are detected to be enabled for encryption;
the device comprises an execution module, a receiving end and a processing module, wherein the execution module is used for transmitting video data containing a preset number of encrypted bytes to the receiving end so that the receiving end inserts extended data for recovering a video format into the video data and chaotically decrypts the video data inserted with the extended data;
wherein each pixel of the video comprises: the device comprises R bytes, G bytes, B bytes and bytes for marking extended data, wherein identification bits corresponding to the R bytes, the G bytes and the B bytes are encryption or decryption enabling, and identification bits corresponding to the bytes for marking the extended data are encryption or decryption forbidding.
6. The video encryption transmission apparatus according to claim 5, wherein the execution module is specifically configured to:
and when the receiving end detects that the identification bit corresponding to the byte in the video data inserted with the extended data is the enable decryption, performing chaotic decryption on the byte corresponding to the enable decryption identification bit.
7. The video encryption transmission apparatus according to claim 5, wherein the execution module is specifically configured to:
video data containing 1446 encrypted bytes is transmitted to the receiving end.
8. A video encryption transmission system, comprising:
the device comprises a sending end, a receiving end and a processing end, wherein the sending end is used for detecting an identification bit corresponding to a byte in each pixel of the video in the HDMI format; when the identification bit corresponding to the byte is detected to be the enabling encryption, carrying out chaotic encryption on the byte corresponding to the enabling encryption identification bit; transmitting video data containing a preset number of encrypted bytes to a receiving end;
the receiving end is used for inserting the extended data for recovering the video format into the video data and performing chaotic decryption on the video data inserted with the extended data;
wherein each pixel of the video comprises: the device comprises R bytes, G bytes, B bytes and bytes for marking extended data, wherein identification bits corresponding to the R bytes, the G bytes and the B bytes are encryption or decryption enabling, and identification bits corresponding to the bytes for marking the extended data are encryption or decryption forbidding.
9. A video encryption transmission apparatus, comprising:
a memory for storing a computer program;
processor for implementing the steps of the video encryption transmission method according to any one of claims 1 to 4 when executing said computer program.
10. A computer-readable storage medium, characterized in that a computer program is stored on the computer-readable storage medium, which computer program, when being executed by a processor, carries out the steps of the video encryption transmission method according to any one of claims 1 to 4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711377177.3A CN108063663B (en) | 2017-12-19 | 2017-12-19 | Video encryption transmission method, device and system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711377177.3A CN108063663B (en) | 2017-12-19 | 2017-12-19 | Video encryption transmission method, device and system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108063663A CN108063663A (en) | 2018-05-22 |
| CN108063663B true CN108063663B (en) | 2021-01-26 |
Family
ID=62139619
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711377177.3A Active CN108063663B (en) | 2017-12-19 | 2017-12-19 | Video encryption transmission method, device and system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108063663B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109040790B (en) * | 2018-06-28 | 2020-12-22 | 苏州科达科技股份有限公司 | Data encryption and decryption method and device and electronic equipment |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6931574B1 (en) * | 2001-10-24 | 2005-08-16 | Finisar Corporation | Systems and methods for interpreting communications packets |
| CN105830134A (en) * | 2013-12-16 | 2016-08-03 | 来特荣国际有限公司 | Method and device for compressing and expanding image intended for encrypted communication, program, and storage medium |
| CN107395338A (en) * | 2017-08-30 | 2017-11-24 | 广东工业大学 | Video chaotic secret communication device and method based on non-linear nominal matrix |
| CN107483173A (en) * | 2017-08-30 | 2017-12-15 | 广东工业大学 | A kind of video chaotic secret communication device and method |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101366912B1 (en) * | 2006-05-16 | 2014-02-24 | 소니 주식회사 | Communication system, transmission device, reception device, communication method, and program |
| CN102982499B (en) * | 2012-09-28 | 2015-10-07 | 河南大学 | Based on color image encryption and the decryption method of multi-fractional order chaos system |
| WO2015115798A1 (en) * | 2014-01-29 | 2015-08-06 | Samsung Electronics Co., Ltd. | User terminal device and secured communication method thereof |
| CN105550972B (en) * | 2016-02-03 | 2018-02-13 | 广东工业大学 | A kind of image encryption method of higher-dimension numeric field chaos system |
-
2017
- 2017-12-19 CN CN201711377177.3A patent/CN108063663B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6931574B1 (en) * | 2001-10-24 | 2005-08-16 | Finisar Corporation | Systems and methods for interpreting communications packets |
| CN105830134A (en) * | 2013-12-16 | 2016-08-03 | 来特荣国际有限公司 | Method and device for compressing and expanding image intended for encrypted communication, program, and storage medium |
| CN107395338A (en) * | 2017-08-30 | 2017-11-24 | 广东工业大学 | Video chaotic secret communication device and method based on non-linear nominal matrix |
| CN107483173A (en) * | 2017-08-30 | 2017-12-15 | 广东工业大学 | A kind of video chaotic secret communication device and method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108063663A (en) | 2018-05-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP6883377B2 (en) | Display driver, display device and operation method of display driver | |
| CN101114903B (en) | High grade encrypting criterion encrypter in Gbpassive optical network system and implementing method thereof | |
| CN102541780B (en) | Multi-data stream channel DMA (Direct Memory Access) system | |
| CN112329038B (en) | Data encryption control system and chip based on USB interface | |
| EP2645235B1 (en) | Random value production methods and systems | |
| US9678891B2 (en) | Efficient search key controller with standard bus interface, external memory interface, and interlaken lookaside interface | |
| CN105049834A (en) | Real-time auto-stereoscopic playing system based on FPGA (Field Programmable Gate Array) | |
| CN102346661A (en) | Method and system for state maintenance of request queue of hardware accelerator | |
| CN102656851B (en) | Data diffluence encapsulation is entered to method, the Apparatus and system in multiple links | |
| CN103413094A (en) | Telemetering encryption system applicable to spacecraft CPU (central processing unit) | |
| US20190362107A1 (en) | Advanced peripheral bus based inter-integrated circuit communication device | |
| CN103092806A (en) | Data transmission method and data transmission system based on serial peripheral interface (SPI) data transmission timing sequences | |
| CN109788347B (en) | Video chaotic secret communication device and method | |
| CN105630446A (en) | FPGA technology based video processing system | |
| CN108063663B (en) | Video encryption transmission method, device and system | |
| CN113190291A (en) | Configurable protocol conversion system and method based on network-on-chip data acquisition | |
| CN107483173A (en) | A kind of video chaotic secret communication device and method | |
| US9594706B2 (en) | Island-based network flow processor with efficient search key processing | |
| CN101529381B (en) | System and method for object oriented hardware | |
| US8237721B2 (en) | Information handling system and method for using main link data channels | |
| CN107087213A (en) | A kind of system and method for video chaotic secret communication | |
| CN107395338A (en) | Video chaotic secret communication device and method based on non-linear nominal matrix | |
| CN105227288B (en) | GMII data transmission method for uplink and device | |
| CN102902648A (en) | Direct memory access (DMA)-based general purpose input output (GPIO) module capable of refreshing light-emitting diode (LED) display screen | |
| CN107786866B (en) | Binocular vision image synthesis system and method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |