CN107483173A - A kind of video chaotic secret communication device and method - Google Patents
A kind of video chaotic secret communication device and method Download PDFInfo
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- CN107483173A CN107483173A CN201710766027.5A CN201710766027A CN107483173A CN 107483173 A CN107483173 A CN 107483173A CN 201710766027 A CN201710766027 A CN 201710766027A CN 107483173 A CN107483173 A CN 107483173A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/001—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols using chaotic signals
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/20—Servers specifically adapted for the distribution of content, e.g. VOD servers; Operations thereof
- H04N21/23—Processing of content or additional data; Elementary server operations; Server middleware
- H04N21/234—Processing of video elementary streams, e.g. splicing of video streams or manipulating encoded video stream scene graphs
- H04N21/2347—Processing of video elementary streams, e.g. splicing of video streams or manipulating encoded video stream scene graphs involving video stream encryption
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/44—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs
- H04N21/4405—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs involving video stream decryption
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Abstract
This application discloses a kind of video chaotic secret communication device and method, the equipment includes video sending end and video receiver；Video sending end includes the first SOC, the first core buffer and data sending device, and video receiver includes the second SOC, the second core buffer and data sink；First SOC includes the first FPGA and the first ARM, and the second SOC includes the 2nd FPGA and the 2nd ARM；First FPGA includes the first VDMA and using chaos encryption module of the AXIS agreements as interface protocol, and the 2nd FPGA includes the 2nd VDMA and using chaos deciphering module of the AXIS agreements as interface protocol.The application has been disposed in the FPGA inside SOC using chaos enciphering/deciphering module and corresponding VDMA of the AXIS agreements as interface protocol, the purpose for carrying out real-time chaotic secret communication to video data on a hardware platform is realized, is advantageous to accelerate the daily use and business promotion of video Chaotic secret communication technology.
Description
Technical field
The present invention relates to technical field of video communication, more particularly to a kind of video chaotic secret communication device and method.
Background technology
With the fast development of multimedia era, people to the quality of video content and the requirement more and more higher of quantity, with
This simultaneously, requirement of the people to the security of video communication also more and more higher.In order to adapt to people to Video security
Actual demand, in recent years video private communication technology become very popular research topic.
However, current people are when research is required to the higher video-encryption communication technology to security and real-time,
Such as generally all it is to deploy to study using numerical simulation, so far also not in hardware when studying Chaotic secret communication technology
The real-time chaotic secret communication to video data is realized on platform, should so as to be unfavorable for the daily of video Chaotic secret communication technology
With and business promotion.
In summary as can be seen that how to realize on a hardware platform to the real-time chaotic secret communication of video data is to work as
It is preceding to also have the problem of to be solved.
The content of the invention
In view of this, can be hard it is an object of the invention to provide a kind of video chaotic secret communication device and method
The real-time chaotic secret communication to video data is realized on part platform.Its concrete scheme is as follows：
A kind of video chaotic secret communication equipment, including video sending end and video receiver；The video sending end bag
Include the first SOC, the first core buffer and data sending device, the video receiver includes the second SOC, the
Two core buffers and data sink；First SOC includes the first FPGA and the first ARM, the 2nd SOC
Chip includes the 2nd FPGA and the 2nd ARM；First FPGA includes the first VDMA and using AXIS agreements as interface association
The chaos encryption module of view, the 2nd FPGA include the 2nd VDMA and using Chaotic Solution of the AXIS agreements as interface protocol
Close module；Wherein,
The chaos encryption module, for obtaining original video data by the first VDMA, based on default chaos
AES, the original video data is encrypted, and will be obtained by the first VDMA after encryption
Encrypted data transmission to first core buffer is preserved；
First ARM, for reading out the encryption data from first core buffer, and pass through the number
The encryption data is sent to the data sink according to dispensing device；
2nd ARM, for obtaining the encryption data of data sink transmission, and by the encryption number
Preserved according to transmitting to second core buffer；
The chaos deciphering module, the institute of second core buffer is stored in for being obtained by the 2nd VDMA
Encryption data is stated, based on default chaos decipherment algorithm, processing is decrypted to the encryption data, obtains decrypting number accordingly
According to.
Optionally, the signal involved by the AXIS protocol interfaces in the chaos encryption module and the chaos deciphering module
Include tvalid, tdata, tuser, tlast and tready signal；
Wherein, handshake of the tvalid and tready between corresponding communicating pair, also, in the case of high level
Start tdata, tuser and tlast signal to be communicated, then suspend data communication in the case of low level.
Optionally, the signalling channel in the chaos encryption module and the chaos deciphering module is parallel channel；
Wherein, the parallel channel in the chaos encryption module and the chaos deciphering module handle respectively tdata,
Tuser, tlast and control signal.
Optionally, each signalling channel in the chaos encryption module and the chaos deciphering module is provided with multilevel flow
Line structure, separated by d type flip flop per level production line and work is triggered by system clock, also, in the flowing water course of work, letter
Number interchannel keeps strict sequential relationship.
Optionally, the converter for being used to solve inside and outside data-bus width mismatch problem in the chaos encryption module
For parallel/serial converter；
The converter for being used to solve inside and outside data-bus width mismatch problem in the chaos deciphering module is serial/parallel
Converter.
Optionally, the parallel/serial converter is the converter created based on selector and counter；
The serial/parallel converter is the converter created based on shift register.
Optionally, the chaos encryption module, the chaos encryption is specifically represented using the form for there are 64 Q32 of symbol
Key parameter and corresponding state variable in algorithm, and corresponding fixed point fortune is carried out by hardware multiplier and adder
Calculate；
The chaos deciphering module, specifically represented using the form for there are 64 Q32 of symbol in the chaos decipherment algorithm
Key parameter and corresponding state variable, and corresponding fixed-point calculation is carried out by hardware multiplier and adder.
Optionally, the chaos encryption module is during being encrypted, specifically using ROM lookup table modes come really
Sine term in the fixed chaos encryption algorithm；
The chaos deciphering module during processing is decrypted, it is specific determined using ROM lookup table modes described in
Sine term in chaos decipherment algorithm.
Optionally, the video sending end also includes the 3rd core buffer being connected with the first VDMA；Described
One FPGA also includes video frequency collection card and the 3rd VDMA；The video receiver also includes the 4th be connected with the 2nd VDMA
Core buffer；2nd FPGA also includes the 4th VDMA；Wherein,
3rd VDMA, the original video data for the video frequency collection card to be collected are transmitted to described
Three core buffers are preserved, so that the first VDMA obtains the original video number from the 3rd core buffer
According to；
4th core buffer, described in being obtained by the 2nd VDMA acquisitions chaos deciphering module
Ciphertext data, and the ciphertext data is preserved；
4th VDMA, for the ciphertext data in the 4th core buffer to be transmitted to display
Shown.
The present invention further correspondingly discloses a kind of video Development of Chaotic Secure Communication Method, is set applied to video chaotic secret communication
It is standby, wherein, the video chaotic secret communication equipment includes video sending end and video receiver；The video sending end includes
First SOC, the first core buffer and data sending device, the video receiver include the second SOC, second
Core buffer and data sink；First SOC includes the first FPGA and the first ARM, the 2nd SOC cores
Piece includes the 2nd FPGA and the 2nd ARM；First FPGA includes the first VDMA and using AXIS agreements as interface protocol
Chaos encryption module, the 2nd FPGA include the 2nd VDMA and using AXIS agreements as interface protocol chaos decryption
Module；Wherein, methods described includes：
The chaos encryption module obtains original video data by the first VDMA, and is based on default chaos encryption
Algorithm, the original video data is encrypted, then added by the first VDMA by what is obtained after encryption
Ciphertext data is transmitted to first core buffer and preserved；
First ARM reads out the encryption data from first core buffer, and is sent out by the data
Device is sent to send the encryption data to the data sink；
2nd ARM obtains the encryption data of the data sink transmission, and the encryption data is passed
Second core buffer is transported to be preserved；
The chaos deciphering module obtains to be stored in described in second core buffer by the 2nd VDMA to be added
Ciphertext data, and default chaos decipherment algorithm is based on, processing is decrypted to the encryption data, obtains decrypting number accordingly
According to.
In the present invention, video chaotic secret communication equipment, including video sending end and video receiver；Video sending end bag
The first SOC, the first core buffer and data sending device are included, video receiver is including in the second SOC, second
Deposit buffering area and data sink；First SOC includes the first FPGA and the first ARM, and the second SOC includes second
FPGA and the 2nd ARM；First FPGA includes the first VDMA and uses chaos encryption module of the AXIS agreements as interface protocol,
2nd FPGA includes the 2nd VDMA and using chaos deciphering module of the AXIS agreements as interface protocol；Wherein, chaos encryption
Module, for obtaining original video data by the first VDMA, based on default chaos encryption algorithm, original video data is entered
Row encryption, and protected the encrypted data transmission obtained after encryption to the first core buffer by the first VDMA
Deposit；First ARM, for reading out encryption data from the first core buffer, and by data sending device by encryption data
Send to data sink；2nd ARM, for obtaining the encryption data of data sink transmission, and encryption data is passed
The second core buffer is transported to be preserved；Chaos deciphering module, delay for being stored in the second internal memory by the 2nd VDMA acquisitions
The encryption data in area is rushed, based on default chaos decipherment algorithm, encryption data is decrypted processing, obtains decrypting number accordingly
According to.
It can be seen that the present invention has been disposed using AXIS agreements in the FPGA inside SOC as interface protocol
Chaos enciphering/deciphering module and corresponding VDMA, so, can be with by VDMA in addition, be additionally provided with corresponding ARM in SOC
The data transmission between FPGA and core buffer is realized, phase can then be completed by the chaos enciphering/deciphering module in FPGA
The chaos enciphering/deciphering processing answered, and corresponding memory read-write operation can be then carried out by ARM, received with completing follow-up data
Hair process, thus, the present invention realize the purpose for carrying out real-time chaotic secret communication to video data on a hardware platform, favorably
In the daily use and business promotion of accelerating video Chaotic secret communication technology, there is huge commercial application value.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
There is the required accompanying drawing used in technology description to be briefly described, it should be apparent that, drawings in the following description are only this
The embodiment of invention, for those of ordinary skill in the art, on the premise of not paying creative work, can also basis
The accompanying drawing of offer obtains other accompanying drawings.
Fig. 1 is a kind of video chaotic secret communication device structure schematic diagram disclosed in the embodiment of the present invention；
Fig. 2 is a kind of specific video chaotic secret communication device hardware structural representation disclosed in the embodiment of the present invention；
Fig. 3 is chaos encryption module diagram disclosed in the embodiment of the present invention；
Fig. 4 is that chaos disclosed in the embodiment of the present invention decrypts module diagram；
Fig. 5 is chaos encryption operator module diagram disclosed in the embodiment of the present invention；
Fig. 6 is that chaos disclosed in the embodiment of the present invention decrypts operator module diagram；
Fig. 7 is input AXIS interface protocol schematic diagrames disclosed in the embodiment of the present invention；
Fig. 8 is output terminals A XIS interface protocol schematic diagrames disclosed in the embodiment of the present invention；
Fig. 9 is a kind of video Development of Chaotic Secure Communication Method flow chart disclosed in the embodiment of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation describes, it is clear that described embodiment is only part of the embodiment of the present invention, rather than whole embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art are obtained every other under the premise of creative work is not made
Embodiment, belong to the scope of protection of the invention.
Shown in Figure 1 the embodiment of the invention discloses a kind of video chaotic secret communication equipment, the equipment includes video
Transmitting terminal and video receiver；Video sending end includes the first SOC 1, the first core buffer 2 and data sending device
3, video receiver includes the second SOC 4, the second core buffer 5 and data sink 6；First SOC 1 is wrapped
The first FPGA11 and the first ARM12 is included, the second SOC 4 includes the 2nd FPGA41 and the 2nd ARM42；First FPGA11 includes
The chaos encryption module 112 of first VDMA111 and use AXIS agreements as interface protocol, the 2nd FPGA41 include second
The chaos deciphering module 412 of VDMA411 and use AXIS agreements as interface protocol；Wherein,
Chaos encryption module 112, for obtaining original video data by the first VDMA111, added based on default chaos
Close algorithm, original video data is encrypted, and the encryption data that will be obtained by the first VDMA111 after encryption
Transmit to the first core buffer 2 and preserved；
First ARM12, for reading out encryption data from the first core buffer 2, and will by data sending device 3
Encryption data is sent to data sink 6；
2nd ARM42, for obtaining the encryption data of the transmission of data sink 6, and by encrypted data transmission to second
Core buffer 5 is preserved；
Chaos deciphering module 412, the encryption number of the second core buffer 5 is stored in for being obtained by the 2nd VDMA411
According to based on default chaos decipherment algorithm, processing is decrypted to encryption data, obtains corresponding ciphertext data.
In the present embodiment, involved by the AXIS protocol interfaces in above-mentioned chaos encryption module 112 and chaos deciphering module 412
Signal include tvalid, tdata, tuser, tlast and tready signal；Wherein, tvalid and tready is corresponding
Communicating pair between handshake, also, in the case of high level start tdata, tuser and tlast signal led to
Letter, then suspend data communication in the case of low level.
Further, in the present embodiment, the signalling channel in above-mentioned chaos encryption module 112 and chaos deciphering module 412
Preferentially it is set to parallel channel；Wherein, the parallel channel in chaos encryption module 112 and chaos deciphering module 412 is handled respectively
Tdata, tuser, tlast and control signal.
In addition, in the present embodiment, each signalling channel in above-mentioned chaos encryption module 112 and chaos deciphering module 412
Multi-stage pipeline arrangement is provided with, is separated by d type flip flop per level production line and work is triggered by system clock, also, in flowing water
Strict sequential relationship is kept in the course of work, between signalling channel.
In the present embodiment, in above-mentioned chaos encryption module 112 be used for solve inside and outside data-bus width mismatch problem
Converter be parallel/serial converter；
And the converter for being used to solve inside and outside data-bus width mismatch problem in above-mentioned chaos deciphering module 412 is
Serial/parallel converter.
Specifically, above-mentioned parallel/serial converter is specially the converter created based on selector and counter；Above-mentioned string/
And converter is specially the converter created based on shift register.
In the present embodiment, the parallel data of 4 byte wides can be changed into 1 byte wide by above-mentioned parallel/serial conversion implement body
Serial data, complete encryption and decryption after, pass through serial/parallel converter recover 4 byte wides output.
In the present embodiment, above-mentioned chaos encryption module 112, it can specifically be represented using the form for having 64 Q32 of symbol
Key parameter and corresponding state variable in chaos encryption algorithm, and carried out accordingly by hardware multiplier and adder
Fixed-point calculation；
Similarly, above-mentioned chaos deciphering module 412, specifically chaos can also be represented using the form for there are 64 Q32 of symbol
Key parameter and corresponding state variable in decipherment algorithm, and by hardware multiplier and adder accordingly determine
Point processing.
Further, above-mentioned chaos encryption module 112 can specifically be looked into during being encrypted using ROM
Table mode determines the sine term in chaos encryption algorithm；
Similarly, above-mentioned chaos deciphering module 412 can also specifically be tabled look-up during processing is decrypted using ROM
Mode determines the sine term in chaos decipherment algorithm.
Delay in addition, the video sending end in the present embodiment can further include with the first VDMA the 3rd internal memories being connected
Rush area；First FPGA can further include video frequency collection card and the 3rd VDMA；Video receiver can further include
The 4th core buffer being connected with the 2nd VDMA；2nd FPGA also includes the 4th VDMA；Wherein,
3rd VDMA, the original video data for video frequency collection card to be collected are transmitted to the 3rd core buffer and carried out
Preserve, so that the first VDMA obtains original video data from the 3rd core buffer；
4th core buffer, for the ciphertext data obtained by the 2nd VDMA acquisition chaos deciphering modules, and to solution
Ciphertext data is preserved；
4th VDMA, shown for the ciphertext data in the 4th core buffer to be transmitted to display.
It can be seen that the embodiment of the present invention has been disposed using AXIS agreements in the FPGA inside SOC as interface
The chaos enciphering/deciphering module of agreement and corresponding VDMA, in addition, being additionally provided with corresponding ARM in SOC, so, pass through
VDMA can realize the data transmission between FPGA and core buffer, then may be used by the chaos enciphering/deciphering module in FPGA
To complete corresponding chaos enciphering/deciphering processing, and corresponding memory read-write operation can be then carried out by ARM, it is follow-up to complete
Data transmit-receive process, thus, the embodiment of the present invention realizes carries out real-time chaotic secret to video data on a hardware platform
The purpose of communication, be advantageous to accelerate the daily use and business promotion of video Chaotic secret communication technology, there is huge business
Application value.
It is shown in Figure 2, the embodiment of the invention discloses a kind of specific video chaotic secret communication equipment, in the equipment
Hardware environment in, specifically selected two sets of SOC embedded platforms respectively as video sending end and video receiver, both ends it
Between LAN formed by gigabit ethernet interface RJ45 and route connection, IP address be respectively configured as 192.168.1.100 and
192.168.1.101, platform is shown using HDMI, and video acquisition is completed using parallel port, and download program is completed using USB.
On the basis of above-mentioned hardware environment is built, also need further to establish the software environment of system, specifically in Win7 operating systems
Lower installation vivado2014.4.1 developing instruments are used for FPGA design, and the SDK developing instruments for installing identical version are used for ARM softwares
Exploitation.Bitstream files are generated by FPGA design, elf files are generated by software programming, first download bitstream texts
Part, then elf files are downloaded, complete the startup of system.
In the present embodiment, the SOC in video sending end and video receiver is using the programmable of Xilinx companies
SOC ZYNQ 0702, including ARM Cortex A9 processors and fpga logic door two spike-type cultivars, by ARM and
FPGA Hardware/Software Collaborative Design, can optimize the performance of system, and and can reduces the difficulty of research and development, it is flexible to embody SOC
And the characteristics of efficient, in addition, the AXIS agreements used in ability chaos enciphering/deciphering module of the present invention are the industry that ARM companies define
Level standard, the interface protocol can realize the seamless compatibility of communicating pair.
Shown in Fig. 2 hardware system configuration principle and SOC on framework, Installed System Memory allocation buffer 1~4, often
There are individual buffering area 3 frame buffers can store 3 frame videos simultaneously, and under conditions of video definition is 320 × 240, frame delays
It is 300KB to deposit capacity.VDMA 1~4 is designed in FPGA, by the row register MM2S_HSIZE, the row that configure its read/write channel
Register MM2S_VSIZE and pointer register S2MM_START_ADDRESS, realize access of the VDMA modules to buffering area video
And transmission.
The access of video and transmit process are related to frame synchronization and read and write synchronous control.Frame synchronization, which refers to VDMA, correctly to be sentenced
The border of other frame of video.Read-write synchronously refers to the sequential relationship that VDMA read/write channels should be kept when operating identical buffering area,
At least one frame buffer of write access should be lagged behind by asking the operation of read channel, to prevent the read/write conflict of frame buffer.VDMA frames are same
Walking has tuser and fsync both of which, and under tuser patterns is synchronously to carry out triggering control with AXIS protocol signals tuser,
Under fsync patterns is synchronously to carry out triggering control with outside pulse signal.VDMA 1~4 read channel uses tuser patterns,
Write access uses fsync patterns.VDMA read-writes synchronously have dynamic master and dynamic slave both of which, work as reading
In the case that write access operates identical buffering area, write access is configured to dynamic master patterns, and reading, which is led to, to be configured to
Dynamic slave patterns, in the case if when read/write channel belongs to different VDMA modules, it is also necessary to will further write
The frame buffer pointer output signal frame_ptr_out of passage is connected to the pointer input signal frame_ptr_in of read channel.
As shown in Fig. 2 the read/write channel for operating identical buffering area must be written and read the configuration of synchronous mode, particularly VDMA1 writes logical
Between road and VDMA2 read channels, further concatenation pointer signal is also needed between VDMA3 write access and VDMA4 read channels.
Fig. 3 and Fig. 4 respectively illustrates chaos encryption module and the structure of chaos deciphering module.The input of encryption/decryption module is defeated
Go out to be communicated using AXIS interface protocols.Input protocol signal has tetra- input letters of tvalid, tdata, tuser, tlast
Number and tready output signals；Output end has tetra- output signals of tvalid, tdata, tuser, tlast and tready input letters
Number.Start to transmit tdata, tuser and tlast signal between handshake tvalid=tready=1 situation lower modules, other
In the case of suspend transmission.Tdata is that the data/address bus of 4 byte wides is used for the transmission of vision signal, and tuser and tlast are arteries and veins
Rush signal and identify frame synchronization and row respectively synchronously, tuser=1 represents first of current tdata data/address bus transmission frame of video
Pixel, similarly, tlast=1 represent last pixel of transmission video line.
In the present embodiment, encryption/decryption module has parallel multi-channel and pipeline organization.Parallel channel includes synchronizing signal
Tuser＆tlast passages, serial data signal datax passages, Data Identification signal flagx passages and counter carry signal
Coutx passages, wherein x represent the series of streamline.The series x=6 of tuser＆tlast passages and datax passages, flagx lead to
The series x=3 in road and coutx passages.Waterline signal is flowed down to next stage saltus step in the triggering of system clock rising edge.In figure！
Full signals are streamline overall situation enable signal,！Full=1 enables streamline normal work.Flagx is video data datax
Validity id signal, flagx=1 enable datax encryption and decryption process.
In the present embodiment, encryption/decryption module has serioparallel exchange structure.Pass through selector and counter in the 1st grade of flowing water
Realize the function of turning serial parallel；Transformation from serial to parallel work(is realized by shift register into the 6th level production line in 3rd level
Energy.4 select 1 selector to input the output of 1 byte for 4 bytes, and selection signal Q_sel is controlled by 2 count values.Carry signal cout0
Exported by delay to meet the timing requirements between parallel channel.
In embodiments of the present invention, the mathematic(al) representation of chaos encryption equation corresponding with chaos encryption algorithm is specially：
X in formula, Y, Z are state variable, key parameter aij(i, j=1,2,3) size is：
State variable and key parameter are represented using the form for having 64 Q32 of symbol.Using FPGA multipliers and adder
Fixed-point calculation is realized, using ROM memory resource and lookup table mode, using radian as address, sine value corresponding to ROM outputs.Will
Radian and sine value establishment for two-dimensional table and form the file for extending entitled .core, and import in ROM memory and can be achieved to look into
Look for table function.
In (1) formula, O (k) is encrypted video sequence, and its mathematic(al) representation is：
Have for chaos decryption equation：
Wherein k=1,2,3 ..., mkWithFor raw video signal and decryption vision signal, skWithFor encryption equation and
Key sequence caused by decryption equation iteration.Under parameter matching conditionThen successful decryption, otherwise decryption failure.Fig. 5
Middle data1 and data2 are raw video signal and encrypted video signal, correspond to the m in (3) formula respectivelykWith O (k)；In Fig. 6
Data1 and data2 respectively correspond to (4) formula in O (k) and
In addition, in the present embodiment, the schematic diagram of input and output terminals A XIS interface protocols point in chaos enciphering/deciphering module
Not as shown in Figure 7 and Figure 8, including FIFO memory, protocol interface and flowing water line interface three parts.
Wherein, FIFO memory has the memory cell and 2 of 34n-1Memory space.Memory cell is by protocol signal
Tdata, tuser and tlast, which merge, to be formed.But it is unfavorable for saving resource because increase n is advantageous to lifting speed, so of the invention
Embodiment preferentially chooses n=11, is derived from 1024 memory cell.
In addition, in the present embodiment, protocol interface realizes AXIS protocol functions and data communication, by reading address to FIFO
rd_ptr[n:0] and write address wr_ptr [n:0] implement logical operation and obtain corresponding handshake tvalid and tready.
Wherein the read/write address useful space is 2n-1, n-th is only used for logical operation and not as address signal.As wr_ptr [n:0]=
rd_ptr[n:0] in the case of, FIFO memory is dummy status, tready=1 in Fig. 7, represents to prepare to receive, tvalid in Fig. 8
=0, represent no data output；When meeting wr_ptr [n] ≠ rd_ptr [n] and wr_ptr [n-1:0]=rd_ptr [n-1:0]
When, FIFO memory is full state, tready=0 in Fig. 7, represents to stop receiving：Tvalid=1 in Fig. 8, indicate that data are defeated
Go out；When meeting wr_ptr [n-1:0]≠rd_ptr[n-1:When 0], FIFO memory is the non-full state of non-NULL, in Fig. 7,8
Tready=1, tvalid=1.The full marking signal full of memory obtains by negating computing in Fig. 8！Full signals, as figure
The global enable signal of streamline in 3-4.
The data that flowing water line interface is realized between memory and streamline communicate.The dataout that memory exports in Fig. 7
Signal enters datax passages and tuser＆tlast passages after splitting, and its validity flag signal flag0 enters flagx passages.
As shown in Figure 3-4, when meeting flag1=1, marking signal enables encryption equation and decryption equation to data1 processing；When
Meet not process during flag1=0.The datain signals of Fig. 8 memories input are by the datax passages and tuser＆ in Fig. 3-4
The signal of tlast passages, which merges, to be formed.When meeting validity flag signal flag3=1, carry signal cout3=1 and memory
During full id signal full=0, datain signals are just stored.
Accordingly, the embodiment of the invention also discloses a kind of video Development of Chaotic Secure Communication Method, protected applied to video chaos
Close communication equipment, wherein, video chaotic secret communication equipment includes video sending end and video receiver；Video sending end includes
First SOC, the first core buffer and data sending device, video receiver include the second SOC, the second internal memory
Buffering area and data sink；First SOC includes the first FPGA and the first ARM, and the second SOC includes second
FPGA and the 2nd ARM；First FPGA includes the first VDMA and uses chaos encryption module of the AXIS agreements as interface protocol,
2nd FPGA includes the 2nd VDMA and using chaos deciphering module of the AXIS agreements as interface protocol；Wherein, referring to Fig. 9 institutes
Show, the above method includes：
Step S11：Chaos encryption module obtains original video data by the first VDMA, and is based on default chaos encryption
Algorithm, original video data is encrypted, then passed the encryption data obtained after encryption by the first VDMA
The first core buffer is transported to be preserved；
Step S12：First ARM reads out encryption data from the first core buffer, and will by data sending device
Encryption data is sent to data sink；
Step S13：2nd ARM obtains the encryption data of data sink transmission, and by encrypted data transmission to second
Core buffer is preserved；
Step S14：Chaos deciphering module obtains the encryption data for being stored in the second core buffer by the 2nd VDMA, and
Based on default chaos decipherment algorithm, processing is decrypted to encryption data, obtains corresponding ciphertext data.
The corresponding contents disclosed in previous embodiment are may be referred on above-mentioned each more detailed process of step, herein
No longer repeated.
It can be seen that the embodiment of the present invention has been disposed using AXIS agreements in the FPGA inside SOC as interface
The chaos enciphering/deciphering module of agreement and corresponding VDMA, in addition, being additionally provided with corresponding ARM in SOC, so, pass through
VDMA can realize the data transmission between FPGA and core buffer, then may be used by the chaos enciphering/deciphering module in FPGA
To complete corresponding chaos enciphering/deciphering processing, and corresponding memory read-write operation can be then carried out by ARM, it is follow-up to complete
Data transmit-receive process, thus, the embodiment of the present invention realizes carries out real-time chaotic secret to video data on a hardware platform
The purpose of communication, be advantageous to accelerate the daily use and business promotion of video Chaotic secret communication technology, there is huge business
Application value.
Finally, it is to be noted that, herein, such as first and second or the like relational terms be used merely to by
One entity or operation make a distinction with another entity or operation, and not necessarily require or imply these entities or operation
Between any this actual relation or order be present.Moreover, term " comprising ", "comprising" or its any other variant meaning
Covering including for nonexcludability, so that process, method, article or equipment including a series of elements not only include that
A little key elements, but also the other element including being not expressly set out, or also include for this process, method, article or
The intrinsic key element of equipment.In the absence of more restrictions, the key element limited by sentence "including a ...", is not arranged
Except other identical element in the process including the key element, method, article or equipment being also present.
A kind of video chaotic secret communication device and method provided by the present invention are described in detail above, herein
In apply specific case to the present invention principle and embodiment be set forth, the explanation of above example is only intended to help
Assistant solves the method and its core concept of the present invention；Meanwhile for those of ordinary skill in the art, the think of according to the present invention
Think, in specific embodiments and applications there will be changes, in summary, this specification content should not be construed as pair
The limitation of the present invention.
Claims (10)
1. a kind of video chaotic secret communication equipment, it is characterised in that including video sending end and video receiver；The video
Transmitting terminal includes the first SOC, the first core buffer and data sending device, and the video receiver includes second
SOC, the second core buffer and data sink；First SOC includes the first FPGA and the first ARM,
Second SOC includes the 2nd FPGA and the 2nd ARM；First FPGA includes the first VDMA and uses AXIS agreements
As the chaos encryption module of interface protocol, the 2nd FPGA includes the 2nd VDMA and using AXIS agreements as interface association
The chaos deciphering module of view；Wherein,
The chaos encryption module, for obtaining original video data by the first VDMA, based on default chaos encryption
Algorithm, the original video data is encrypted, and the encryption that will be obtained by the first VDMA after encryption
Data transfer to first core buffer is preserved；
First ARM, sent out for reading out the encryption data from first core buffer, and by the data
Device is sent to send the encryption data to the data sink；
2nd ARM, for obtaining the encryption data of the data sink transmission, and the encryption data is passed
Second core buffer is transported to be preserved；
The chaos deciphering module, add for obtaining to be stored in described in second core buffer by the 2nd VDMA
Ciphertext data, based on default chaos decipherment algorithm, processing is decrypted to the encryption data, obtains corresponding ciphertext data.
2. video chaotic secret communication equipment according to claim 1, it is characterised in that the chaos encryption module and institute
State signal involved by the AXIS protocol interfaces in chaos deciphering module include tvalid, tdata, tuser, tlast and
Tready signals；
Wherein, handshake of the tvalid and tready between corresponding communicating pair, also, start in the case of high level
Tdata, tuser and tlast signal are communicated, and then suspend data communication in the case of low level.
3. video chaotic secret communication equipment according to claim 2, it is characterised in that the chaos encryption module and institute
It is parallel channel to state the signalling channel in chaos deciphering module；
Wherein, the parallel channel in the chaos encryption module and the chaos deciphering module handle respectively tdata, tuser,
Tlast and control signal.
4. video chaotic secret communication equipment according to claim 3, it is characterised in that the chaos encryption module and institute
The each signalling channel stated in chaos deciphering module is provided with multi-stage pipeline arrangement, is separated simultaneously by d type flip flop per level production line
Work is triggered by system clock, also, strict sequential relationship is kept in the flowing water course of work, between signalling channel.
5. video chaotic secret communication equipment according to claim 4, it is characterised in that
The converter for being used to solve inside and outside data-bus width mismatch problem in the chaos encryption module is parallel/serial conversion
Device；
The converter for being used to solve inside and outside data-bus width mismatch problem in the chaos deciphering module is serial/parallel conversion
Device.
6. video chaotic secret communication equipment according to claim 5, it is characterised in that
The parallel/serial converter is the converter created based on selector and counter；
The serial/parallel converter is the converter created based on shift register.
7. video chaotic secret communication equipment according to claim 6, it is characterised in that
The chaos encryption module, specifically represent close in the chaos encryption algorithm using the form for there are 64 Q32 of symbol
Key parameter and corresponding state variable, and corresponding fixed-point calculation is carried out by hardware multiplier and adder；
The chaos deciphering module, specifically represent close in the chaos decipherment algorithm using the form for there are 64 Q32 of symbol
Key parameter and corresponding state variable, and corresponding fixed-point calculation is carried out by hardware multiplier and adder.
8. video chaotic secret communication equipment according to claim 7, it is characterised in that
The chaos encryption module specifically determines the chaos using ROM lookup table modes during being encrypted
Sine term in AES；
The chaos deciphering module specifically determines the chaos using ROM lookup table modes during processing is decrypted
Sine term in decipherment algorithm.
9. the video chaotic secret communication equipment according to any one of claim 1 to 7, it is characterised in that the video hair
Sending end also includes the 3rd core buffer being connected with the first VDMA；First FPGA also includes video frequency collection card and the
Three VDMA；The video receiver also includes the 4th core buffer being connected with the 2nd VDMA；2nd FPGA is also
Including the 4th VDMA；Wherein,
3rd VDMA, the original video data for the video frequency collection card to be collected are transmitted in the described 3rd
Deposit buffering area to be preserved, so that the first VDMA obtains the original video data from the 3rd core buffer；
4th core buffer, for the decryption obtained by the 2nd VDMA acquisitions chaos deciphering module
Data, and the ciphertext data is preserved；
4th VDMA, carried out for the ciphertext data in the 4th core buffer to be transmitted to display
Display.
A kind of 10. video Development of Chaotic Secure Communication Method, it is characterised in that applied to video chaotic secret communication equipment, wherein, institute
Stating video chaotic secret communication equipment includes video sending end and video receiver；The video sending end includes the first SOC cores
Piece, the first core buffer and data sending device, the video receiver include the second SOC, the second memory buffer
Area and data sink；First SOC includes the first FPGA and the first ARM, and second SOC includes the
Two FPGA and the 2nd ARM；First FPGA is included the first VDMA and added using AXIS agreements as the chaos of interface protocol
Close module, the 2nd FPGA include the 2nd VDMA and using chaos deciphering module of the AXIS agreements as interface protocol；Its
In, methods described includes：
The chaos encryption module obtains original video data by the first VDMA, and is calculated based on default chaos encryption
Method, the original video data is encrypted, the encryption that then will be obtained by the first VDMA after encryption
Data transfer to first core buffer is preserved；
First ARM reads out the encryption data from first core buffer, and is sent and filled by the data
Put and send the encryption data to the data sink；
2nd ARM obtains the encryption data of the data sink transmission, and by the encrypted data transmission extremely
Second core buffer is preserved；
The chaos deciphering module obtains the encryption number for being stored in second core buffer by the 2nd VDMA
According to, and default chaos decipherment algorithm is based on, processing is decrypted to the encryption data, obtains corresponding ciphertext data.
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