CN108008676B - Multi-processing unit relay protection system and synchronization method thereof - Google Patents
Multi-processing unit relay protection system and synchronization method thereof Download PDFInfo
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- CN108008676B CN108008676B CN201711258435.6A CN201711258435A CN108008676B CN 108008676 B CN108008676 B CN 108008676B CN 201711258435 A CN201711258435 A CN 201711258435A CN 108008676 B CN108008676 B CN 108008676B
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Abstract
The invention discloses a multi-processing unit relay protection system and a synchronization method thereof, which adopt a multi-processing unit system architecture, distribute the protection processing process of a single relay protection device into three processing units, namely a front-end sampling processing unit, a front-end computing processing unit and a protection logic processing unit. The method has the advantages that an extra circuit is not introduced, the multiprocessor calculation synchronization is realized only through the closed-loop processing process of sampling the synchronous signal S/H, the multi-device sampling and calculation and the power grid frequency are accurately synchronized, and a good technical platform is provided for realizing the protection function with high requirement on the synchronization precision, such as the line longitudinal differential protection.
Description
Technical Field
The invention belongs to the technical field of power system relay protection, and relates to a multi-processing unit relay protection system and a synchronization method thereof.
Background
With the popularization of smart power grids, the requirement on the data processing capacity of a relay protection device is higher and higher, and in order to ensure the rapidity and the reliability of the protection device, a multi-processing unit system architecture is generally applied to share different data processing and protection calculation tasks. When protection calculation is carried out, a plurality of processing units which are responsible for different calculation tasks are required to be synchronized, so that data consistency and data pipeline synchronization are ensured. Especially in the case of longitudinal differential protection of the line, two or three devices with a distance of tens of kilometers or even more than hundreds of kilometers are required to be synchronized in sampling and calculation, and higher requirements are provided for multi-machine synchronization of a multi-processing unit system.
Disclosure of Invention
The invention aims to provide a multi-processing unit relay protection system and a synchronization method thereof, which are methods for realizing sampling and calculation synchronization among multiple processing units and multiple devices on a multi-processing unit system architecture of a relay protection device, solve the problem of difficult synchronization among the multiple processing units and remote multiple devices in the prior art, realize the synchronization of data sampling and processing among processors of different devices in the whole system, and provide an excellent platform foundation for relay protection application.
In order to achieve the purpose, the technical scheme adopted by the invention is as follows:
a multi-processing unit relay protection system comprises a plurality of relay protection devices which are communicated with each other, wherein each single relay protection device comprises a front-end sampling processing unit, a front-end computing processing unit and a protection logic processing unit;
the front-end sampling processing unit is used for receiving and resampling S/H signals and sending sampling data to the front-end computing processing unit;
the front-end computing processing unit is used for calculating phasor and frequency and putting the calculation result into a shared storage area;
the protection logic processing unit is used for communicating with the far-side relay protection device and reading a phasor value from the shared storage area; and generating a system sampling synchronization signal S/H signal through proportion adjustment calculation, and sending the system sampling synchronization signal S/H signal to the front-end sampling processing unit and the front-end calculation processing unit to synchronize the sampling and calculation period with the S/H signal.
The front-end computing processing unit is also used for sending an interrupt signal to the protection logic processing unit once the S/H signal is received; and the protection logic processing unit reads the phasor value from the shared storage area after receiving the interrupt signal.
The front-end computing processing unit takes one sampling point data from the receiving buffer area every time an S/H signal is received, and takes N sampling point data every time N sampling points are receivedpassCarrying out primary phasor and frequency calculation on each sampling point data; wherein N ispassN/N, N samples per cycle, T intervals calculated by the processorpassDividing each power grid cycle time into n integer numbers of TpassThen each TpassTreatment of NpassThe sampling point data.
The protection logic processing unit is used for inputting the difference value of the sampling frequency and the grid frequency and the difference value of the sampling phase angles at two sides into the frequency-locking phase-locked loop for calculation, outputting a new S/H signal frequency value, continuously adjusting the S/H signal interval, and finally realizing the synchronization between the relay protection devices, and the S/H signal frequency fnInfinitely close to the grid frequency f.
A synchronization method for a multi-processing unit relay protection system for one of a plurality of intercommunicating relay protection devices, the synchronization method comprising the steps of:
a presynchronization step, namely sending S/H signals for triggering sampling by synchronizing with a far-side relay protection device and the frequency of a power grid, and sending N S/H signal pulses at equal intervals every cycle;
a sampling step of receiving and resampling an S/H signal;
calculating, namely calculating phasor and frequency, and putting a calculation result into a shared storage area;
and a logic processing step, reading the phasor value from the shared storage area, and generating a system sampling synchronization signal S/H signal through proportion adjustment calculation so that the sampling and calculation periods of the relay protection device and the far-side relay protection device are synchronous with the S/H signal.
As a further improvement of the present invention, in the calculating step, an interrupt signal is sent once every time an S/H signal is received; in the logic processing step, the phasor value is read from the shared memory area after receiving the interrupt signal.
As a further improvement of the invention, in the calculating step, one sampling point data is taken from the receiving buffer every time the S/H signal is received, and every time N is receivedpassCarrying out primary phasor and frequency calculation on each sampling point data; wherein N ispassN/N, N samples per cycle, T intervals calculated by the processorpassDividing each power grid cycle time into n integer numbers of TpassThen each TpassTreatment of NpassThe sampling point data.
As a further improvement of the invention, in the logic processing step, the difference value of the sampling frequency and the power grid frequency and the difference value of the sampling phase angles at two sides are input into the frequency-locking phase-locked loop for calculation, a new S/H signal frequency value is output, the S/H signal interval is continuously adjusted, and finally the synchronization between the relay protection devices is realized, and the S/H signal frequency fnInfinitely close to the grid frequency f.
As a further improvement of the invention, the logic processing steps are specifically as follows:
reading phasor values from the shared storage area, counting S/H signal pulses while sending the S/H signal pulses, and performing ping-pong timing by mutually sending recorded count values with a far-side relay protection device; the difference value of the sampling frequency and the grid frequency is compared with two sidesThe sampling phase angle difference value is input into a frequency-locked phase-locked loop to carry out proportion regulation calculation, and a new sampling frequency value f is outputnAnd according to the S/H signal frequency, until the counting phase difference of the two relay protection devices is an integral multiple of N, the counting sampling phase angle difference of the two relay protection devices is approximately equal to 0, and the S/H signal frequency fnApproximately equal to the grid frequency f, at which point the PLL phase lock succeeds.
Compared with the prior art, the invention has the following advantages:
the synchronous system is composed of two or three sets of relay protection devices which are positioned at different physical positions and based on a multi-processing unit system framework, synchronous data sampling and calculation processing are carried out among processing units in the device and among the devices, a protection logic processing unit is communicated with a far-side relay protection device, a phasor value is read from a shared storage area, a system sampling synchronous signal S/H signal is generated through proportion regulation calculation and sent to a front-end sampling processing unit and a front-end calculation processing unit, and the sampling and calculation period of the system sampling synchronous signal S/H signal S/. The system does not introduce an extra circuit, realizes the calculation synchronization of a plurality of processors only through the closed-loop processing process of sampling a synchronous signal S/H signal, realizes the accurate synchronization of the sampling and calculation of the plurality of devices and the frequency of a power grid, and provides a good technical platform for realizing the protection function with high requirement on the synchronization precision, such as the longitudinal differential protection of a circuit.
The method comprises a pre-synchronization step, a sampling step, a calculation step and a logic processing step, wherein a system sampling synchronization signal S/H signal is generated through proportion adjustment calculation, so that the sampling and calculation periods of the relay protection device and a far-side relay protection device are synchronous with the S/H signal, and the synchronization of data sampling and processing among processors of different devices in the whole system is realized; the method has high synchronization efficiency and accurate synchronization, and ensures the data consistency and the synchronization of the data pipeline.
Drawings
FIG. 1 is a diagram of a multi-processing unit relay protection system architecture according to the present invention;
fig. 2 is a schematic diagram of the synchronization method of the present invention.
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.
A typical multi-processing unit relay protection system architecture of the present invention is shown in fig. 1. The principle of the synchronization method is shown in fig. 2.
The multi-processing unit relay protection device synchronization system adopts a multi-processing unit system architecture, and the protection processing process of a single relay protection device is distributed in three processing units, namely a front-end sampling processing unit, a front-end computing processing unit and a protection logic processing unit.
The front-end sampling processing unit is responsible for A/D data sampling in the traditional relay protection device and is responsible for SV receiving and resampling in the intelligent relay protection device. The front-end computing processing unit is responsible for phasor calculation. The protection logic processing unit is responsible for protection logic calculation and fault discrimination, and is also responsible for optical fiber communication with a far-side device.
The system sampling synchronization signal S/H signal (sampleCount) is generated by the protection logic processing unit and sent to the front-end sampling processing unit and the front-end computing processing unit, and the sampling and computing periods among the processing units are strictly synchronized with the S/H signal, so that the synchronization among the processors is realized. The protection logic processing unit and the far-side device perform ping-pong time synchronization based on S/H signal counting, the difference value of the sampling frequency and the power grid frequency and the difference value of the sampling phase angles at two sides are input into an internal software frequency-locking phase-locked loop for calculation, a new S/H signal frequency value is output, the S/H signal interval is continuously adjusted, and finally synchronization between the devices is realized, and the S/H signal frequency fnInfinitely close to the grid frequency f.
The whole system samples the input alternating current signal at fixed sampling points of each cycle, the number of sampling points of each cycle is N, and the processor calculates the interval to be TpassDividing each power grid cycle time into n integer numbers of TpassThen each TpassTreatment of NpassThe sampling point data.
For example, if N is 64 and N is 8, then N ispass＝N/n＝64/8＝8。
The protection logic processing unit sends S/H signal pulses for triggering sampling to the front-end sampling processing unit through synchronizing with the far-side protection logic processing unit and the power grid frequency, and N S/H signal pulses with equal intervals are sent every cycle.
The front-end sampling processor receives the S/H signal, immediately carries out data sampling once and sends the sampled data to the front-end computing processing unit.
The front-end computing processing unit takes a sampling point data from the receiving buffer area every time the S/H signal is received, and every time the N sampling point data is receivedpassAnd carrying out primary phasor and frequency calculation on the sampling point data, and putting the calculation result into a shared storage area. At the same time, every received NpassThe S/H signal sends an interrupt signal to the protection logic processing unit.
And the protection logic processing unit reads the phasor value from the shared storage area after receiving the interrupt signal. The protection logic processing unit counts S/H signal pulses while sending out the S/H pulses, namely, the S/H signal pulses are sampleCount, and ping-pong time synchronization is carried out by mutually sending the recorded sampleCount value with the opposite side protection logic processing unit. The protection logic processing unit inputs the difference value of the sampling frequency and the power grid frequency and the difference value of the sampling phase angles at two sides into a frequency-locked phase-locked loop (PLL) for proportional adjustment calculation, and outputs a new sampling frequency value fnAccording to fnAdjusting the sampling interval, i.e. the S/H signal frequency, until the SampleCount difference on both sides is an integer multiple of N, the sampling phase angle difference on both sides is approximately equal to 0, and the S/H frequency fnApproximately equal to the grid frequency f, at which point the PLL phase lock succeeds. f. ofnIs calculated to adjust the period TsynThat is, the operation period of the frequency-locked phase-locked loop is generally set to be an even number of TpassThe receiving and transmitting period of SampleCount and phasor angle in ping-pong timing is also TsynAnd it is necessary to ensure that the protection logic processing unit is at TsynAnd sending and receiving the SampleCount at a fixed time of a cycle to ensure that the communication channels are symmetrical in time delay.
Fig. 2 shows the principle of two-sided device synchronization, and three-sided device synchronization can also be referred to in this method, where one device is set as the master and the other two devices are synchronized in this way.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, and all equivalent changes and modifications made within the scope of the present invention should be considered as the technical scope of the present invention.
Claims (8)
1. A multi-processing unit relay protection system is characterized by comprising a plurality of relay protection devices which are communicated with each other, wherein each single relay protection device comprises a front-end sampling processing unit, a front-end computing processing unit and a protection logic processing unit;
the front-end sampling processing unit is used for receiving and resampling S/H signals and sending sampling data to the front-end computing processing unit;
the front-end computing processing unit is used for calculating phasor and frequency and putting the calculation result into a shared storage area;
the protection logic processing unit is used for communicating with the far-side relay protection device and reading a phasor value from the shared storage area; generating a system sampling synchronization signal S/H signal through proportion adjustment calculation, and sending the system sampling synchronization signal S/H signal to the front-end sampling processing unit and the front-end calculation processing unit to synchronize the sampling and calculation period with the S/H signal; the device is also used for reading the phasor value from the shared storage area, counting the S/H pulse while sending out the S/H pulse, and carrying out ping-pong time synchronization by mutually sending the recorded count value with the far-side relay protection device; inputting the difference value of the sampling frequency and the grid frequency and the difference value of the sampling phase angles at two sides into a frequency-locked phase-locked loop for proportional adjustment calculation, and outputting a new sampling frequency value fnAnd according to the S/H signal frequency, until the counting phase difference of the two relay protection devices is an integral multiple of N, the sampling phase angle difference of the two relay protection devices is approximately equal to 0, and the S/H frequency fnApproximately equal to the grid frequency f, at which point the PLL phase lock succeeds.
2. The multi-processing unit relay protection system of claim 1, wherein the front end computing unit is further configured to receive N timespassThe S/H signals send a primary interrupt signal to the protection logic processing unit; the protection logic processing unit reads phasor from the shared memory area after receiving the interrupt signalThe value is obtained.
3. The multi-processing unit relay protection system of claim 1, wherein the front-end computing unit obtains a sampling point data from the receiving buffer every time it receives an S/H signal, and obtains a sampling point data from the receiving buffer every time it receives N signalspassCarrying out primary phasor and frequency calculation on each sampling point data; wherein N ispassN/N, N samples per cycle, T intervals calculated by the processorpassDividing each power grid cycle time into n integer numbers of TpassThen each TpassTreatment of NpassThe sampling point data.
4. The multi-processing unit relay protection system according to claim 1, wherein the protection logic processing unit is configured to input a difference between the sampling frequency and the grid frequency and a difference between sampling phase angles at two sides into the frequency-locked phase-locked loop for calculation, output a new S/H signal frequency value, and continuously adjust an S/H signal interval, thereby finally realizing synchronization between the relay protection devices, and the S/H signal frequency f isnInfinitely close to the grid frequency f.
5. A synchronization method for a multi-processing unit relay protection system, for one of a plurality of relay protection devices communicating with each other, the synchronization method comprising the steps of:
a presynchronization step, namely sending S/H signals for triggering sampling by synchronizing with a far-side relay protection device and the frequency of a power grid, and sending N S/H signal pulses at equal intervals every cycle;
a sampling step of receiving and resampling an S/H signal;
calculating, namely calculating phasor and frequency, and putting a calculation result into a shared storage area;
a logic processing step, reading the phasor value from the shared storage area, and generating a system sampling synchronization signal S/H signal through proportion adjustment calculation so that the sampling and calculation periods of the relay protection device and the far-side relay protection device are synchronous with the S/H signal; the logic processing steps are as follows:
reading phasor values from the shared storage area, counting S/H pulses while sending out the S/H pulses, and sending recorded count values to a far-side relay protection device for a ping-pong time synchronization mechanism; inputting the difference value of the sampling frequency and the grid frequency and the difference value of the sampling phase angles at two sides into a frequency-locked phase-locked loop for proportional adjustment calculation, and outputting a new sampling frequency value fnAnd according to the S/H signal frequency, until the counting phase difference of the two relay protection devices is an integral multiple of N, the sampling phase angle difference of the two relay protection devices is approximately equal to 0, and the S/H frequency fnApproximately equal to the grid frequency f, at which point the PLL phase lock succeeds.
6. The synchronization method of multi-processing unit relay protection system according to claim 5, wherein in the calculating step, every N receivedpassSending a primary interrupt signal by each S/H signal; in the logic processing step, the phasor value is read from the shared memory area after receiving the interrupt signal.
7. The synchronization method of multi-processing unit relay protection system as claimed in claim 5, wherein in the calculating step, a sampling point data is obtained from the receiving buffer every time an S/H signal is received, and every time N is receivedpassCarrying out primary phasor and frequency calculation on each sampling point data; wherein N ispassN/N, N samples per cycle, T intervals calculated by the processorpassDividing each power grid cycle time into n integer numbers of TpassThen each TpassTreatment of NpassThe sampling point data.
8. The synchronization method of the multi-processing unit relay protection system according to claim 5, wherein in the logic processing step, the difference between the sampling frequency and the grid frequency and the difference between the sampling phase angles at two sides are input into the frequency-locked phase-locked loop for calculation, a new S/H signal frequency value is output, the S/H signal interval is continuously adjusted, and finally the synchronization between the relay protection devices is realized, and the S/H signal frequency fnInfinitely close to the grid frequency f.
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