CN107844321A - A kind of MCU processing systems - Google Patents
A kind of MCU processing systems Download PDFInfo
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- CN107844321A CN107844321A CN201610837925.0A CN201610837925A CN107844321A CN 107844321 A CN107844321 A CN 107844321A CN 201610837925 A CN201610837925 A CN 201610837925A CN 107844321 A CN107844321 A CN 107844321A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/22—Microcontrol or microprogram arrangements
- G06F9/223—Execution means for microinstructions irrespective of the microinstruction function, e.g. decoding of microinstructions and nanoinstructions; timing of microinstructions; programmable logic arrays; delays and fan-out problems
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/22—Microcontrol or microprogram arrangements
- G06F9/26—Address formation of the next micro-instruction ; Microprogram storage or retrieval arrangements
- G06F9/261—Microinstruction address formation
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/22—Microcontrol or microprogram arrangements
- G06F9/28—Enhancement of operational speed, e.g. by using several microcontrol devices operating in parallel
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Abstract
The present invention provides a kind of MCU processing systems, including：Data storage, ALU arithmetic elements, data selector and address selector；The address selector is connected to the data storage, and the data storage is connected to the data selector by data/address bus；The data selector is connected with the input of the ALU arithmetic elements.The MCU processing systems it is more efficient.
Description
Technical field
The present invention relates to electronic technology field, more particularly to a kind of MCU processing systems.
Background technology
Micro-control unit (Microcontroller Unit, MCU), also known as one chip microcomputer (Single Chip
Microcomputer) or single-chip microcomputer, it is that one kind can be central processing unit (Central Process Unit, CPU) frequency
Rate and specification do appropriate reduction, and can by internal memory (memory), counter (Timer), USB, A/D conversion, UART, PLC,
The perimeter interfaces such as DMA, or even the external circuit such as LCD drive circuits can be incorporated on one chip, the chip-scale of formation
Computer, think that various combination control is done in different application scenarios.Such as mobile phone, PC periphery, remote control, automotive electronics, industry
On stepper motor, robotic arm control etc., all visible MCU figure.
The efficiency that existing MCU processing systems are operated to the data in data storage has to be hoisted.
The content of the invention
Present invention solves the technical problem that it is to lift the effect that MCU processing systems are operated to the data in data storage
Rate.
In order to solve the above technical problems, the embodiment of the present invention provides a kind of MCU processing systems, including：Data storage,
ALU arithmetic elements, data selector and address selector；The address selector is connected to the data storage, the number
The data selector is connected to by data/address bus according to memory；The data selector is defeated with the ALU arithmetic elements
Enter end to be connected.
Optionally, the data storage includes multiple memory cell, and the address selector is suitable to be based on direct addressin
Instruction decoding result, choose the memory cell in the data storage.
Optionally, the data selector is suitable to based on direct addressing instruction decoding result, total by the data
Line reads the data of the selected memory cell, and the data of the memory cell are provided to the ALU arithmetic elements.
Optionally, the output end of the ALU arithmetic elements is connected to the data storage by the data/address bus.
Optionally, the ALU arithmetic elements are suitable to operation result writing the address choice by the data/address bus
The memory cell that device is chosen.
Optionally, the MCU processing systems also include：Command register, the command register are respectively connecting to described
Address selector and the data selector.
Optionally, the MCU processing systems also include：Register group, the register group are suitable to the ALU computings list
Member provides the operation result of data and/or storage from the ALU arithmetic elements.
Optionally, the address selector is suitable to, based on indirect addressing instructions decoding result, obtain from the register group
Address, to choose the memory cell that the address is pointed in the data storage according to the address.
Optionally, the MCU processing systems are applicable reduced instruction set computer.
Optionally, the data storage is SRAM.
Compared with prior art, the technical scheme of the embodiment of the present invention has the advantages that：
In embodiments of the present invention, MCU processing systems include data storage, ALU arithmetic elements, data selector and ground
Location selector.Wherein, address selector is connected to data storage, and data storage is connected to data by data/address bus and selected
Device, data selector are connected with the input of ALU arithmetic elements.Thus, address selector can be directly to data storage
To be selected, the data in data storage directly can reach ALU arithmetic elements by data/address bus and data selector, from
And cause ALU arithmetic elements to obtain the data of data storage indirectly by register group, it is possible thereby to so that
The efficiency that the lifting of MCU processing systems is operated to the data in data storage.
Further, data storage includes multiple memory cell, and address selector can be based on direct addressing instruction and decode
As a result, the memory cell in the data storage is chosen.Thus, it is possible to simplification is chosen to memory cell in data storage
Process, further lift the efficiency operated to the data in data storage.
Further, the output end of ALU arithmetic elements is connected to data storage by bus, and ALU arithmetic elements can be straight
The memory cell for choosing operation result by data/address bus writing address selector is connect, without being stored in by operation result
After register group, then the memory cell by the data storage in register group to data storage, so as to reduce operation step
Suddenly, the efficiency operated to memory cell can further be lifted.
Brief description of the drawings
Fig. 1 is a kind of structural representation of MCU processing systems in the embodiment of the present invention.
Embodiment
As it was previously stated, the efficiency that existing MCU processing systems are operated to the data in data storage have it is to be hoisted.
Study and find through inventor, in existing MCU processing systems, directly the data in data storage can not be carried out
Arithmetic operation, when the data in data storage carry out arithmetic operation, it is necessary to be realized by a plurality of instruction, efficiency compared with
It is low.For example, when the data in data register carry out add operation, it is necessary to first by the data read-out in data storage extremely
After register group, add operation is carried out using the data stored in register group, operating procedure is more.
In embodiments of the present invention, MCU processing systems include data storage, ALU arithmetic elements, data selector and ground
Location selector.Wherein, address selector is connected to data storage, and data storage is connected to data by data/address bus and selected
Device, data selector are connected with the input of ALU arithmetic elements.Thus, address selector can be directly to data storage
To be selected, the data in data storage directly can reach ALU arithmetic elements by data/address bus and data selector, from
And cause ALU arithmetic elements to obtain the data of data storage indirectly by register group, it is possible thereby to so that
The efficiency that the lifting of MCU processing systems is operated to the data in data storage.
It is understandable to enable above-mentioned purpose, feature and the beneficial effect of the present invention to become apparent, below in conjunction with the accompanying drawings to this
The specific embodiment of invention is described in detail.
Fig. 1 is a kind of structural representation of MCU processing systems in the embodiment of the present invention.
As shown in figure 1, the MCU processing systems in the present embodiment mainly include：Data storage 11, ALU arithmetic elements 12,
Data selector 13 and address selector 14.In addition, the MCU processing systems can also include data/address bus 17 and register group
16。
Wherein, the output end of the address selector 14 is connected to the data storage 11, the data storage 11
The input of the data selector 13 is connected to by data/address bus 17；The output end of the data selector 13 with it is described
The input of ALU arithmetic elements 12 is connected.
Because data storage 11 by data/address bus 17 is connected to data selector 13, data selector 13 and ALU is transported
The input for calculating unit 12 is connected, therefore ALU arithmetic elements 12 can be obtained directly by data/address bus 17 and data selector 13
Take the data in data storage 11, it is not necessary to transfer is carried out by register group 16, so as to be lifted to data storage 11
In data carry out arithmetic operation efficiency.
In specific implementation, data storage 11 can include multiple memory cell, and memory cell therein can be by ground
Location selector 14 is chosen, and then can carry out data read-write operation to selected memory cell.Address selector 14 can be with base
Result is decoded in direct addressing instruction, chooses the memory cell in the data storage 11.
One in the specific implementation, entering row decoding to direct addressing instruction by command register 15, direct addressing instruction is generated
Decode result.Address of the data in need operated in data storage 11 is carried in direct addressing instruction.The address
It can be transmitted by address selector 14 to data storage 11, so as to choose depositing for address sensing in data storage 11
Storage unit.It should be noted that direct addressing instruction can be with any support in the instruction set of the direct addressin of data storage 11
Instruction, however it is not limited to particular, instruction set.
Existing MCU processing systems are when the data in data storage calculate, it is necessary to be referred to based on indirect addressing
Order, namely access unit address to be chosen first is stored in register group, address selector is further according to indirect addressing instructions
Decoding result obtains access unit address from register group and selected and arithmetic operation is carried out to memory cell.
For example, in the data in needing acquisition data storage, it is necessary to by the address assignment of data into register group
Some register, the mode of indirect addressing is recycled, by the digital independent stored in memory cell to its in register group
His register, the data read to register are further operated again afterwards.
And in the embodiment of the present invention, address selector 14 can be based on direct addressing instruction directly in data storage 11
Memory cell chosen, the data of the memory cell chosen via data deposit bus 17 and data selector 13 transmit to
ALU arithmetic elements 12, without access unit address to be chosen first is stored in into register group 16.Thus, it is possible to simplified pair
The process chosen with data acquisition of memory cell in data storage 11, lifts the effect operated to data storage 11
Rate.
In specific implementation, the data selector 13 can be based on direct addressing instruction decoding result, pass through institute
State data/address bus 17 and obtain the data of the selected memory cell, and the data of the memory cell are provided to described
ALU arithmetic elements 12.
In existing MCU processing systems, ALU arithmetic elements can only obtain the number in data storage by register group
According to, and in embodiments of the present invention, ALU arithmetic elements 12 directly can obtain number by data/address bus 17 and data selector 13
According to the data in memory 11, therefore the efficiency of MCU processing systems can be lifted.
In specific implementation, the MCU processing systems can also include command register 15, and command register 15 connects respectively
To the input of address selector 14 and the input of data selector 13.Command register 15 can to instructing into row decoding,
And address selector 14 and data selector 13 can be controlled, such as by decoding result caused by decoding to address
Selector 14 and data selector 13 are controlled.
More specifically, address and data can be included by decoding in result, address is transmitted to address selector 14, data and passed
Transport to data selector 13.Control signal can also be included in decoding result, to control address selector 14 from multiple inputs
Address in select appropriate address to export, and control data selector 13 selected from the data of multiple inputs it is appropriate
Data output.
For example, command register 15 can be connected by decoding result or other appropriate mode control data selectors 13
Logical data/address bus 17 and ALU arithmetic elements 12, to allow ALU arithmetic elements 12 to obtain data storage from data/address bus 17
Data in 11, to carry out follow-up computing.
In specific implementation, the output end of the ALU arithmetic elements 12 can be connected to institute by the data/address bus 17
State data storage 11.Accordingly, the operation result of the ALU arithmetic elements 12 can write institute by the data/address bus 17
State the memory cell that address selector 14 is chosen.
In existing MCU processing systems, when calculating the data in data storage, it is necessary to first by data storage
In digital independent to register；After ALU arithmetic elements complete computing, operation result is back to register；Again will deposit
Numerical value write back data memory in device.
And in the embodiment of the present invention, ALU arithmetic elements 12 can directly be obtained without register by data/address bus 17
Data in data storage 11, and after ALU arithmetic elements 12 complete computing, will directly can be transported by data/address bus 17
Calculate result and write back former memory cell.Thus, the MCU processing systems in the embodiment of the present invention are operated to data storage 11
Process is simpler, more efficient.
In specific implementation, the register group 16 in MCU processing systems can provide data to ALU arithmetic elements 12, deposit
Store up the operation result from the ALU arithmetic elements 12 and/or provide address to address selector 14.
MCU processing systems in the embodiment of the present invention can support the mode of indirect addressing to choose data storage 11 simultaneously
In memory cell.Specifically, address selector 14 can be based on indirect addressing instructions decoding result, from the register group 16
Address is obtained, to choose the memory cell that the address is pointed in the data storage 11 according to the address.
In specific implementation, multiple register groups that register group 16 includes can be divided into master register combination auxiliary deposit
Device group, wherein master register group support the access of all instructions for being related to the operation of register group 16, and background register group is only
A part is supported to be related to the access of the instruction of the operation of register group 16.
In a non-limitative example, multiple register group R0-R7 that register group 16 includes can be divided into main deposit
Device group R0-R3, and background register group R4-R7.Wherein, it is related to all instructions of the operation of register group 16, can be right
Master register group R0-R3 is operated；And only part instruction can operate to background register group R4-R7.
Only master register group R0-R3 supports all operations for being related to register group 16, can cause register group 16
The digit that is taken in instruction system of address it is less；When necessary, part instruction can be carried out to background register group R4-R7
Operation so that background register group R4-R7 is as the supplement to master register group R0-R3.Thus, it is possible to ensureing systematic function
While reduce the resource that register group 16 takes in instruction system.
MCU processing systems in the embodiment of the present invention can be applicable reduced instruction set computer, and data storage 11 therein can be with
It is SRAM, such as on-chip SRAM.This MCU processing system can be fully integrated on a single chip, namely the modules in Fig. 1
All integrate on a single chip, or can also be partially integrated on one single chip.
For the MCU processing systems in the embodiment of the present invention are described in detail, below with suitable for of the invention real
Apply and be further detailed exemplified by the specific instruction and implementation procedure of the MCU processing systems of example.
In an embodiment of the present invention, can in a manner of direct addressin read data memory data, data are deposited
After the data in data and register in reservoir are calculated, result is stored to data storage.For example, it can perform such as
Give an order：
ADD 0x80, R0 (1)
By instructing (1) can be added register R0 with the data in memory cell 0x80, and result of calculation is stored
To the memory cell that address is 0x80.
During execute instruction (1), command register enters row decoding to instruction (1), decodes obtained decoding result
In include access unit address, decoding result of the address selector based on command register, choose the storage that address is 0x80
Unit, wherein the data stored are transmitted to ALU arithmetic elements via data/address bus and data selector.ALU arithmetic elements according to
The instruction of the decoding result of command register, obtain the data stored in register R0, by the data stored in register R0 with
Data in memory cell 0x80 are added, and obtain operation result.
Based on the decoding result of instruction (1), ALU arithmetic elements can be deposited operation result write-in data by data/address bus
Address is 0x80 memory cell in reservoir, and in ablation process, address selector chooses the memory cell that address is 0x80.If
The calculating process of instruction (1) is realized, it is necessary to by a plurality of instruction based on existing MCU processing systems, such as：
MOV R1, #0x80 (2)
LD R2, [R1] (3)
ADD R2, R0 (4)
ST [R1], R2 (5)
Wherein：By instructing (2), register R1 content is entered as access unit address 0x80；In instruction (3)
In, addressed the data in register R1 as access unit address, the data in memory cell for being 0x80 by address are assigned
It is worth and gives register R2；In (4) are instructed, the data in register R0 are added with the data in register R2, and by computing knot
Fruit is stored to register R2；In (5) are instructed, the operation result preserved in register R2 is written back to the storage that address is 0x80
Unit.
By comparing as can be seen that MCU processing systems only need 1 i.e. achievable computing of instruction to exist in the embodiment of the present invention
4 instructions are needed just to complete in existing MCU processing systems, therefore the efficiency of the MCU processing systems in the embodiment of the present invention
It is higher.
In an alternative embodiment of the invention, can in a manner of direct addressin read data memory data, by data
The data in data and register in memory are calculated, and result is stored to register.For example, it can perform as follows
Instruction：
ADD R0,0x80 (6)
By instructing (6) can be added address with the data in register R0 for the data in 0x80 memory cell,
Operation result is stored to R0.
During execute instruction (6), command register enters row decoding to instruction (6), and address selector is based on decoding
Result choose the memory cell that address in data storage is 0x80；Control of the data selector based on command register, even
Logical ALU arithmetic elements and data/address bus so that it is 0x80 that ALU arithmetic elements obtain address via data/address bus and data selector
Memory cell in data.Decoding result based on command register, ALU arithmetic elements obtain the data in register R0,
And the data in the data and R0 in the memory cell for being 0x80 to address are summed, and result is stored to register R0.
If instruction (6) is realized in existing MCU processing systems, it is necessary to 3 instructions could be completed, such as：
MOV R1, #0x80
LD R2, [R1]
ADD R0, R2
The implication of each bar instruction may refer to will not be repeated here to (4) in instruction (2) in above-mentioned three instructions.
MCU processing systems in the embodiment of the present invention can also be supported to carry out data storage its elsewhere of direct addressin
Reason instruction, such as：SUB 0x80, R1；SUB R1,0x80 etc., will not enumerate herein.
MCU processing systems in the embodiment of the present invention can also compatible existing MCU processing systems instruction, such as oppose
The computing of data i.e. in number and register, to the computing of data in register, the data based on register indirect addressing load etc.,
Including but not limited to：ADD R0, #0x01；ADD R0, R1；LD R2, [R1] etc..
In embodiments of the present invention, MCU processing systems include data storage, ALU arithmetic elements, data selector and ground
Location selector.Wherein, address selector is connected to data storage, and data storage is connected to data by data/address bus and selected
Device, data selector are connected with the input of ALU arithmetic elements.Thus, address selector can be directly to data storage
To be selected, the data in data storage directly can reach ALU arithmetic elements by data/address bus and data selector, from
And cause ALU arithmetic elements to obtain the data of data storage indirectly by register group, it is possible thereby to so that
The efficiency that the lifting of MCU processing systems is operated to the data in data storage.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, this is not being departed from
In the spirit and scope of invention, it can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
The scope of restriction is defined.
Claims (10)
- A kind of 1. MCU processing systems, it is characterised in that including：Data storage, ALU arithmetic elements, data selector and address Selector；The address selector is connected to the data storage, and the data storage is connected to the number by data/address bus According to selector；The data selector is connected with the input of the ALU arithmetic elements.
- 2. MCU processing systems according to claim 1, it is characterised in that it is single that the data storage includes multiple storages Member, the address selector are suitable to, based on direct addressing instruction decoding result, choose the memory cell in the data storage.
- 3. MCU processing systems according to claim 2, it is characterised in that the data selector is suitable to based on described straight Addressing instruction decoding result is connect, the data of the selected memory cell are read by the data/address bus, and deposit described The data of storage unit are provided to the ALU arithmetic elements.
- 4. MCU processing systems according to claim 2, it is characterised in that the output end of the ALU arithmetic elements passes through institute State data/address bus and be connected to the data storage.
- 5. MCU processing systems according to claim 4, it is characterised in that the ALU arithmetic elements are suitable to operation result The memory cell chosen by the data/address bus write-in address selector.
- 6. MCU processing systems according to claim 1, it is characterised in that also include：Command register, the instruction are posted Storage is respectively connecting to the address selector and the data selector.
- 7. MCU processing systems according to claim 1, it is characterised in that also include：Register group, suitable for the ALU Arithmetic element provides the operation result of data and/or storage from the ALU arithmetic elements.
- 8. MCU processing systems according to claim 7, it is characterised in that the address selector is suitable to be based on seeking indirectly Location Instruction decoding result, address is obtained from the register group, to choose institute in the data storage according to the address State the memory cell of address sensing.
- 9. the MCU processing systems according to any one of claim 1 to 8, it is characterised in that the MCU processing systems are applicable Reduced instruction set computer.
- 10. the MCU processing systems according to any one of claim 1 to 8, it is characterised in that the data storage is SRAM。
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| WO2020172988A1 (en) * | 2019-02-28 | 2020-09-03 | Huawei Technologies Co., Ltd. | Shader alu outlet control |
| CN113440403A (en) * | 2020-07-05 | 2021-09-28 | 上海宏勃生物科技发展有限公司 | System capable of detecting bath entering and bath exiting of patient |
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| CN110609705B (en) * | 2019-09-20 | 2021-05-11 | 深圳市航顺芯片技术研发有限公司 | Method for improving MCU bus efficiency, intelligent terminal, storage medium and chip |
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