CN108108189A

CN108108189A - A kind of computational methods and Related product

Info

Publication number: CN108108189A
Application number: CN201711362617.8A
Authority: CN
Inventors: 胡帅; 刘恩赫; 张尧; 孟小甫
Original assignee: Beijing Zhongke Cambrian Technology Co Ltd
Current assignee: Anhui Cambricon Information Technology Co Ltd
Priority date: 2017-12-15
Filing date: 2017-12-15
Publication date: 2018-06-01
Anticipated expiration: 2037-12-15
Also published as: CN108108189B; CN112230994A

Abstract

Present disclose provides a kind of computational methods and Related product, the method is applied in computing device, and the computing device includes：Storage medium, register cell and matrix calculation unit；Described method includes following steps：The computing device controls the matrix calculation unit to obtain the first operational order, and the matrix that first operational order includes performing needed for described instruction reads instruction；The computing device controls the arithmetic element to read instruction according to the matrix and sends reading order to the storage medium；The computing device controls the arithmetic element to indicate corresponding matrix according to using the batch reading manner reading matrix reading, and first operational order is performed to the matrix.The technical solution that the application provides has the advantages of calculating speed is fast, efficient.

Description

A kind of computational methods and Related product

Technical field

This application involves technical field of data processing, and in particular to a kind of computational methods and Related product.

Background technology

Data processing is the step of most of algorithm needs to pass through or stage, after computer introduces data processing field, More and more data processings realize have computing device carrying out the calculating of matrix data in existing algorithm by computer Shi Sudu is slow, and efficiency is low.

Apply for content

The embodiment of the present application provides a kind of computational methods and Related product, can promote the processing speed of computing device, carry High efficiency.

In a first aspect, provide a kind of computational methods, applied in computing device, the computing device include storage medium, Register cell and matrix operation unit, the described method includes：

The computing device controls the matrix operation unit to obtain the first operational order, and first operational order is used for Realize the computing between matrix and scalar, the matrix that first operational order includes performing needed for described instruction reads instruction, The required matrix is at least one matrix, and at least one matrix is the matrix that length is identical or length is different；

The computing device controls the matrix operation unit to read instruction according to the matrix and is sent out to the storage medium Send reading order；

The computing device controls the matrix operation unit to be read using batch reading manner from the storage medium The matrix reads the corresponding matrix of instruction, and performs first operational order to the matrix.

It is described that matrix execution first operational order is included in some possible embodiments：

The computing device controls the matrix operation unit to be held using the calculation of multistage pipelining-stage to the matrix Row first operational order.

In some possible embodiments, each pipelining-stage in the multistage pipelining-stage includes at least one computing Device,

The computing device controls the matrix operation unit to be held using the calculation of multistage pipelining-stage to the matrix Row first operational order includes：

The computing device controls the matrix operation unit to utilize first order pipelining-stage according to the selection of multiple selector In first choice arithmetic unit to the matrix be calculated first as a result, first result is input to second level stream The second Selecting operation device execution in water grade be calculated second as a result, and so on, until inputting (i-1)-th result to the I-th of result is calculated in the i-th Selecting operation device execution in i grades of pipelining-stages；

I-th of result is inputted to the storage medium and is stored；

Wherein, the quantity i of the multistage pipelining-stage is determined according to the calculating topological structure of first operational order, And i is positive integer.

In some possible embodiments, each pipelining-stage in the multistage pipelining-stage is each configured with corresponding multichannel Selector, the multiple selector setting are free option, and the sky option is used to indicate the kth being connected with the multiple selector Grade pipelining-stage and subsequent kth+1 to i-stage pipelining-stage not perform calculating operation, wherein, k is less than or equal to i just Integer.

In some possible embodiments, it is described multistage pipelining-stage in each pipelining-stage included by arithmetic unit and institute The quantity for stating arithmetic unit is by user side or the self-defined setting in computing device side.

In some possible embodiments, each pipelining-stage in the multistage pipelining-stage includes pre-set fixation Arithmetic unit, the fixation arithmetic unit in each pipelining-stage differ,

The computing device controls the matrix operation unit using the fixation arithmetic unit in first order pipelining-stage to described Matrix be calculated first as a result, the fixation arithmetic unit first result being input in the pipelining-stage of the second level performs Be calculated second as a result, and so on, until (i-1)-th result inputted to the fixation arithmetic unit in i-stage pipelining-stage holding I-th of result is calculated in row；

I-th of result is inputted to the storage medium and is stored；

In some possible embodiments, the arithmetic unit in the multistage pipelining-stage in each pipelining-stage include it is following in Any one or multinomial combination：Addition of matrices arithmetic unit, matrix multiplication operation device, matrix scalar multiplication arithmetic unit, non-linear fortune Calculate device and matrix comparison operation device.

In some possible embodiments, first operational order includes any one of following：Matrix Calculating determinant Command M DET, Matrix Calculating order command M RANK, Matrix Calculating mark command M TRA, Matrix Calculating neutral element proportional command MNZ, Matrix Calculating master Characteristic value command M EVA.

In some possible embodiments, first operational order is Matrix Calculating determinant command M DET,

The computing device controls the matrix operation unit to utilize first order pipelining-stage according to the selection of multiple selector In matrix comparison operation device to the matrix carry out inverse order of sequence computing obtain first as a result, first result is defeated Enter into second level pipelining-stage to carry out first result using the matrix multiplication operation device in it multiplication of all sequences Computing obtains second as a result, second result is inputted into third level pipelining-stage to utilize the addition of matrices arithmetic unit in it All sequences summation operation is carried out to second result and obtains the 3rd result；3rd result is inputted to the storage and is situated between Matter is stored.

In some possible embodiments, first operational order is Matrix Calculating order command M RANK,

The computing device controls the matrix operation unit to utilize first order pipelining-stage according to the selection of multiple selector In addition of matrices arithmetic unit Applying Elementary Row Operations carried out to the matrix obtain first as a result, inputting first result to the The statistics that matrix comparison operation device in two level pipelining-stage carries out non-zero line number obtains the second result；Second result is inputted It is stored to the storage medium, second result is rank of matrix.

In some possible embodiments, first operational order is Matrix Calculating mark command M TRA,

The computing device controls the matrix operation unit to utilize first order pipelining-stage according to the selection of multiple selector In matrix comparison operation device to the matrix select diagonal element be calculated first as a result, first result is defeated Enter to the addition of matrices arithmetic unit progress matrix diagonals element in the pipelining-stage of the second level and sum to obtain the second result；By described second As a result input to the storage medium and stored.

In some possible embodiments, first operational order is Matrix Calculating neutral element proportional command MNZ,

The computing device controls the matrix operation unit to utilize first order pipelining-stage according to the selection of multiple selector In matrix comparison operation device the matrix is carried out neutral element is selected to obtain first as a result, inputting first result to second Second is obtained as a result, by second result into row matrix neutral element number statistical in addition of matrices arithmetic unit in grade pipelining-stage The 3rd result is calculated to the matrix multiplication operation device in third level pipelining-stage into row matrix neutral element ratio in input；By described in 3rd result, which is inputted to the storage medium, to be stored.

In some possible embodiments, first operational order is Matrix Calculating dominant eigenvalue command M EVA,

The computing device controls the matrix operation unit to utilize first order pipelining-stage according to the selection of multiple selector In addition of matrices arithmetic unit be normalized to obtain first to the matrix as a result, inputting first result to the second level Addition of matrices arithmetic unit in pipelining-stage performs normalization and obtains second as a result, inputting second result to the third level again Dominant eigenvalue is carried out in matrix multiplication operation device in pipelining-stage is calculated the 3rd result；By the 3rd result input to The storage medium is stored.

In some possible embodiments, the instruction format of first operational order includes command code and at least one behaviour Make domain, command code is used to indicate the function of the operational order, and arithmetic element is by identifying that the command code can carry out different matrixes Computing, operation domain are used to indicate the data message of the operational order, wherein, data message can be immediate or register number, For example, when obtaining a matrix, matrix initial address and matrix can be obtained in corresponding register according to register number Length obtains the matrix of appropriate address storage further according to matrix initial address and matrix length in storage medium.Optionally, may be used Any one of following middle information or multinomial combination are obtained in corresponding registers：The line number of matrix needed for described instruction, row Number, data type, mark, storage address (first address) and dimension length, the dimension length refer to row matrix length and/ Or the length of rectangular array.

In some possible embodiments, the matrix, which reads instruction, to be included：The storage of matrix needed for described instruction The mark of matrix needed for location or described instruction.

In some possible embodiments, when matrix reading is designated as the mark of matrix needed for described instruction,

The computing device controls the matrix operation unit to read instruction according to the matrix and is sent out to the storage medium Reading order is sent to include：

It is single that the computing device controls the matrix operation unit to be used according to the mark from the register cell Position reading manner reads the corresponding storage address of the mark；

The computing device controls the matrix operation unit to be sent to the storage medium and reads the storage address Reading order simultaneously obtains the matrix using batch reading manner.

In some possible embodiments, the computing device further includes：Buffer unit, the method further include：

Pending operational order is cached in the buffer unit by the computing device.

In some possible embodiments, in the computing device matrix operation unit is controlled to obtain the first computing and referred to Before order, the method further includes：

The computing device determines first operational order and the second operational order before first operational order With the presence or absence of incidence relation, if first operational order and second operational order there are incidence relation, will described in First operational order is cached in the buffer unit, after second operational order is finished, from the buffer unit It extracts first operational order and is transmitted to the arithmetic element；

Described definite first operational order whether there is with the second operational order before the first operational order to be associated System includes：

The first storage address section of required matrix in first operational order is extracted according to first operational order, The second storage address section of required matrix in second operational order is extracted according to second operational order, if described First storage address section and the second storage address section have Chong Die region, it is determined that first operational order and Second operational order has incidence relation, if the first storage address section and the second storage address section are not Region with overlapping, it is determined that first operational order does not have incidence relation with second operational order.

Second aspect, provides a kind of computing device, and the computing device includes the method for performing above-mentioned first aspect Functional unit.

The third aspect, provides a kind of computer readable storage medium, and storage is used for the computer journey of electronic data interchange Sequence, wherein, the computer program causes computer to perform the method that first aspect provides.

Fourth aspect, provides a kind of computer program product, and the computer program product includes storing computer journey The non-transient computer readable storage medium of sequence, the computer program are operable to that computer is made to perform first aspect offer Method.

5th aspect, provides a kind of chip, and the chip includes the computing device that as above second aspect provides.

6th aspect, provides a kind of chip-packaging structure, and the chip-packaging structure includes as above the 5th aspect and provides Chip.

7th aspect, provides a kind of board, and the board includes the chip-packaging structure that as above the 6th aspect provides.

Eighth aspect, provides a kind of electronic equipment, and the electronic equipment includes the board that as above the 7th aspect provides.

In some embodiments, the electronic equipment includes data processing equipment, robot, computer, printer, scanning Instrument, tablet computer, intelligent terminal, mobile phone, automobile data recorder, navigator, sensor, camera, server, cloud server, Camera, video camera, projecting apparatus, wrist-watch, earphone, mobile storage, wearable device, the vehicles, household electrical appliance, and/or medical treatment Equipment.

In some embodiments, the vehicles include aircraft, steamer and/or vehicle；The household electrical appliance include electricity Depending on, air-conditioning, micro-wave oven, refrigerator, electric cooker, humidifier, washing machine, electric light, gas-cooker, kitchen ventilator；The Medical Devices include Nuclear Magnetic Resonance, B ultrasound instrument and/or electrocardiograph.

Implement the embodiment of the present application, have the advantages that：

As can be seen that by the embodiment of the present application, computing device is provided with register cell and storage medium, is respectively used to Store scalar data and matrix data, and unit reading manner and batch are read the application for two kinds of memory distributions Mode, the characteristics of by matrix data distribution match the data reading mode of its feature, can be good at, using bandwidth, avoiding Because influence of the bottleneck of bandwidth to matrix computations speed, in addition, for register cell, since its storage is scalar Data there is provided the reading manner of scalar data, improve the utilization rate of bandwidth, so the technical solution that the application provides can Well using bandwidth, avoid influence of the bandwidth to calculating speed, so it is fast with calculating speed, it is efficient the advantages of.

Description of the drawings

In order to illustrate more clearly of the technical solution in the embodiment of the present application, make required in being described below to embodiment Attached drawing is briefly described, it should be apparent that, the accompanying drawings in the following description is some embodiments of the present application, for ability For the those of ordinary skill of domain, without creative efforts, it can also be obtained according to these attached drawings other attached Figure.

Fig. 1 is a kind of structure diagram of computing device provided by the embodiments of the present application.

Fig. 2 is a kind of structure diagram of arithmetic element provided by the embodiments of the present application.

Fig. 3 is a kind of flow diagram of computational methods provided in an embodiment of the present invention.

Fig. 4 A and Fig. 4 B are the configuration diagrams of two kinds of pipelining-stages provided by the embodiments of the present application.

Fig. 5 is the structure diagram of pipelining-stage provided by the embodiments of the present application.

Fig. 6 A and 6B are the form schematic diagrams of two kinds of instruction set provided by the embodiments of the present application.

Fig. 7 is the structure diagram of another computing device provided by the embodiments of the present application.

Fig. 8 is the flow chart that computing device provided by the embodiments of the present application performs the instruction of Matrix Calculating mark.

Specific embodiment

Below in conjunction with the attached drawing in the embodiment of the present application, the technical solution in the embodiment of the present application is carried out clear, complete Site preparation describes, it is clear that described embodiment is some embodiments of the present application, instead of all the embodiments.Based on this Shen Please in embodiment, the every other implementation that those of ordinary skill in the art are obtained without creative efforts Example, shall fall in the protection scope of this application.

Term " first ", " second ", " the 3rd " in the description and claims of this application and the attached drawing and " Four " etc. be for distinguishing different objects rather than for describing particular order.In addition, term " comprising " and " having " and it Any deformation, it is intended that cover non-exclusive include.Such as it contains the process of series of steps or unit, method, be The step of system, product or equipment are not limited to list or unit, but optionally further include the step of not listing or list Member is optionally further included for the intrinsic other steps of these processes, method, product or equipment or unit.

Referenced herein " embodiment " is it is meant that a particular feature, structure, or characteristic described can wrap in conjunction with the embodiments It is contained at least one embodiment of the application.Each position in the description occur the phrase might not each mean it is identical Embodiment, nor the independent or alternative embodiment with other embodiments mutual exclusion.Those skilled in the art explicitly and Implicitly understand, embodiment described herein can be combined with other embodiments.

It should be noted that this application involves matrix be specifically as follows m*n matrixes, wherein, m and N are more than or equal to 1 Integer when m or n is 1, is represented by 1*n matrixes or m*1 matrixes, is referred to as vector；When m and n simultaneously for 1 when, can be with It is considered as the Special matrix of 1*1.Following matrixes all can be in above-mentioned three types matrix any one, do not repeating below.

The embodiment of the present application provides a kind of computational methods, which can be applied in computing device.It is this such as Fig. 1 A kind of structure diagram of possible computing device shown in inventive embodiments.Computing device as shown in Figure 1 includes：

Storage medium 201, for storage matrix.The preferred storage medium can be scratchpad, Neng Gouzhi Hold the matrix data of different length；Necessary calculating data are temporarily stored in scratchpad (Scratchpad by the application Memory), this arithmetic unit is made more flexibly can effectively to support the data of different length during matrix operation is carried out. Above-mentioned storage medium can also be the outer database of piece, database or other media that can be stored etc..

Register cell 202, for storing scalar data, wherein, which includes but not limited to：Matrix data (the application is also referred to as matrix) storage address and matrix in storage medium 201 and scalar during scalar operation.In a kind of reality It applies in mode, register cell can be scalar register heap, provide scalar register needed for calculating process, scalar deposit Device not only stores matrix address, and also storage has scalar data.It is to be understood that matrix address (the i.e. storage address of matrix, as first Location) also it is scalar.When being related to the computing of matrix and scalar, arithmetic element not only will with obtaining matrix from register cell Location will also obtain corresponding scalar from register cell, such as the type of the line number of matrix, columns, matrix data (can also claim For data type), matrix dimension length (the concretely length of row matrix, length of rectangular array etc.).

Arithmetic element 203 (the application is also referred to as matrix operation unit 203), for obtaining and performing the first operational order. As shown in Fig. 2, the arithmetic element includes multiple arithmetic units, which includes but not limited to：Addition of matrices arithmetic unit 2031, square Battle array multiplicative operator 2032, size comparison operation device 2033 (or matrix comparison operation device), 2034 and of nonlinear operator Matrix scalar multiplication arithmetic unit 2035.

This method is as shown in figure 3, include the following steps：

Step S301, arithmetic element 203 obtains the first operational order, and first operational order is used to implement matrix and mark The computing of amount, first operational order include：It performs the matrix needed for the instruction and reads instruction.

In step S301, matrix needed for the above-mentioned execution instruction read instruction be specifically as follows it is a variety of, for example, at this Apply in an optional technical solution, the matrix needed for the above-mentioned execution instruction reads the storage that instruction can be required matrix Address.For another example, in the application in another optional technical solution, matrix needed for the above-mentioned execution instruction reads instruction can be with For the mark of required matrix, the form of expression of the mark can be a variety of, for example, the title of matrix, for another example, the identification of matrix Number, the matrix is in the register number or storage address of register cell for another example.

Illustrate the square performed needed for the instruction that above-mentioned first operational order includes below by the example of a reality Battle array reads instruction, it is assumed here that and the matrix operation formula is f (x)=A+B, wherein, A, B are matrix.So in the first computing In instruction in addition to carrying the matrix operation formula, the storage address of matrix needed for the matrix operation formula can also be carried, is had Body, such as the storage address of A is 0000-0FFF, the storage address of B is 1000-1FFF.For another example, it can carry A's and B Mark, for example, A be identified as 0101, B be identified as 1010.

Step S302, arithmetic element 203 reads instruction according to the matrix and sends reading order to the storage medium 201.

The implementation method of above-mentioned steps S302 is specifically as follows：

Such as matrix reads the storage address that instruction can be required matrix, and arithmetic element 203 is sent out to the storage medium 201 It gives the reading order of the reading storage address and corresponding matrix is obtained using batch reading manner.

For another example the matrix reads instruction when can be the mark of required matrix, and arithmetic element 203 is according to the mark from deposit The corresponding storage address of the mark is read using unit reading manner at device unit, then arithmetic element 203 is to the storage medium 201 send the reading order of the reading storage address and obtain corresponding matrix using batch reading manner.

Above-mentioned single reading manner is specifically as follows, and reads every time as the data of unit, i.e. 1bit data.It sets at this time The reason for unit reading manner i.e. 1 reading manner, is, for scalar data, the capacity occupied is very small, if adopted With batch data reading manner, then the data volume of reading is easily more than the capacity of required data, can so cause bandwidth Waste, so using unit reading manner here for the data of scalar to read to reduce the waste of bandwidth.

Step S303, arithmetic element 203 reads the corresponding matrix of the instruction using batch reading manner, which is performed First operational order.

Batch reading manner is specifically as follows in above-mentioned steps S303, and reading every time is the data of multidigit, such as every time The data bits of reading is 16bit, 32bit or 64bit, i.e., no matter the data volume needed for it is how many, and that reads every time is equal For the data of fixed long number, the data mode that this batch is read is very suitable for the reading of big data, for matrix, due to Its occupied capacity is big, if using single reading manner, the speed read can be very slow, so being read here using batch Mode is taken to obtain the data of multidigit so as to quickly read matrix data, is avoided because reading the excessively slow influence matrix meter of matrix data The problem of calculating speed.

The computing device for the technical solution that the application provides is provided with register cell and storage medium, stores mark respectively Measure data and matrix data, and the application for two kinds of memory distributions unit reading manner and batch reading manner, The distribution of the characteristics of by matrix data matches the data reading mode of its feature, can be good at using bandwidth, avoid because Influence of the bottleneck of bandwidth to matrix computations speed, in addition, for register cell, since its storage is scalar number According to there is provided the reading manner of scalar data, the utilization rate of bandwidth being improved, so the technical solution that the application provides can be very Good utilization bandwidth, avoids influence of the bandwidth to calculating speed, so it is fast with calculating speed, it is efficient the advantages of.

Optionally, it is above-mentioned that matrix execution first operational order is specifically as follows：

The calculation of multistage pipelining-stage can be used in arithmetic element 203, and the meter of i grades of pipelining-stages can be used in the embodiment of the present application Calculation mode performs first operational order to the matrix.Specifically include following several embodiments.

In the first embodiment, the computing device can also design at least one multiple selector MMUX to realize multistage The calculating of pipelining-stage.The specific realization framework that pipelining-stage more than two kinds is shown respectively such as Fig. 4 A and 4B.Such as Fig. 4 A, the computing device Can be that each pipelining-stage designs a multiple selector MMUX；Fig. 4 B are shown as multiple pipelining-stages and set a multiple selector MMUX.Multiple selector it is corresponding needed for control/selection pipelining-stage connection, for select the arithmetic unit in the pipelining-stage with Realize relevant calculating.It is to be understood that arithmetic unit of the multiple selector selected in pipelining-stage is according to the first operational order What corresponding calculating network topology determined, specifically it will be described in detail later.

In the specific implementation, arithmetic element 203 can be according to the selection of multiple selector, using selected by first (grade) pipelining-stage First choice arithmetic unit to the matrix be calculated first and utilized as a result, the first result then is inputted the second pipelining-stage The execution of second pipelining-stage selected second Selecting operation device be calculated second as a result, and so on, (i-1)-th result is defeated Enter into the i-th pipelining-stage and i-th of result is calculated using its selected i-th Selecting operation device execution.Here i-th of result As export result (being specially output matrix).Further, arithmetic element 203 can store the output result to storage medium 201。

What the quantity i of the multistage pipelining-stage was specifically determined according to the calculating topological structure of first operational order, i For positive integer.In general, i=3.May be provided with arithmetic unit correspondingly in each pipelining-stage, the arithmetic unit include but not limited to Any one of lower or multinomial combination：Addition of matrices arithmetic unit, matrix scalar multiplication arithmetic unit, nonlinear operator, matrix Comparison operation device and other matrix operation devices.It is the quantity of arithmetic unit and arithmetic unit included in each pipelining-stage Can there are user side or the self-defined setting in computing device side, not limit.

With i=3, exemplified by three-level flowing water, arithmetic element can select the first pipelining-stage respectively extremely by three multiple selector The respective required arithmetic unit (alternatively referred to as arithmetic unit) used in 3rd pipelining-stage；Meanwhile the first flowing water is performed to the matrix Grade is calculated first as a result, the first result is input to calculating for the second pipelining-stage the second pipelining-stage of execution by (optional) To second as a result, (optional) by the second result be input to the 3rd pipelining-stage perform the 3rd pipelining-stage be calculated the 3rd as a result, (optional) stores the 3rd result to storage medium 201.As Fig. 5 shows a kind of operating process schematic diagram of pipelining-stage.

Above-mentioned first pipelining-stage includes but not limited to：Matrix multiplication operation device etc..

Above-mentioned second pipelining-stage includes but not limited to：Addition of matrices arithmetic unit, size comparison operation device etc..

Above-mentioned 3rd pipelining-stage includes but not limited to：Nonlinear operator, matrix scalar multiplication arithmetic unit etc..

By three pipelining-stage computings of matrix point primarily to improving the speed of computing, for the calculating of matrix, example Such as using general processor when calculating, the step of computing, is specifically as follows, and processor carries out matrix to be calculated first As a result, then by the storage of the first result in memory, processor reads the execution of the first result from memory and the is calculated for the second time Two as a result, then by the storage of the second result in memory, processor is calculated for the third time from interior performed from the second result of reading 3rd as a result, then by the storage of the 3rd result in memory.It can be seen that from the step of above-mentioned calculating and carried out in general processor During matrix computations, there is no shunt water grade to be calculated, then every time calculate after be required to the data that will be had been calculated into Row preservation needs to read again when next time calculates, so this scheme needs repetition storage to read multiple data, for the application's For technical solution, the first result that the first pipelining-stage calculates is directly entered the grading row calculating of the second flowing water, the second pipelining-stage meter The second result calculated enters directly into the 3rd pipelining-stage and is calculated, the first result that the first pipelining-stage and the second pipelining-stage calculate With the second result without storage, which reduce the occupied space of memory first, secondly, which obviate result multiple storage and It reads, improves the utilization rate of bandwidth, further improve computational efficiency.

In another embodiment of the application, each flowing water component can be freely combined or take level-one pipelining-stage.It such as will Second pipelining-stage and the 3rd pipelining-stage, which merge, either all merges first and second and the 3rd assembly line or each Pipelining-stage is responsible for different computings can be with permutation and combination.For example, first order flowing water is responsible for comparison operation, and partial product computing, Two level flowing water is responsible for the combinations such as nonlinear operation and matrix scalar multiplication.It is that the i pipelining-stage designed in the application is supported to appoint Multiple pipelining-stages of anticipating are in parallel, connect and merge, and to form different permutation and combination, the application does not limit.

It should be noted that being also provided with sky option in each multiple selector, i.e., it is connected with the multiple selector Pipelining-stage and follow-up pipelining-stage are not involved in computing.It that is to say, sky option described herein is used to indicate to be selected with the multichannel The kth grade pipelining-stage and subsequent kth+1 to i-stage pipelining-stage for selecting device connection not perform calculating operation, wherein, k is Positive integer less than or equal to i.

With i=3, exemplified by three-level flowing water, if the multiple selector selected as sky option of the 3rd pipelining-stage of connection, the 3rd Pipelining-stage is not involved in computing, and the current pipelining-stage for performing arithmetic operation is less than three；For example, certain operational order is instructed comprising two-stage, Then the corresponding multiple selector of the 3rd pipelining-stage chooses sky option.

Using above-mentioned computing device (be designed with multiple selector select to need in every grade of pipelining-stage the arithmetic unit used/ Arithmetic unit), it has the advantages that：In addition to bandwidth is improved, while have that logic is clear and definite, the output result of no arithmetic unit From rear pipelining-stage redirecting to preceding pipelining-stage, the characteristics of input interface and output interface are single, good operability.

In second of embodiment, the computing device can be that the fixation pipelining-stage of each operational order design correspondingly is real Existing framework.A kind of realization framework of the corresponding three-level pipelining-stage of operational order as shown in figure 5 above.It is to refer to for certain computing For order, arithmetic unit included in each pipelining-stage is that the fixed setting in advance of user side or the computing device side is good, this The alternatively referred to as fixed arithmetic unit of application.In addition, fixation arithmetic unit in each pipelining-stage can it is identical also can be different, typically not Identical.For example, the first pipelining-stage be addition of matrices arithmetic unit, second level flowing water be matrix multiplication operation device, third level flowing water For nonlinear operator；For another example, the first pipelining-stage is addition of matrices arithmetic unit, and second level flowing water is addition of matrices arithmetic unit, the Three-level flowing water is matrix multiplication operation device etc..I.e. different operational orders is related to different flowing water stage arrangement (realization framework). It is to be understood that according to the realization demand that nonidentity operation instructs, the quantity i of the pipelining-stage being related to can be different, can correspond to increase or Less, the application does not limit.

In the specific implementation, arithmetic element 203 is successively using the fixation arithmetic unit in first (grade) pipelining-stage to the matrix First be calculated as a result, the first result is inputted the second pipelining-stage to be calculated using the fixation arithmetic unit execution in it To second as a result, and so on, until (i-1)-th result is inputted to the i-th pipelining-stage to hold using the fixation arithmetic unit in it I-th of result is calculated in row.Here i-th of result is to export result (being specially output matrix).Further, computing list Member 203 can store the output result to storage medium 201.Quantity i and each pipelining-stage on the multistage pipelining-stage The fixation arithmetic unit of middle design can be found in the related elaboration in previous embodiment, and which is not described herein again.

With i=3, exemplified by three-level flowing water.Referring to earlier figures 5, a kind of the fixed real of the corresponding pipelining-stage of operational order is shown Existing framework.Specifically, the multiplication that arithmetic element performs the matrix the first pipelining-stage is calculated first as a result, by the first result The additional calculation for being input to the second pipelining-stage the second pipelining-stage of execution obtains second as a result, the second result is input to the 3rd flowing water The NONLINEAR CALCULATION that grade performs the 3rd pipelining-stage obtains the 3rd as a result, storing the 3rd result (exporting result) to storage medium 201。

It should be noted that the arithmetic unit in above-mentioned computing device in each pipelining-stage be in advance it is self-defined set, Once it is determined that do not allow to change；That is i grades of pipelining-stage may be designed as the permutation and combination of arbitrary arithmetic unit, i grades of pipelining-stages once driving not It changes again, different operational orders can design different i grade flowing water stage arrangements.Wherein, which can be according to specific instruction Demand, adaptability increases/quantity of less pipelining-stage.Finally, the flowing water stage arrangement designed for different instruction can be combined Together, the computing device is formed.

Using above-mentioned computing device (i.e. arithmetic unit/arithmetic unit design in every grade of pipelining-stage is fixed), have with following Beneficial effect：In addition to bandwidth is improved, have specificity high, without extra logic judgment, further improve operational performance, arithmetic speed The characteristics of fast.

Optionally, above-mentioned computing device can also include：Buffer unit 204, for caching the first operational order.Instruction exists It in implementation procedure, while is also buffered in instruction cache unit, after an instruction has performed, if the instruction is simultaneously It is not to be submitted an instruction earliest in instruction in instruction cache unit, which will carry on the back and submits, once it submits, this instruction The operation of progress will be unable to cancel to the change of unit state.In one embodiment, instruction cache unit can be reset Sequence caches.

Optionally, the above method can also include before step S301：

Determine that first operational order whether there is incidence relation with the second operational order before the first operational order, such as First operational order there are incidence relation, is then performed with the second operational order before the first operational order in the second operational order After finishing, first operational order is extracted from buffer unit and is transferred to arithmetic element 203.If the first operational order is with being somebody's turn to do Instruction onrelevant relation before first operational order, then be directly transferred to arithmetic element by the first operational order.

Above-mentioned definite first operational order whether there is with the second operational order before the first operational order to be associated The concrete methods of realizing of system can be：

The first storage address section of required matrix in first operational order, foundation are extracted according to first operational order Second operational order extracts the second storage address section of required matrix in second operational order, such as the first stored address area Between with the second storage address section there is Chong Die region, it is determined that the first operational order and the second operational order are with associating System.Such as the first storage address section and the non-overlapping region in the second storage address section, it is determined that the first operational order and second Operational order does not have incidence relation.

There is overlapping region the first operational order of explanation occur in trivial of this storage and have accessed phase with the second operational order With matrix, for matrix, as judging be since the space of its storage is bigger, such as using identical storage region The no condition for incidence relation, in fact it could happen that situation be, the second operational order access storage region contain the first computing The storage region accessed is instructed, is deposited for example, the second operational order accesses A matrix storage areas, B matrix storage areas and C matrixes Storage area domain, if A, B storage region are adjacent or A, C storage region are adjacent, the second operational order access storage region be, A, B storage regions and C storage regions or A, C storage region and B storage regions.In this case, if the first operational order Access is the storage region of A matrixes and D matrix, then the storage region for the matrix that the first operational order accesses can not be with second The storage region of the matrix of operational order model essay is identical, if using identical Rule of judgment, it is determined that the first operational order with Second operational order does not associate, but it was verified that the first operational order and the second operational order belong to incidence relation at this time, institute With the application by whether have overlapping region to determine whether for incidence relation condition, the erroneous judgement of the above situation can be avoided.

Illustrate which kind of situation belongs to incidence relation below with the example of a reality, which kind of situation belongs to dereferenced pass System.It is assumed here that the matrix needed for the first operational order is A matrixes and D matrix, the storage region of wherein A matrixes is【0001, 0FFF】, the storage region of D matrix is【A000, AFFF】, it is A matrixes, B matrixes and C for the matrix needed for the second operational order Matrix, corresponding storage region are【0001,0FFF】、【1000,1FFF】、【B000, BFFF】, refer to for the first computing For order, corresponding storage region is：【0001,0FFF】、【A000, AFFF】, for the second operational order, correspond to Storage region be：【0001,1FFF】、【B000, BFFF】, so the storage region of the second operational order and the first operational order Storage region have overlapping region【0001,0FFF】, so the first operational order has incidence relation with the second operational order.

It is assumed here that the matrix needed for the first operational order is E matrixes and D matrix, the storage region of wherein A matrixes is 【C000, CFFF】, the storage region of D matrix is【A000, AFFF】, it is A matrixes for the matrix needed for the second operational order, B Matrix and C matrixes, corresponding storage region are【0001,0FFF】、【1000,1FFF】、【B000, BFFF】, for For one operational order, corresponding storage region is：【C000, CFFF】、【A000, AFFF】, come for the second operational order It says, corresponding storage region is：【0001,1FFF】、【B000, BFFF】, so the storage region of the second operational order and the The storage region of one operational order does not have overlapping region, so the first operational order and the second operational order onrelevant relation.

In the application, if Fig. 6 is a kind of instruction (can be the first operational order or operational order) that the application provides Instruction set form schematic diagram, as shown in Figure 6A, operational order include a command code and an at least operation domain, wherein, operate Code is used to indicate the function of the operational order, and arithmetic element is operated by identifying that the command code can carry out different matrix operations Domain is used to indicate the data message of the operational order, wherein, data message can be immediate or register number, for example, to obtain When taking a matrix, matrix initial address and matrix length, then root can be obtained in corresponding register according to register number The matrix of appropriate address storage is obtained in storage medium according to matrix initial address and matrix length.

I.e. the first operational order can include：Operation domain and at least one command code, by taking matrix operation command as an example, such as Shown in table 1, wherein, register 0, register 1, register file 2, register 3, register 4 can be operation domain.Wherein, each Register 0, register 1, register 2, register 3, register 4 be used for marker register number, can be one or Multiple registers.It is to be understood that the quantity of register does not limit in command code, each register is used to storage computing and refers to The related data information of order.

If Fig. 6 B are the fingers for another instruction (can be the first operational order, alternatively referred to as operational order) that the application provides Make collection form schematic diagram, as shown in Figure 6B, instruction include at least two command codes and at least an operation domain, wherein, it is described extremely Few two command codes include the first command code and the second command code (diagram is respectively command code 1 and command code 2).The command code 1 type for being used to indicate instruction (i.e. certain major class instructs), such as can concretely I/O instruction, logical order or operational order etc. Deng, the command code 2 is used to indicate the function (explanation of the specific instruction i.e. under major class instruction) of instruction, such as in operational order Matrix operation command (such as Matrix Multiplication vector instruction MMUL, matrix inversion command M INV), vector operation instruction is (as vector is asked Lead instruction VDIER etc.) etc., the application does not limit.

It is to be understood that the form of instruction can be user side or the self-defined setting in computing device side.The behaviour of instruction Regular length, such as 8bit, 16bit etc. are may be designed as code.Instruction format as shown in Fig. 6 A has the advantage that feature： Command code occupancy digit is few, decoding system design is simple.Instruction format as shown in Fig. 6 B has the advantage that feature：It is variable Long, decoding average efficiency higher, in the case that certain major class instructs lower specific instruction less and calls frequency height, design its second The length of command code (i.e. command code 2) is short and small, can improve decoding efficiency；Moreover it is possible to enhance the readable and expansible of instruction Property optimizes the coding structure of instruction.

In the embodiment of the present application, instruction set includes the operational order of difference in functionality, concretely：

Matrix Calculating order instruct (MRANK), according to the instruction, device from memory (preferred scratchpad or Scalar register heap) specified address take out setting length matrix data, the fortune to Matrix Calculating order is carried out in arithmetic element It calculates, and results back into.Preferably, and by result of calculation memory (preferred scratchpad or scalar are written back to Register file) specified address；What deserves to be explained is numerical value can be as matrix (an only row element, the row of special shape The matrix of element) it is stored in memory (preferred scratchpad or scalar register heap).

Matrix Calculating mark instructs (MTRA), and according to the instruction, device is from memory (preferred scratchpad or mark Measure register file) specified address take out setting length matrix data, the computing to Matrix Calculating mark is carried out in arithmetic element, And it results back into.Preferably, and by result of calculation being written back to memory, (preferred scratchpad or scalar are deposited Device heap) specified address；What deserves to be explained is numerical value can be as matrix (only a row element, the column element of special shape Matrix) be stored in memory (preferred scratchpad or scalar register heap).

Matrix Calculating determinant instruct (MDET), according to the instruction, device from memory (preferred scratchpad or Person's scalar register heap) specified address take out setting length matrix data, carried out in arithmetic element to Matrix Calculating ranks The computing of formula, and result back into.Preferably, and by result of calculation be written back to memory (preferred scratchpad or Person's scalar register heap) specified address；What deserves to be explained is numerical value can be as matrix (only a line member of special shape Element, the matrix of a column element) it is stored in memory (preferred scratchpad or scalar register heap).

Matrix Calculating neutral element proportional command (MNZ), according to the instruction, from memory, (preferred scratchpad stores device Device or scalar register heap) specified address take out setting length matrix data, carried out in arithmetic element to matrix unite The computing of neutral element number is counted, and is resulted back into.Preferably, and by result of calculation it is (preferred temporary at a high speed to be written back to memory Deposit memory or scalar register heap) specified address；What deserves to be explained is numerical value can be as the matrix of special shape (only a row element, the matrix of a column element) is stored in memory (preferred scratchpad or scalar register Heap) in.

Matrix Calculating dominant eigenvalue instructs (MEVA), and according to the instruction, device is from memory (preferred scratchpad Or scalar register heap) specified address take out setting length matrix data, carried out in arithmetic element to matrix count The computing of neutral element number, and result back into.Preferably, and by result of calculation it is written back to memory (preferred scratchpad Memory or scalar register heap) specified address；What deserves to be explained is numerical value can as special shape matrix (only Have a row element, the matrix of a column element) it is stored in memory (preferred scratchpad or scalar register heap) In.

It is to be understood that operation/operational order that the application proposes is mainly used for solving the behaviour of the scalar of performance Matrix Properties Make.Therefore, the arithmetic unit designed in every grade of pipelining-stage is including but not limited to any one of following or multinomial combination：Matrix adds Method arithmetic unit, matrix multiplication operation device, matrix scalar multiplication arithmetic unit, nonlinear operator, matrix comparison operation device.

Be exemplified below this application involves operational order (i.e. the first operational order) calculating.

By taking first operational order is Matrix Calculating determinant command M DET as an example, given Matrix Calculating determinant is transported It calculates.In the specific implementation, giving a square formation A, the determinant of the matrix A is calculated according to equation below.

Wherein, j₁,j₂,...j_nFor the arbitrary arrangement of 1,2.., n.τ(j₁,j₂,...j_n) it is sequence j₁,j₂,...j_nIt is inverse Ordinal number.For line n jth in matrix A_nThe element of row.

Correspondingly, the instruction format of Matrix Calculating determinant instruction is specially：

With reference in previous embodiment, arithmetic element can obtain Matrix Calculating determinant command M DET, and after being decoded to it, utilize The multiple selector of first pipelining-stage choose matrix comparison operation device matrix is carried out inverse order of sequence be calculated first as a result, Then the multiplication for inputting progress all sequences in the matrix multiplication operation device selected by the multiple selector of the second pipelining-stage obtains To second as a result, recently enter in the addition of matrices arithmetic unit selected by the multiple selector of the 3rd pipelining-stage to all sequences into Row read group total obtains the 3rd result (exporting result).Optionally, the 3rd result is stored into storage medium.

By first operational order for exemplified by Matrix Calculating order command M RANK, calculating gives rank of matrix.Specific implementation When, a matrix A is given, carries out asking order computing using the elementary variation of row.

Correspondingly, the instruction format of Matrix Calculating order command M RANK is specially：

With reference in previous embodiment, arithmetic element can obtain Matrix Calculating order command M RANK, and after being decoded to it, utilize The multiple selector of one pipelining-stage chooses addition of matrices arithmetic unit and obtains first as a result, then defeated to matrix progress Applying Elementary Row Operations The statistics for entering to carry out non-zero line number in the matrix comparison operation device selected by the multiple selector of the second pipelining-stage is calculated the Two results (i.e. output is as a result, rank of matrix).Optionally, which is stored into storage medium.

By taking first operational order is Matrix Calculating mark command M TRA as an example, calculate to the mark of set matrix.During specific implementation, A matrix A is given, according to the mark of equation below solution matrix.

Wherein, A_iiRefer to the element that the i-th row i-th arranges in matrix A, i is positive integer.

Correspondingly, the instruction format of Matrix Calculating mark command M TRA is specially：

With reference in previous embodiment, arithmetic element can obtain Matrix Calculating mark command M TRA, and after being decoded to it, utilize first The multiple selector of pipelining-stage chooses matrix comparison operation device and matrix is carried out diagonal element is selected to be calculated first as a result, then It inputs in the second pipelining-stage as carrying out matrix diagonals element read group total in the addition of matrices arithmetic unit selected by multiple selector Obtain the second result (exporting result).Optionally, which is stored into storage medium.

By taking first operational order is Matrix Calculating neutral element proportional command MNZ as an example, calculate to the neutral element of set matrix Ratio.During specific implementation, give a matrix A, according to neutral element in equation below statistical matrix A number and calculate zero The ratio of element.

Wherein, n_ijFor the element that the i-th row jth in matrix A arranges, i and j are positive integer.

Correspondingly, the instruction format of Matrix Calculating neutral element proportional command MNZ is specially：

With reference in previous embodiment, arithmetic element can obtain Matrix Calculating neutral element proportional command MNZ, and after being decoded to it, Neutral element is carried out using the matrix comparison operation device selected by multiple selector in the first pipelining-stage to matrix to choose to obtain first As a result, it then inputs in the second pipelining-stage through carrying out neutral element number system in the addition of matrices arithmetic unit selected by multiple selector Meter obtain second as a result, input again in the 3rd pipelining-stage through in the matrix multiplication operation device selected by multiple selector into row matrix The 3rd result is calculated in the ratio of neutral element (i.e. output is as a result, the ratio of matrix neutral element).Optionally, by the 3rd knot Fruit is stored into storage medium.

By taking first operational order is Matrix Calculating dominant eigenvalue command M EVA as an example, calculate to the main feature of set matrix Value.During specific implementation, a matrix A is given, the dominant eigenvalue of the matrix is calculated according to equation below.

Seek dominant eigenvalue：

Wherein, a_ijThe element arranged for the i-th row jth in matrix A；(CW) i is i-th of component of matrix product CW.

Correspondingly, the instruction format of Matrix Calculating dominant eigenvalue command M EVA is specially：

With reference in previous embodiment, arithmetic element can obtain Matrix Calculating dominant eigenvalue command M EVA, and after being decoded to it, profit Matrix is normalized with the addition of matrices arithmetic unit selected by the multiple selector of the first pipelining-stage, the first knot is calculated Then fruit is inputted in the second pipelining-stage as being normalized to obtain again in the addition of matrices arithmetic unit selected by multiple selector Then second as a result, input in the 3rd pipelining-stage as carrying out dominant eigenvalue in the matrix multiplication operation device selected by multiple selector The 3rd result (exporting result) is calculated.Optionally, the 3rd result is stored into storage medium.

It should be noted that the acquisition and decoding of above-mentioned various operational orders will be described in detail later.Ying Li Solution, the calculating of each operational order (such as Matrix Calculating order command M RANK) is realized using the structure of above-mentioned computing device, can be obtained Obtain following advantageous effect：The scalable of matrix, it is possible to reduce instruction number, the use of reduction instruction；Difference can be handled to deposit The matrix of form (row-major order and row main sequence) is stored up, avoids the expense converted to matrix；Support is stored according to certain intervals Matrix format, avoid the executive overhead converted to matrix storage format and the space hold of storage intermediate result.

Setting length in aforesaid operations instruction (i.e. matrix operation command/first operational order) can voluntarily be set by user Fixed, in an optional embodiment, which can be arranged to a value by user, certainly in practical applications, The setting length can also be arranged to multiple values by user.The application specific embodiment does not limit the specific of the setting length Value and number.Purpose, technical scheme and advantage to make the application are more clearly understood, below in conjunction with specific embodiment, and Referring to the drawings, the application is further described.

Refering to Fig. 7, Fig. 7 is another computing device 50 that the application specific embodiment provides.Shown in Fig. 7, dress is calculated Putting 50 includes：Storage medium 501, register cell 502 (preferably scalar data storage unit, scalar register unit), Arithmetic element 503 (can also claim matrix operation unit 503) and control unit 504；

Storage medium 501, for storage matrix；

Scalar data storage unit 502, for storing scalar data, the scalar data includes at least：The matrix exists Storage address in the storage medium；

Control unit 504, for the arithmetic element to be controlled to obtain the first operational order, first operational order is used for Realize the computing between matrix and scalar, the matrix that first operational order includes performing needed for described instruction reads instruction；

Arithmetic element 503 sends reading order for reading instruction according to the matrix to the storage medium；Foundation is adopted The matrix is read with batch reading manner and reads the corresponding matrix of instruction, and first operational order is performed to the matrix.

Optionally, above-mentioned matrix reads instruction and includes：Storage address or the described instruction institute of matrix needed for described instruction Need the mark of matrix.

Optionally as needed for matrix reading is designated as described instruction during the mark of matrix,

Control unit 504, for the arithmetic element to be controlled to go out according to the mark from the register cell using single Position reading manner reads the corresponding storage address of the mark, and the arithmetic element is controlled to be sent to the storage medium and reads institute It states the reading order of storage address and the matrix is obtained using batch reading manner.

Optionally, specifically for the calculation using multistage pipelining-stage, institute is performed to the matrix for arithmetic element 503 State the first operational order.

Optionally, each pipelining-stage in the multistage pipelining-stage includes at least one arithmetic unit,

Arithmetic element 503 specifically for the selection according to multiple selector, utilizes the first choice in first order pipelining-stage Arithmetic unit to the matrix be calculated first as a result, first result to be input to second in the pipelining-stage of the second level The execution of Selecting operation device be calculated second as a result, and so on, until inputting (i-1)-th result into i-stage pipelining-stage The i-th Selecting operation device execution i-th of result is calculated；I-th of result is inputted to the storage medium and is deposited Storage；Wherein, the quantity i of the multistage pipelining-stage is determined according to the calculating topological structure of first operational order, and i is Positive integer.

Optionally, each pipelining-stage in the multistage pipelining-stage is each configured with corresponding multiple selector, described more Selector setting in road is free option, the sky option be used to indicate the kth grade pipelining-stage that is connected with the multiple selector and Subsequent kth+1 to i-stage pipelining-stage not performs calculating operation, wherein, k is the positive integer less than or equal to i.

Optionally, the quantity of the arithmetic unit included by each pipelining-stage in the multistage pipelining-stage and the arithmetic unit It is by user side or the self-defined setting in computing device side.

Optionally, each pipelining-stage in the multistage pipelining-stage includes pre-set fixed arithmetic unit, described every Fixation arithmetic unit in a pipelining-stage differs,

I-th of result is inputted to the storage medium and is stored；

Optionally, first operational order is Matrix Calculating determinant command M DET,

Optionally, first operational order is Matrix Calculating order command M RANK,

Optionally, first operational order is Matrix Calculating mark command M TRA,

Optionally, first operational order is Matrix Calculating neutral element proportional command MNZ,

Optionally, first operational order is Matrix Calculating dominant eigenvalue command M EVA,

Optionally, the computing device further includes：

Buffer unit 505, for caching pending operational order；

Described control unit 504, for pending operational order to be cached in the buffer unit 504.

Optionally, control unit 504, for determining the before first operational order and first operational order Two operational orders whether there is incidence relation, such as first operational order and second operational order there are incidence relation, Then by first operational order caching in the buffer unit, after second operational order is finished, from described Buffer unit extracts first operational order and is transmitted to the arithmetic element；

The first storage address section of required matrix in first operational order is extracted according to first operational order, The second storage address section of required matrix in second operational order is extracted according to second operational order, such as described the One storage address section has Chong Die region with the second storage address section, it is determined that first operational order and institute The second operational order is stated with incidence relation, such as the first storage address section does not have with the second storage address section The region of overlapping, it is determined that first operational order does not have incidence relation with second operational order.

Optionally, above-mentioned control unit 503 can be used for obtaining operational order from instruction cache unit, and to the computing After instruction is handled, the arithmetic element is supplied to.Wherein, control unit 503 can be divided into three modules, be respectively： Fetching module 5031, decoding module 5032 and instruction queue module 5033,

Fetching module 5031, for obtaining operational order from instruction cache unit；

Decoding module 5032, for the operational order to acquisition into row decoding；

Instruction queue 5033, for after decoding operational order carry out sequential storage, it is contemplated that different instruction comprising Register on there may be dependence, for cache decode after instruction, emit after dependence is satisfied and refer to Order.

Refering to Fig. 8, Fig. 8 is the flow chart that computing device provided by the embodiments of the present application performs operational order, such as Fig. 8 institutes Show, the hardware configuration of the computing device is refering to structure shown in Fig. 7, and storage medium as shown in Figure 7 is with scratchpad Exemplified by, performing the process of Matrix Calculating mark command M TRA includes：

Step S601, computing device control fetching module takes out the instruction of Matrix Calculating mark, and Matrix Calculating mark instruction is sent to Decoding module.

Step S602, decoding module are sent to instruction queue to the Matrix Calculating mark Instruction decoding, and by Matrix Calculating mark instruction.

Step S603, in instruction queue, Matrix Calculating mark instruction needs to obtain three in instruction from scalar register heap The data in scalar register corresponding to a operation domain, the data include input matrix address, output vector address and output Vector length.

Step S604, control unit determine whether are Matrix Calculating mark instruction and the operational order before the instruction of Matrix Calculating mark There are incidence relations, and such as there are incidence relation, the instruction of Matrix Calculating mark is deposited into buffer unit, will such as there is no associate management Matrix Calculating mark instruction is transmitted to arithmetic element.

Step S605, data in scalar register of the arithmetic element according to corresponding to three operation domains are from scratch pad memory It is middle to take out the matrix data needed, it then completes to ask mark computing in arithmetic element.

Step S606, after the completion of arithmetic element computing, write the result into memory (preferred scratchpad or Scalar register heap) specified address, reorder caching in the Matrix Calculating mark instruction is submitted.

Optionally, in above-mentioned steps S605 when mark computing is asked in arithmetic element execution, matrix can be used in the computing device Comparison operation device selects matrix diagonals element, reuses addition of matrices arithmetic unit and carries out matrix diagonals element summation acquisition matrix Mark.

In the specific implementation, after decoding module is to the Matrix Calculating mark Instruction decoding, the control signal according to caused by decoding, Input matrix acquired in S603 is performed to via the selected matrix comparison operation device of first order pipelining-stage multiple selector Matrix diagonals element be calculated first as a result, then the control further according to control signal the first result is inputted to via second Matrix diagonals element read group total, which is performed, in the grade selected addition of matrices arithmetic unit of pipelining-stage multiple selector obtains the second knot Fruit, the multiple selector of third level pipelining-stage would know that the grade is empty option according to control signal.Correspondingly, by second knot Fruit (exporting result) is directly transferred to output terminal.

Operational order in above-mentioned Fig. 8 is by taking the instruction of Matrix Calculating mark as an example, in practical applications, in embodiment as shown in Figure 8 The instruction of Matrix Calculating mark Matrix Calculating determinant can be used to instruct, Matrix Calculating order instructs, Matrix Calculating neutral element proportional command or matrix Maximum eigenvalue instruction equal matrix computing/operational order is asked to replace, is not repeated one by one here.

The embodiment of the present application also provides a kind of computer storage media, wherein, computer storage media storage is for electricity The computer program that subdata exchanges, it is arbitrary as described in above-mentioned embodiment of the method which so that computer is performed Implementation section or Overall Steps.

The embodiment of the present application also provides a kind of computer program product, and the computer program product includes storing calculating The non-transient computer readable storage medium of machine program, the computer program are operable to that computer is made to perform such as above-mentioned side Arbitrary implementation section or Overall Steps described in method embodiment.

The embodiment of the present application additionally provides a kind of accelerator, including：Memory：It is stored with executable instruction；Processor： For performing the executable instruction in storage unit, when executing instruction according to the embodiment recorded in above method embodiment into Row operation.

Wherein, processor can be single processing unit, but can also include two or more processing units.In addition, Processor can also include general processor (CPU) or graphics processor (GPU)；It is additionally may included in field programmable logic Gate array (FPGA) or application-specific integrated circuit (ASIC), to be configured to neutral net and computing.Processor can also wrap Include to cache the on-chip memory of purposes (i.e. including the memory in processing unit).

In some embodiments, a kind of chip is also disclosed, that includes above-mentioned for performing above method embodiment institute Corresponding neural network processor.

In some embodiments, a kind of chip-packaging structure is disclosed, that includes said chips.

In some embodiments, a kind of board is disclosed, that includes said chip encapsulating structures.

In some embodiments, a kind of electronic equipment is disclosed, that includes above-mentioned boards.

Electronic equipment include data processing equipment, robot, computer, printer, scanner, tablet computer, intelligent terminal, Mobile phone, automobile data recorder, navigator, sensor, camera, server, cloud server, camera, video camera, projecting apparatus, hand Table, earphone, mobile storage, wearable device, the vehicles, household electrical appliance, and/or Medical Devices.

The vehicles include aircraft, steamer and/or vehicle；The household electrical appliance include TV, air-conditioning, micro-wave oven, Refrigerator, electric cooker, humidifier, washing machine, electric light, gas-cooker, kitchen ventilator；The Medical Devices include Nuclear Magnetic Resonance, B ultrasound instrument And/or electrocardiograph.

It should be noted that for foregoing each method embodiment, in order to be briefly described, therefore it is all expressed as a series of Combination of actions, but those skilled in the art should know, the application and from the limitation of described sequence of movement because According to the application, some steps may be employed other orders or be carried out at the same time.Secondly, those skilled in the art should also know It knows, embodiment described in this description belongs to alternative embodiment, involved action and module not necessarily the application It is necessary.

In the above-described embodiments, all emphasize particularly on different fields to the description of each embodiment, there is no the portion being described in detail in some embodiment Point, it may refer to the associated description of other embodiment.

In several embodiments provided herein, it should be understood that disclosed device, it can be by another way It realizes.For example, the apparatus embodiments described above are merely exemplary, such as the division of the unit, it is only one kind Division of logic function, can there is an other dividing mode in actual implementation, such as multiple units or component can combine or can To be integrated into another system or some features can be ignored or does not perform.Another, shown or discussed is mutual Coupling, direct-coupling or communication connection can be by some interfaces, the INDIRECT COUPLING or communication connection of device or unit, Can be electrical or other forms.

The unit illustrated as separating component may or may not be physically separate, be shown as unit The component shown may or may not be physical location, you can be located at a place or can also be distributed to multiple In network element.Some or all of unit therein can be selected to realize the mesh of this embodiment scheme according to the actual needs 's.

In addition, each functional unit in each embodiment of the application can be integrated in a processing unit, it can also That unit is individually physically present, can also two or more units integrate in a unit.Above-mentioned integrated list The form that hardware had both may be employed in member is realized, can also be realized in the form of software program module.

If the integrated unit is realized in the form of software program module and is independent production marketing or use When, it can be stored in a computer-readable access to memory.Based on such understanding, the technical solution of the application substantially or Person say the part contribute to the prior art or the technical solution all or part can in the form of software product body Reveal and, which is stored in a memory, is used including some instructions so that a computer equipment (can be personal computer, server or network equipment etc.) performs all or part of each embodiment the method for the application Step.And foregoing memory includes：USB flash disk, read-only memory (ROM, Read-Only Memory), random access memory The various media that can store program code such as (RAM, Random Access Memory), mobile hard disk, magnetic disc or CD.

One of ordinary skill in the art will appreciate that all or part of step in the various methods of above-described embodiment is can Relevant hardware to be instructed to complete by program, which can be stored in a computer-readable memory, memory It can include：Flash disk, read-only memory (English：Read-Only Memory, referred to as：ROM), random access device (English： Random Access Memory, referred to as：RAM), disk or CD etc..

The embodiment of the present application is described in detail above, specific case used herein to the principle of the application and Embodiment is set forth, and the explanation of above example is only intended to help to understand the present processes and its core concept； Meanwhile for those of ordinary skill in the art, according to the thought of the application, can in specific embodiments and applications There is change part, in conclusion this specification content should not be construed as the limitation to the application.

Claims

1. a kind of computational methods, which is characterized in that applied in computing device, the computing device includes storage medium, deposit Device unit and matrix operation unit, the described method includes：

The computing device controls the matrix operation unit to obtain the first operational order, and first operational order is used to implement Computing between matrix and scalar, the matrix that first operational order includes performing needed for described instruction reads instruction, described Required matrix is at least one matrix, and at least one matrix is the matrix that length is identical or length is different；

The computing device controls the matrix operation unit to read instruction according to the matrix and sends reading to the storage medium Take order；

The computing device is controlled described in the matrix operation unit read from the storage medium using batch reading manner Matrix reads the corresponding matrix of instruction, and using the calculation of multistage pipelining-stage, first fortune is performed to the matrix Calculate instruction.

2. according to the method described in claim 1, it is characterized in that, it is described multistage pipelining-stage in each pipelining-stage include to A few arithmetic unit,

The calculation using multistage pipelining-stage, performing first operational order to the matrix includes：

The computing device controls selection of the matrix operation unit according to multiple selector, using in first order pipelining-stage First choice arithmetic unit to the matrix be calculated first as a result, first result is input to second level pipelining-stage In the execution of the second Selecting operation device be calculated second as a result, and so on, until inputting (i-1)-th result to i-stage I-th of result is calculated in the i-th Selecting operation device execution in pipelining-stage；

I-th of result is inputted to the storage medium and is stored；

Wherein, i-th of result is output matrix, and the quantity i of the multistage pipelining-stage is according to first operational order Calculating topological structure determine that and i is positive integer.

3. according to the method described in claim 1, it is characterized in that, it is described multistage pipelining-stage in each pipelining-stage include it is pre- The fixation arithmetic unit first set, the fixation arithmetic unit in each pipelining-stage differ,

The computing device controls the matrix operation unit using the fixation arithmetic unit in first order pipelining-stage to the matrix First be calculated as a result, the fixation arithmetic unit execution that first result is input in the pipelining-stage of the second level is calculated To second as a result, and so on, until (i-1)-th result inputted to the fixation arithmetic unit in i-stage pipelining-stage performing calculating Obtain i-th of result；

I-th of result is inputted to the storage medium and is stored；

Wherein, the quantity i of the multistage pipelining-stage is determined according to the calculating topological structure of first operational order, and i For positive integer.

4. method according to any one of claim 1-3, which is characterized in that each flowing water in the multistage pipelining-stage Grade is each configured with corresponding multiple selector, and the multiple selector setting is free option, the sky option be used to indicate with The kth grade pipelining-stage of the multiple selector connection and subsequent kth+1 not perform to i-stage pipelining-stage and calculate behaviour Make, wherein, k is the positive integer less than or equal to i；

Arithmetic unit in the multistage pipelining-stage in each pipelining-stage includes any one of following or multinomial combination：Matrix adds Method arithmetic unit, matrix multiplication operation device, matrix scalar multiplication arithmetic unit, nonlinear operator and matrix comparison operation device.

5. according to the method described in claim 1, it is characterized in that, first operational order is including any one of following： Matrix Calculating determinant command M DET, Matrix Calculating order command M RANK, Matrix Calculating mark command M TRA, Matrix Calculating neutral element proportional command MNZ, Matrix Calculating dominant eigenvalue command M EVA；

The instruction format of first operational order includes at least one command code and at least one operation domain, described at least one Command code is used to indicate the function of first operational order, and at least one operation domain is used to indicate first computing and refers to The data message of order, the data message include immediate or register number, and instruction and institute are read for storing the matrix State the length of matrix；Wherein, at least one command code includes the first command code and the second command code, first command code The type of first operational order is used to indicate, second command code is used to indicate the function of first operational order.

6. according to the method described in right 2, which is characterized in that first operational order is Matrix Calculating determinant command M DET,

The computing device controls selection of the matrix operation unit according to multiple selector, using in first order pipelining-stage Matrix comparison operation device to the matrix carry out inverse order of sequence computing obtain first as a result, by first result input to In the pipelining-stage of the second level with utilize the matrix multiplication operation device in it to first result carry out all sequences multiplying Second is obtained as a result, inputting into third level pipelining-stage to utilize the addition of matrices arithmetic unit in it to institute by second result It states the second result progress all sequences summation operation and obtains the 3rd result；By the 3rd result input to the storage medium into Row storage.

7. a kind of computing device, which is characterized in that the computing device includes storage medium, register cell, matrix operation list Member and controller unit；

The storage medium, for storage matrix；

The register cell, for storing scalar data, the scalar data includes at least：The matrix is situated between in the storage Storage address in matter；

The controller unit, for the matrix operation unit to be controlled to obtain the first operational order, first operational order The computing being used to implement between matrix and scalar, the matrix reading that first operational order includes performing needed for described instruction refer to Show, the required matrix is at least one matrix, and at least one matrix is the matrix that length is identical or length is different；

The matrix operation unit sends reading order for reading instruction according to the matrix to the storage medium；Foundation The matrix is read using batch reading manner and reads the corresponding matrix of instruction, using the calculation of multistage pipelining-stage, to institute It states matrix and performs first operational order.

8. a kind of chip, which is characterized in that the chip includes the as above computing device described in claim 7.

9. a kind of electronic equipment, which is characterized in that the electronic equipment includes the as above chip described in claim 8.

10. a kind of computer readable storage medium, which is characterized in that the computer storage media is stored with computer program, The computer program includes program instruction, and described program instruction makes the processor perform such as right when being executed by a processor It is required that 1-6 any one of them methods.