CN107786294B - A kind of centralized 1588 realization system and method - Google Patents
A kind of centralized 1588 realization system and method Download PDFInfo
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- CN107786294B CN107786294B CN201710862615.9A CN201710862615A CN107786294B CN 107786294 B CN107786294 B CN 107786294B CN 201710862615 A CN201710862615 A CN 201710862615A CN 107786294 B CN107786294 B CN 107786294B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0641—Change of the master or reference, e.g. take-over or failure of the master
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0658—Clock or time synchronisation among packet nodes
- H04J3/0661—Clock or time synchronisation among packet nodes using timestamps
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0682—Clock or time synchronisation in a network by delay compensation, e.g. by compensation of propagation delay or variations thereof, by ranging
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Abstract
A kind of centralized 1588 realization system and method, it is related to 1588 time synchronization fields, system includes master clock device and the device from clock, and each device includes main control unit and route disk, include time synchronization module in main control unit and route disk, further includes local zone time module in main control unit；Main control unit time synchronization module completes the transmission of 1588 messages, receives work, and is adjusted according to the time synchronization that the data being collected into calculate deviation finishing device；Main control unit local zone time module gives route disk time synchronization module synchronization for exporting 1PPS+TOD signal, is also used to complete the normal forwarding of 1588 messages and beats the Forwarding Delay that timestamp corrects message portion in the device；Route disk time synchronization module completes the normal forwarding of 1588 messages and beats the Forwarding Delay that timestamp corrects message portion in the device.The present invention guarantees the convergence of time synchronization between centralized realization device in the case where arbitrary velocity message interaction.
Description
Technical field
The present invention relates to 1588 time synchronization fields, in particular to a kind of centralized 1588 realization system and side
Method.
Background technique
Currently, being broadly divided into distributed implementation for the implementation of 1588 time synchronism apparatus and centralization being realized.Its
In, centralized implementation method has apparent advantage, becomes the way of mainstream gradually.With reference to IEEE1588-2008 standard, 1588
Time synchronization technique gets 4 by synchronisation message, time delay request message and DELAY RESPONSE message between master and slave devices
A timestamp t1, t2, t3, t4 and sync message amendment domain CF1, time delay request message correct domain CF2, then according to formula:
Time deviation=((t2-t1-CF1)-(t4-t3-CF2))/2
Reporting is obtained, the time synchronization between realization device is adjusted.
(1) as shown in Figure 1, tradition centralization realization device generally comprises main control unit and route disk two parts, inside the two
It is provided with a time synchronization module.
Main control unit time synchronization module completes the transmission of 1588 messages, receives work, and is calculated according to the data being collected into
Deviation, the time synchronization adjustment of finishing device.
Route disk time synchronization module completes the normal forwarding of 1588 messages and beats timestamp, and amendment message is in the device
The Forwarding Delay in portion.
Main control unit time synchronization module and route disk time synchronization module must assure that time synchronization, only guaranteed 2 moulds
The time reference of block is consistent, and Forwarding Delay just can be accurate inside the modified message of route disk.Common practice is that main control unit is sent
1PPS+TOD signal gives route disk, the time of route disk synchronous 1 main control unit every 1 second.
(2) as shown in Fig. 2, correcting the schematic diagram of domain CF1 to obtain t1, t2 timestamp and sync message.
1 main control unit time synchronization module of device sends sync message and stamps timestamp t1, which takes as master clock
Band issues in sync message, and the amendment domain CF1 field value of sync message is 0 at this time.
1 route disk time synchronization module of device receives sync message, stamps timestamp t1', updates the amendment domain CF1 of message
Value is t1'-t1 (difference is exactly Forwarding Delay of the sync message inside device 1), and sync message transfers device 1.
2 route disk time synchronization module of device receives sync message, stamps timestamp t2', which carries in synchronization
2 main control unit of device is transmitted in message.
2 main control unit time synchronization module of device is used as from clock, is received sync message and is stamped timestamp t2, updates message
Amendment domain CF1 value be the t1'-t1+t2-t2'(difference be exactly total Forwarding Delay of the message inside device 1,2).
(3) as shown in Fig. 3, the schematic diagram of domain CF2 is corrected to obtain t3, t4 timestamp and time delay request message.
2 main control unit time synchronization module of device be used as from clock, transmission delay request message simultaneously stamps timestamp t3, this when
Portion is locally stored in stamp, while carrying and issuing in time delay request message, and the amendment domain CF2 field value of message is 0 at this time.
2 route disk time synchronization module of device receives time delay request message, stamps timestamp t3', updates time delay request report
The amendment domain CF2 value of text is t3'-t3 (difference is exactly Forwarding Delay of the time delay request message inside device 2), time delay
Request message transfers device 2.
1 route disk time synchronization module of device receives time delay request message, stamps timestamp t4', which carries
1 main control unit of device is transmitted in time delay request message.
1 main control unit time synchronization module of device simultaneously stamps timestamp t4 as master clock, reception delay request message, updates
When the amendment domain CF2 value of message is that the t3'-t3+t4-t4'(difference is exactly total forwarding of the message inside device 1,2
Prolong).
1 main control unit time synchronization module of device replys DELAY RESPONSE message, carry in time delay request message upper t4 and
CF2, the time delay request message are transparent to always 2 main control unit time synchronization module of device, and intermediate link is not processed.
By above-mentioned (2) and (3), from clock apparatus time synchronization module got required for adjustment deviation to
Total data can normally complete the time synchronization with master clock device time synchronization module.But it carefully analyzes, it can be seen that should
There are hidden danger for implementation.
It is assumed that when master clock device main control unit time synchronization module and initial route disk time synchronization module
Between be 0, be 5 from clock apparatus main control unit time synchronization module and route disk time synchronization module time, then leading at this time
It is 5 from clock offset time, the forward-path time delay between message module might as well be fixed as 1, then need to count by message interaction
It calculates deviation and adjusts.
1 main control unit time synchronization module initial time of device is 0, issues sync message at this time and stamps timestamp t1=0,
The amendment domain CF1 field value of message is 0 at this time.
1 route disk time synchronization module of device receives sync message, and the module time is 1 at this time, so timestamp t1'=
1, the amendment domain CF1 value for updating message is t1'-t1=1-0=1.
2 route disk time synchronization module of device receives sync message, and the module time is 7 at this time, so timestamp t2'=
7。
2 main control unit time synchronization module of device receives sync message, and the module time is 8 at this time, so timestamp t2=
8, the amendment domain CF1 value for updating message is t1'-t1+t2-t2'=1-0+8-7=2.
2 main control unit time synchronization module transmission delay request message of device, it is assumed that while receiving sync message at once
Transmission delay request message, the module time is still 8 at this time, so timestamp t3=8, the amendment domain CF2 word of message at this time
Section value is 0.
2 route disk time synchronization module of device receives time delay request message, and the module time is 9 at this time, so timestamp
T3'=9, the amendment domain CF2 value for updating message is t3'-t3=9-8=1.
1 route disk time synchronization module of device receives time delay request message, and the module time is 5 at this time, so timestamp
T4'=5.
1 main control unit time synchronization module of device receives time delay request message, and the module time is 6 at this time, so timestamp
T4=6, the amendment domain CF2 value for updating message is t3'-t3+t4-t4'=9-8+6-5=2.
Message interaction finishes, and calculates deviation ((t2-t1-CF1)-(t4-t3-CF2))/2=((8-0-2)-from clock apparatus
(6-8-2))/2=5, illustrate from clock apparatus faster than master clock device 5, is at this time 11 from clock apparatus time, so adjustment
Time is 11-5=6, and the master clock device time is just 6, the two time synchronization.
But to be adjusted at this time only from clock master disk time synchronization module, and from clock line disk time synchronization mould
The time of block or 11, according to above-mentioned (1) it is found that from clock master disk time synchronization module by export 1PPS+TOD signal to
Realize synchronization between the two from clock line disk time synchronization module, however the signal is per second just issues 1 time, then at this time
If:
1. completed next time before message interaction from clock, from clock line disk time synchronization module synchronize in time from when
Clock main control unit time synchronization module can find principal and subordinate then the subsequent how many times message interaction that no matter repeats calculates deviation adjusting
The time deviation of clock apparatus is fixed as always 0, synchronous convergence.
2. failing to synchronize in time from clock line disk time synchronization module before completing message interaction next time from clock
From clock master disk time synchronization module, it is assumed that 4 message interactions of completion in 1 second, repeatedly before deviation calculate, will
It was found that the time deviation of master-salve clock device as shown in figure 5, can not stable convergence to 0, be not able to satisfy the requirement of time synchronization.
In conclusion for traditional centralized realization device, must be requested that message interaction speed is per second no more than 1
Secondary, not so synchronizing can not restrain.It is per second under normal circumstances to complete 16 message interactions and according to the requirement of 1588 standards, far
Far more than 1 time, in the case of high-speed message interaction, how centralized fashion guarantees that time synchronization process convergence is to be badly in need of
It solves the problems, such as.
Summary of the invention
In view of the deficiencies in the prior art, the purpose of the present invention is to provide a kind of centralized 1588 realization systems
And method guarantees the convergence of time synchronization between centralized realization device in the case where arbitrary velocity message interaction.
To achieve the above objectives, the present invention takes a kind of centralized 1588 realization system, including master clock device and from
The device of clock, each device include main control unit and route disk, include a time synchronization mould in main control unit and route disk
Block further includes a local zone time module, time oneself maintenance of main control unit local zone time module, for defeated in the main control unit
1PPS+TOD signal gives route disk time synchronization module synchronization out, while main control unit local zone time module is also used to complete 1588 reports
The normal forwarding of text and beat the Forwarding Delay that timestamp corrects message portion in the device.
Based on the above technical solution, the main control unit time synchronization module is completed the transmission of 1588 messages, is received
Work, and adjusted according to the time synchronization that the data being collected into calculate deviation finishing device；The route disk time synchronization module
It completes the normal forwarding of 1588 messages and beats the Forwarding Delay that timestamp corrects message portion in the device.
The present invention provides the implementation method of centralization 1588, comprising steps of
S1. the main control unit time synchronization module of master clock device sends sync message and stamps timestamp t1, with device
Sync message is stamped timestamp t1' by main control unit local zone time module, and correcting domain CF1 field value at this time is 0；With the line of device
Sync message is stamped timestamp t1 " by road disk time synchronization module, and amendment domain CF1 field value is t1 "-t1'；
Sync message is received from the route disk time synchronization module of clock apparatus, timestamp t2 " is stamped, with the master control of device
Disk local zone time module receives sync message, stamps timestamp t2', and amendment domain CF1 field value is t1 "-t1'+t2'-t2 "；
Main control unit time synchronization module with device receives sync message and stamps timestamp t2；
S2. from the main control unit time synchronization module transmission delay request message of clock apparatus and timestamp t3 is stamped, with filling
The main control unit local zone time module set receives time delay request message and stamps timestamp t3', and correcting domain CF2 field value at this time is 0；
Route disk time synchronization module with device receives time delay request message, stamps timestamp t3 ", and amendment domain CF2 field value is
t3"-t3'；
The route disk time synchronization module of master clock device receives time delay request message, timestamp t4 " is stamped, with device
Main control unit local zone time module receives time delay request message, stamps timestamp t4', and amendment domain CF2 field value is t3 "-t3'+
t4'-t4"；With device main control unit time synchronization module reception delay request message and stamp timestamp t4, then reply time delay
Response message is transparent to from clock apparatus main control unit time synchronization module；
S3. time deviation is calculated from clock apparatus by formula ((t2-t1-CF1)-(t4-t3-CF2))/2, carries out the time
It is synchronous.
Based on the above technical solution, in institute S1, timestamp t1 carrying is sent to same device in sync message
Main control unit local zone time module；Timestamp t1' carries the route disk time synchronization module that same device is sent in sync message.
Based on the above technical solution, in the S1, the synchronous report from master clock device is received from clock apparatus
Wen Hou, timestamp t2 " carry the main control unit that same device is transmitted in sync message.
Based on the above technical solution, in the S2, the timestamp stamped from clock apparatus in time delay request message
T3 is locally stored portion, while carrying and being sent to same device main control unit local zone time module in time delay request message.
Based on the above technical solution, in the S2, what the route disk time synchronization module of master clock device was stamped
Main control unit local zone time module in same device is issued in timestamp t4 ", carrying in time delay request message.
Based on the above technical solution, in the S2, when the main control unit time synchronization module of master clock device is replied
Prolong response message, wherein carrying timestamp t4 and amendment domain CF2, intermediate link is not processed, is transparent to from clock apparatus master control
Disk time synchronization module.
The beneficial effects of the present invention are: by the way that local zone time module is arranged in the main control unit of two devices, to receiving
Message stamp timestamp, therefore two devices are no longer required for route disk time synchronization module synchronization main control unit time synchronization mould
Block, but synchronous main control unit local zone time module, main control unit local zone time module does not need same with main control unit time synchronization module
Step.Due to main control unit local zone time module oneself safeguard, the time be it is stable, do not need to adjust, thus evade falling
The not real-time defect of 1PPS+TOD synchronizing channel.In the case of arbitrary velocity message interaction, especially high-speed message interaction,
Guarantee the convergence of time synchronization between centralized realization device.
Detailed description of the invention
Fig. 1 is the centralized realization device configuration diagram of tradition in background technique；
Fig. 2 is the centralized realization device synchronisation message schematic diagram of tradition in background technique；
Fig. 3 is the centralized realization device interaction time delay request message schematic diagram of tradition in background technique；
Fig. 4 is the centralized realization device representative instance schematic diagram of tradition in background technique；
Fig. 5 is that background technique high speed rate deviation dissipates schematic diagram；
Fig. 6 is the realization system schematic of present invention centralization 1588；
Fig. 7 is synchronisation message schematic diagram in the implementation method of present invention centralization 1588；
Fig. 8 is interaction time delay request message schematic diagram in the implementation method of present invention centralization 1588；
Fig. 9 is synchronisation message schematic diagram in the specific embodiment of the invention；
Figure 10 is interaction time delay request message schematic diagram in the specific embodiment of the invention.
Specific embodiment
Invention is further described in detail with reference to the accompanying drawings and embodiments.
As shown in fig. 6, the realization system of present invention centralization 1588, including master clock device and from the device of clock, often
A device all includes main control unit and route disk, includes a time synchronization module in main control unit and route disk, goes back in main control unit
Including a local zone time module.Main control unit time synchronization module completes the transmission of 1588 messages, receives work, and according to collection
The data arrived calculate the time synchronization adjustment of deviation finishing device.The time oneself of main control unit local zone time module safeguards, is not required to
It is synchronous with external module, it does not need to adjust, main control unit local zone time module is for when exporting 1PPS+TOD signal to route disk
Between synchronization module it is synchronous；Main control unit local zone time module is also used to complete the normal forwarding of 1588 messages and beats timestamp simultaneously
Correct the Forwarding Delay in message portion in the device.When route disk time synchronization module is completed the normal forwarding of 1588 messages and is beaten
Between stamp amendment message portion in the device Forwarding Delay.
The implementation method of centralization 1588 of the invention, includes the following steps:
S1. the amendment domain CF1 of acquisition time stamp t1, t2 and sync message.As shown in fig. 7, sync message is filled in master clock
It sets and forwards from completion between clock apparatus and beat timestamp, detailed step is as follows:
S101. the main control unit time synchronization module of master clock device sends sync message and stamps timestamp t1, timestamp
T1 carrying issues in sync message, and the amendment domain CF1 field value of sync message is 0 at this time.
S102. the main control unit local zone time module of master clock device receives sync message, stamps timestamp t1', timestamp
T1' carrying issues in sync message, and the amendment domain CF1 field value of sync message is 0 at this time.
S103. sync message is stamped into timestamp t1 " with the route disk time synchronization module of device, updates sync message
Amendment domain CF1 field value be t1 "-t1', and forward the packet out master clock device.
S104. sync message is received from the route disk time synchronization module of clock apparatus, stamps timestamp t2 ", timestamp
T2 " stamp carries the main control unit that same device is transmitted in sync message.
S105. sync message is received from the main control unit local zone time module of clock apparatus, stamps timestamp t2', change is same
The amendment domain CF1 field value for walking message is t1 "-t1'+t2'-t2 ", it is transmitted to the main control unit time synchronization module of same device.
S106. sync message is received from the main control unit time synchronization module of clock apparatus, and stamps timestamp t2.
S2. the amendment domain CF2 of acquisition time stamp t4, t4 and time delay request message.As shown in figure 8, time delay request message, when
Prolong response message to forward in master clock device and from completion between clock apparatus and beat timestamp, specifically includes the following steps:
S201. from the main control unit time synchronization module transmission delay request message of clock apparatus, and timestamp t3 is stamped, when
Between stamp t3 be locally stored portion, while carrying and being issued in time delay request message, at this time the amendment domain CF2 word of time delay request message
Section value is 0.
S202. time delay request message is received from the main control unit local zone time module of clock apparatus, stamp timestamp t3' and turned
The route disk of same device is issued, the amendment domain CF2 field value of time delay request message is 0 at this time.
S203. time delay request message is received from the route disk time synchronization module of clock apparatus, stamps timestamp t3 ", more
The amendment domain CF2 field value of new time delay request message is t3 "-t3', and message is transferred from clock apparatus.
S204. the route disk time synchronization module of master clock device receives time delay request message, stamps timestamp t4 ", when
Between stab t4 " stamp and carry and be transmitted to the main control unit of same device in time delay request message.
S205. the main control unit local zone time module of master clock device receives time delay request message, stamps timestamp t4', more
The amendment domain CF2 field value of new time delay request message is t3 "-t3'+t4'-t4 ", the main control unit time for being transmitted to same device is same
Walk module.
S206. the main control unit time synchronization module reception delay request message of master clock device and timestamp t4 is stamped, so
DELAY RESPONSE message is replied afterwards, wherein carrying upper t4 and CF2, DELAY RESPONSE message is transparent to always the master control from clock apparatus
Disk time synchronization module, intermediate link are not processed.
S3. pass through formula from the main control unit time synchronization module of clock apparatus: time deviation=((t2-t1-CF1)-(t4-
T3-CF2))/2, time deviation is calculated, and carries out time synchronization.
As shown in Figure 9 and Figure 10, the present invention is further illustrated by a specific embodiment, it is assumed that master clock device
Main control unit time synchronization module time is 0, and main control unit local zone time module and route disk time synchronization module initial time are
1；It is 5 from the main control unit time synchronization module time of clock apparatus, main control unit local zone time module and route disk time synchronization mould
Block initial time is 2.So the time deviation of master and slave clock time is 5 at this time, and the forward-path time delay between message module is not
Harm is fixed as 1, then the step of calculating time deviation by message interaction and adjusting is as follows:
A101. the main control unit time synchronization module initial time of master clock device is 0, issues sync message at this time and stamps
Timestamp t1=0, the amendment domain CF1 field value of sync message is 0 at this time.
A102. the main control unit local zone time module of master clock device receives sync message, and the module time is 2 at this time, institute
With timestamp t1'=2, the amendment domain CF1 field value of sync message is 0 at this time.
A103. the route disk time synchronization module of master clock device receives sync message, and the module time is 3 at this time, institute
With timestamp t1 "=3, the amendment domain CF1 field value for updating sync message is t1 "-t1'=3-2=1.
A104. sync message is received from the route disk time synchronization module of clock apparatus, the module time is 5 at this time, institute
With timestamp t2 "=5.
A105. sync message is received from the main control unit local zone time module of clock apparatus, the module time is 6 at this time, institute
With timestamp t2'=6, the amendment domain CF1 field value for updating sync message is t1 "-t1'+t2'-t2 "=3-2+6-5=2.
A106. sync message is received from the main control unit time synchronization module of clock apparatus, the module time is 10 at this time, institute
With timestamp t2=10.
A107. from the main control unit time synchronization module transmission delay request message of clock apparatus, might as well assume to receive synchronization
At once with regard to transmission delay request message while message, the module time is still 10 at this time, so timestamp t3=10, at this time
The amendment domain CF2 field value of time delay request message is 0.
A108. time delay request message is received from the main control unit local zone time module of clock apparatus, the module time is at this time
8, so timestamp t3'=8, the amendment domain CF2 field value of time delay request message is 0 at this time.
A109. time delay request message is received from the route disk time synchronization module of clock apparatus, the module time is at this time
9, so timestamp t3 "=9, the amendment domain CF2 field value for updating time delay request message is t3 "-t3'=9-8=1.
A110. the route disk time synchronization module of master clock device receives time delay request message, and the module time is at this time
9, so timestamp t4 "=9.
A111. the local zone time module of master clock device receives time delay request message, and the module time is 10 at this time, so
Timestamp t4'=10, the amendment domain CF2 field value for updating time delay request message is t3 "-t3'+t4'-t4 "=9-8+10-9
=2.
A112. the main control unit time synchronization module of master clock device receives time delay request message, and the module time is at this time
10, so timestamp t4=10, replys the DELAY RESPONSE message for carrying upper t4 and CF2, is transparent to always from clock apparatus
Main control unit time synchronization module, message interaction finish.
A113. time deviation, time deviation=((t2-t1- are calculated from the main control unit time synchronization module of clock apparatus
CF1)-(t4-t3-CF2))/2=((10-0-2)-(10-10-2))/2=5, illustrate faster than master clock device from clock apparatus
5, it is at this time 15 from the clock apparatus time, so adjustment time is 15-5=10, and the master clock device time is just 10, the two
Time synchronization, and at this time no matter how fast message interaction rate, it all will not influence the convergence synchronous from clock apparatus, always can
Enough rapidly converge to 0.
The present invention is not limited to the above-described embodiments, for those skilled in the art, is not departing from
Under the premise of the principle of the invention, several improvements and modifications can also be made, these improvements and modifications are also considered as protection of the invention
Within the scope of.The content being not described in detail in this specification belongs to the prior art well known to professional and technical personnel in the field.
Claims (7)
1. a kind of centralized 1588 realization system, including master clock device and from the device of clock, each device includes master
It manipulates stock quotations and route disk, includes a time synchronization module in main control unit and route disk, it is characterised in that: in the main control unit also
Including a local zone time module, the time oneself of main control unit local zone time module is safeguarded, for export 1PPS+TOD signal to
Route disk time synchronization module synchronization, at the same main control unit local zone time module be also used to complete 1588 messages it is normal forwarding and
Beat the Forwarding Delay in timestamp amendment message portion in the device；
The main control unit time synchronization module completes the transmission of 1588 messages, receives work, and is calculated according to the data being collected into
The time synchronization of deviation finishing device adjusts；The route disk time synchronization module is completed the normal forwarding of 1588 messages and is beaten
Timestamp corrects the Forwarding Delay in message portion in the device.
2. a kind of implementation method based on the centralization 1588 for realizing system described in claim 1, which is characterized in that including step
It is rapid:
S1. the main control unit time synchronization module of master clock device sends sync message and stamps timestamp t1, with the master control of device
Sync message is stamped timestamp t1' by disk local zone time module, and correcting domain CF1 field value at this time is 0；With the route disk of device
Sync message is stamped timestamp t1 " by time synchronization module, and amendment domain CF1 field value is t1 "-t1'；
Sync message is received from the route disk time synchronization module of clock apparatus, timestamp t2 " is stamped, with the main control unit sheet of device
Ground time module receives sync message, stamps timestamp t2', and amendment domain CF1 field value is t1 "-t1'+t2'-t2 "；With dress
The main control unit time synchronization module set receives sync message and stamps timestamp t2；
S2. from the main control unit time synchronization module transmission delay request message of clock apparatus and timestamp t3 is stamped, with device
Main control unit local zone time module receives time delay request message and stamps timestamp t3', and correcting domain CF2 field value at this time is 0；With dress
The route disk time synchronization module set receives time delay request message, stamps timestamp t3 ", and amendment domain CF2 field value is t3 "-
t3'；
The route disk time synchronization module of master clock device receives time delay request message, timestamp t4 " is stamped, with the master control of device
Disk local zone time module receives time delay request message, stamps timestamp t4', and amendment domain CF2 field value is t3 "-t3'+t4'-
t4"；With device main control unit time synchronization module reception delay request message and stamp timestamp t4, then reply DELAY RESPONSE
Message transmission is to from clock apparatus main control unit time synchronization module；
S3. time deviation is calculated from clock apparatus by formula ((t2-t1-CF1)-(t4-t3-CF2))/2, it is same carries out the time
Step.
3. the implementation method of centralization 1588 as claimed in claim 2, it is characterised in that: in institute S1, timestamp t1 is carried same
The main control unit local zone time module of same device is sent in step message；Timestamp t1' carrying is sent to dress in sync message
The route disk time synchronization module set.
4. the implementation method of centralization 1588 as claimed in claim 2, it is characterised in that: in the S1, received from clock apparatus
After sync message from master clock device, timestamp t2 " carries the main control unit that same device is transmitted in sync message.
5. as claimed in claim 2 centralization 1588 implementation method, it is characterised in that: in the S2, from clock apparatus when
Prolong the timestamp t3 that request message is stamped, portion is locally stored, while carrying and being sent to same device master in time delay request message
It manipulates stock quotations local zone time module.
6. the implementation method of centralization 1588 as claimed in claim 2, it is characterised in that: in the S2, the line of master clock device
The timestamp t4 " that road disk time synchronization module is stamped, when main control unit local in same device is issued in carrying in time delay request message
Between module.
7. the implementation method of centralization 1588 as claimed in claim 2, it is characterised in that: in the S2, the master of master clock device
Time synchronization of manipulating stock quotations module replys DELAY RESPONSE message, wherein carrying timestamp t4 and amendment domain CF2, intermediate link, which is not done, to be located
Reason, is transparent to from clock apparatus main control unit time synchronization module.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710862615.9A CN107786294B (en) | 2017-09-22 | 2017-09-22 | A kind of centralized 1588 realization system and method |
| BR112020001370-6A BR112020001370A2 (en) | 2017-09-22 | 2018-08-27 | centralized implementation system and method for 1588. |
| PCT/CN2018/102459 WO2019056921A1 (en) | 2017-09-22 | 2018-08-27 | Centralized 1588 implementation system and method |
| PH12020550002A PH12020550002A1 (en) | 2017-09-22 | 2020-01-02 | Centralized 1588 implementation system and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710862615.9A CN107786294B (en) | 2017-09-22 | 2017-09-22 | A kind of centralized 1588 realization system and method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107786294A CN107786294A (en) | 2018-03-09 |
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| CN (1) | CN107786294B (en) |
| BR (1) | BR112020001370A2 (en) |
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| CN107786294B (en) * | 2017-09-22 | 2019-04-30 | 烽火通信科技股份有限公司 | A kind of centralized 1588 realization system and method |
| CN113225253B (en) | 2020-01-21 | 2022-08-09 | 华为技术有限公司 | Message forwarding method and device |
| CN111865464B (en) * | 2020-06-30 | 2022-03-01 | 烽火通信科技股份有限公司 | Automatic mounting method and device for multi-slot communication system clock channel |
| CN113573403B (en) * | 2021-07-26 | 2023-11-03 | 南京濠暻通讯科技有限公司 | Slave clock synchronization system and method for 5G RRU |
| CN114157381A (en) * | 2021-12-09 | 2022-03-08 | 福州大学 | Network delay jitter-oriented dynamic delay estimation period adjustment method |
| CN115021853B (en) * | 2022-06-09 | 2023-02-28 | 广州市保伦电子有限公司 | Clock synchronization method between master device and slave device based on PID control algorithm |
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| WO2014040453A1 (en) * | 2012-09-12 | 2014-03-20 | 大唐移动通信设备有限公司 | Clock synchronization system and method for base station |
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| CN102123046B (en) * | 2011-01-21 | 2013-09-04 | 烽火通信科技股份有限公司 | Packet transport network (PTN) device and method for realizing time synchronization protection switching (PS) by using main cross disk and spare cross disk of PTN device |
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| CN105281882A (en) * | 2014-06-30 | 2016-01-27 | 中兴通讯股份有限公司 | Method and device for realizing time synchronization |
| CN107786294B (en) * | 2017-09-22 | 2019-04-30 | 烽火通信科技股份有限公司 | A kind of centralized 1588 realization system and method |
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| CN102142954A (en) * | 2010-11-30 | 2011-08-03 | 中兴通讯股份有限公司 | Time synchronization method and equipment in rack |
| CN103210690B (en) * | 2011-09-09 | 2014-12-31 | 华为技术有限公司 | Time synchronization method and system, and node device |
| WO2014040453A1 (en) * | 2012-09-12 | 2014-03-20 | 大唐移动通信设备有限公司 | Clock synchronization system and method for base station |
| CN105939243A (en) * | 2016-04-14 | 2016-09-14 | 烽火通信科技股份有限公司 | Multi-port PTP (Precision Time Protocol) message processing system |
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| CN107786294A (en) | 2018-03-09 |
| WO2019056921A1 (en) | 2019-03-28 |
| PH12020550002A1 (en) | 2020-10-12 |
| BR112020001370A2 (en) | 2020-08-11 |
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