CN105939243A - Multi-port PTP (Precision Time Protocol) message processing system - Google Patents
Multi-port PTP (Precision Time Protocol) message processing system Download PDFInfo
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- CN105939243A CN105939243A CN201610231798.XA CN201610231798A CN105939243A CN 105939243 A CN105939243 A CN 105939243A CN 201610231798 A CN201610231798 A CN 201610231798A CN 105939243 A CN105939243 A CN 105939243A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/46—Interconnection of networks
- H04L12/4633—Interconnection of networks using encapsulation techniques, e.g. tunneling
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0647—Synchronisation among TDM nodes
- H04J3/065—Synchronisation among TDM nodes using timestamps
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/46—Interconnection of networks
- H04L12/4641—Virtual LANs, VLANs, e.g. virtual private networks [VPN]
- H04L12/4645—Details on frame tagging
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/46—Interconnection of networks
- H04L12/4641—Virtual LANs, VLANs, e.g. virtual private networks [VPN]
- H04L12/467—Arrangements for supporting untagged frames, e.g. port-based VLANs
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- Computer Networks & Wireless Communication (AREA)
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- Computer Security & Cryptography (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
The invention discloses a multi-port PTP (Precision Time Protocol) message processing system, and relates to the field of communication. The system comprises a CPU interface module, a real-time time generation module, a sending mark and serial number generation module, a Sync frame sending module, a Delay _Req frame sending module, a Delay _Resp frame sending module, an Announce frame sending module, a Sync frame receiving module, a Delay _Req frame receiving module, a Delay _Resp frame receiving module, an Announce frame receiving module, a multiplexing module, a demultiplexing module and a frame monitoring module. According to the system, the development cost of a communication network device can be effectively reduced, and a flexible PTP message processing scheme can be provided.
Description
Technical field
The present invention relates to the communications field, be specifically related to the process of a kind of multiport PTP message
System.
Background technology
Measuring and in control system along with the development of network technology, especially Ethernet
Application is more and more extensive, and cyber-net industry is also same in the timing being devoted to solve Ethernet
The problem of step scarce capacity, to reduce the volume using other technology, such as IRIG-B etc. to bring
Outer wiring expenditure.Then NTP (the Network Time of a kind of software mode is developed
Protocol, NTP), improve the Timing Synchronization ability between each network equipment.
The synchronous accuracy of NTP version in 1992 can reach 200 μ s, but still can not
Meet the accuracy needed for measuring instrument and Industry Control.Network precision interval clock synchronize committee in
In calendar year 2001 obtain IEEE (Institute of Electrical and Electronics Engineers,
IEEE-USA) national institute of standards and technology of instrumentation and testing committee
(NIST) support, the specification that this committee drafts will obtain ieee standard in the end of the year 2002
Committee passes through, as IEEE1588 standard.The definition of this standard is exactly PTP (Precision
Time Protocol, Precision Time Protocol).
PTP protocol is without clock special line transfer clock synchronizing signal, when utilizing data network transmission
Clock synchronization message, reduces the expense setting up synchronization system；Thering is provided and GPS (Global
Positioning System, global positioning system) under identical precise manner, it is not necessary to for often
Individual equipment installs the assembly that GPS is expensive like that, it is only necessary to a high-precision local clock and
Thering is provided the parts of high precision clock stamp, relative cost is low.Hardware is used to be combined design with software,
And the various parts affecting synchronization accuracy are effectively corrected, to provide the synchronization of submicrosecond level
Precision.
PTP protocol is widely used in communication network device at present, generally uses special
PTP protocol processes chip and realizes precise synchronization function.Special PTP is used to assist
It is higher that view processes chip cost, uses also underaction.
Summary of the invention
The invention aims to overcome the deficiency of above-mentioned background technology, it is provided that a kind of multiterminal
The processing system of mouth PTP message, it is possible to effectively reduce communication network device development cost, energy
Enough processing schemes that PTP message flexibly is provided for concrete application scenarios.
The present invention provides the processing system of a kind of multiport PTP message, and this system includes CPU
Interface module, real-time time generation module, transmission mark and serial number generation module, Sync
Frame sending module, Delay_Req frame sending module, Delay_Resp frame sending module,
Announce frame sending module, Sync frame receiver module, Delay_Req frame receiver module,
Delay_Resp frame receiver module, Announce frame receiver module, Multiplexing module, demultiplexing
Module, frame monitoring module, wherein:
Sync is a kind of sync message for Frequency Synchronization of 1588v2 protocol definition；
Delay_Req is a kind of time delay calculated for chain-circuit time delay of 1588v2 protocol definition
Computation requests message；
Delay_Resp is a kind of time delay calculated for chain-circuit time delay of 1588v2 protocol definition
Calculate response message；
Announce be 1588v2 protocol definition a kind of master-salve clock between reciprocally negotiate disappear
Breath message；
Cpu i/f module is used for: give the variable distribution register address needing configuration, it is achieved
Readable/writeable depositor；Give the variable needing to read or constant distribution register address, it is achieved
Read-only register；There is provided sub-chip selection signal and data to other submodules possessing cpu i/f
Input/output interface, wherein the configuration register of 128 Precision Time Protocol PTP passages is adopted
Realize with block storage, and by sending the PTP passage that mark generates with serial number generation module
Indication signal read-out channel in a time multiplexed manner configuration data；
Real-time time generation module is used for: according to pps pulse per second signal PPS_IN and CPU of input
The second value of configuration generates real-time time, Time of Day of sampling when PPS_IN is effective
TOD_TIME is as time second, and nanoseconds is zero, the most often carrys out the rising of a clock
Edge, nanoseconds adds 8；
Send mark and serial number generation module is used for: to all kinds of PTP messages of each passage
Thering is provided and send mark and transmit Sequence Number, produce PTP frame transmission mark enables signal substantially；
Sync frame sending module is used for: complete according to the Sync frame relevant parameter of CPU configuration
Packet framing and transmission；
Delay_Req frame sending module is used for: according to the Delay_Req frame phase of CPU configuration
Related parameter completes packet framing and transmission；Delay_Req frame sending module also to
Delay_Req receiver module provides Delay_Req frame to transmit Sequence Number and sends time stamp accordingly
T3, T4 time stamp and the total CF territory from clock to master clock direction: T4-T4`+T3-T3`,
Wherein, T3 is the time stamp beaten during master control board card transmission Delay_Req frame, and T3 ' is that line card is sent out
The time stamp beaten when sending Delay_Req frame, T4 is to beat during master control board card reception Delay_Req frame
Time stamp, T4 ' is line card time stamp of beating when receiving Delay_Req frame；
Delay_Resp frame sending module is used for: according to the Delay_Resp frame phase of CPU configuration
Related parameter and the part field extracted from Delay_Req frame complete packet framing and transmission；
Announce frame sending module is used for: be correlated with according to the Announce frame of CPU configuration
Parameter completes packet framing and transmission；
Sync frame receiver module is used for: according to CPU configuration from port numbers Slave_port_num
The channel number Channel_ID corresponding with PTP message, identifies Slave from the data stream of input
The Sync frame that port receives, generates Sync frame and receives time stamp T2, and disappear from the PTP received
Breath extracts time stamp T1, T2` and CF territory, then reports T1, T2 time stamp and master to CPU
Clock is to the total CF territory from clockwise: T1`-T1+T2-T2`, and wherein, T1 is master control
The time stamp beaten when board sends Sync message, T1` be line card beat when sending Sync message time
Stamp, T2 is the time stamp beaten during master control board card reception Sync message, and T2` is that line card receives Sync
The time stamp beaten during message；
Delay_Req frame receiver module is used for: according to Slave_port_num and Channel_ID,
From the data stream of input, identify the Delay_Req message that Master port receives, generate
The reception time stamp T4 of Delay_Req message, and extraction please from the Delay_Req message received
Ask port-mark, T4` and CF territory, then by request port-mark, T4 and total CF territory:
T4-T4`+T3`-T3, output sends out frame module to Delay_Resp；
Delay_Resp frame receiver module is used for: according to Slave_port_num and
Channel_ID, identifies the Delay_Resp frame that Slave port receives from the data stream of input,
And from the Delay_Resp frame received, extract claim frame serial number, time stamp T4 and revise territory
CF；Then by receive claim frame serial number and caching in from Delay_Req sending module
Claim frame serial number compare, if both values are equal, then to CPU report T3,
T4 time stamp and total CF territory: T4-T4`+T3-T3`；If the claim frame serial number received
Value is relatively big, then continue to take transmission claim frame serial number from caching, until both values are equal,
Then T3, T4 time stamp and T4-T4`+T3-T3` are reported to CPU；If the claim frame received
The value of serial number is less, the most again receives Delay_Resp message；
Announce frame receiver module is used for: turned by the message of each passage according to Channel_ID
Deposit into corresponding memory space in dual port RAM, read for CPU；
Multiplexing module is used for: by Sync, Delay_Req, Delay_Resp of each passage and
Announce message is first multiplexed into a road, is then packaged by 1588 frame payload forms,
It is packaged by the Ethernet encapsulation format of band VLAN afterwards；
Demultiplexing module is used for: to 1588 frames received, first according to the ether of band VLAN
Net encapsulation format carries out 1588 frame decapsulations, obtains 1588 frame payloads, then to PTP Packet
Decapsulate, obtain PTP message frame；
Frame monitoring module is used for: select one from 1588 frames transmitted/received according to the configuration of depositor
Road carries out packet capturing operation, counts all kinds of messages that transmit/receive simultaneously.
On the basis of technique scheme, the described mark that sends is sent out with serial number generation module
The process sending mark is: within 1 second, will be divided into the time slot of 256 3.91ms with reference to PPS_IN signal,
If the frame number that the Sync frame that N1 is certain passage is per second, N1=1/2,1,2,4,8,
16,32,64,128,256, first time slot in certain is 1 second sends out frame, is then spaced
The time slot of 256/N 3.91ms sends out next frame；If N2 is certain passage
What Delay_Req/Announce frame was per second sends out frame number, and Delay_Req/Announce is 1588v2
A kind of message packet reciprocally negotiated between the master-salve clock of protocol definition, N2=1/16,1/8/,
1/4,1/2,1,2,4,8,16, first time slot in certain is 1 second sends out frame, then between
Time slot every 256/N 3.91ms sends out next frame, the maximum simultaneously supported according to master control board card
PTP port number 128, does segmentation further to the time slot of each 3.91ms, each segmentation
The corresponding PTP passage of the time slot of 30.52us, for transmitting the corresponding PTP message of this passage；
The 128th the clock cycle output Sync frame at each segmentation time slot sends mark, the
128+512 clock cycle output Delay_Req/Delay_Resp sends mark, the
128+1024 clock cycle output Announce frame sends mark.
On the basis of technique scheme, the described mark that sends is sent out with serial number generation module
The process sending serial number is: according to the transmission mark of Sync/Delay_Req/Announce frame and
PTP passage indication signal, produces time-multiplexed Sync/Delay_Req/Announce frame
Transmit Sequence Number；
On the basis of technique scheme, described Sync frame sending module is joined according to CPU
It is as follows with the process of transmission that the Sync frame relevant parameter put completes packet framing: first basis
Higher level sends mark and the enabling signal of serial number generation module offer, generates one and sends counting
Device；Then according to value delta frame beginning flag, content frame and the data valid signal of enumerator,
Last delta frame end signal after framing completes.
On the basis of technique scheme, described Delay_Req frame sending module according to
The Delay_Req frame relevant parameter of CPU configuration completes the concrete mistake of packet framing and transmission
Journey is as follows: first send mark and the enabling signal of serial number generation module offer according to higher level,
Generate a transmitting counter；Then according to value delta frame beginning flag, the content frame of enumerator
And data valid signal, finally delta frame end signal after framing completes.
On the basis of technique scheme, described Delay_Resp frame sending module according to
CPU configuration Delay_Resp frame relevant parameter and from Delay_Req frame extract part
It is as follows with the detailed process of transmission that field completes packet framing: first sends mark according to higher level
The enabling signal provided with serial number generation module and Delay_Req receive indication signal, generate
Delay_Resp frame sends initial signal, and joins counter initialization, according to Delay_Resp
The length of frame safeguards enumerator；Then change delta frame content and data according to enumerator are effective
Signal, finally delta frame end signal after framing completes.
On the basis of technique scheme, described Announce frame sending module is according to CPU
The Announce frame relevant parameter of configuration completes the detailed process of packet framing and transmission such as
Under: first send mark and the enabling signal of serial number generation module offer according to higher level, generate
One transmitting counter；Then according to value delta frame beginning flag, the content frame sum of enumerator
According to useful signal, finally delta frame end signal after framing completes.
On the basis of technique scheme, front 14 bytes of described 1588 frame payloads are
Extended head, is respectively used for transmitting the 1588 frame signal flow directions, PTP channel number, loaded length
And time stamp, load, the byte number of extended head is adjusted as required.
On the basis of technique scheme, described PTP message frame is by the PTP message of standard
Frame adds extended head composition, and the extended head of extended head and 1588 frame payloads is consistent.
Compared with prior art, advantages of the present invention is as follows:
(1) present invention is according to practical application request, at most provides 128 PTP ports, its
In a port be slave port, remaining port is master port；Use the time-division multiple
Mode carry out the transmission of PTP message, 1 second is divided into 256 time periods, Mei Geshi
Between section be separated into 128 time periods, thus can easily realizing the PTP of 128 ports
Message sends, and PTP message transmission frequency, up to 256 times per second, meets 1588V2 specification；
The parameter of each passage can be with separate configurations, it is simple to different application pattern or different encapsulation format
1588 port interconnected.The present invention possesses centralized PTP message processing capability, it is possible to effectively
Reduce communication network device development cost, it is possible to provide PTP flexibly for concrete application scenarios
The processing scheme of message, it is adaptable to the multiple communication network such as PTN, IPRAN and POTN sets
Standby.
(2) present invention provides Sync on master control board card (Sync is 1588v2 protocol definition
A kind of sync message for Frequency Synchronization) the transmission time stamp T1 of message, Sync on master control board card
On the reception time stamp T2 of message, master control board card, (Delay_Req is 1588v2 to Delay_Req
A kind of time-delay calculation request message calculated for chain-circuit time delay of protocol definition) transmission of message
On time stamp T3 and master control board card the reception time stamp T4 of Delay_Req message report interface,
Directly report the time stamp matched and the CF calculated (Correction Field revises territory) territory
Etc. information, it is simple to computed in software circuit delay.
(3) present invention provides abundant performance statistics depositor and the internal each node of FPGA to grab
Packet function.
Accompanying drawing explanation
Fig. 1 is the processing system of multiport PTP message in the embodiment of the present invention
(PTP_Engine) allomeric function block diagram.
Fig. 2 is the schematic diagram that in the embodiment of the present invention, PTP message time division multiplex sends.
Fig. 3 is T1, T2 time stamp and the process chart in CF territory in the embodiment of the present invention.
Fig. 4 is T3, T4 time stamp and the process chart in CF territory in the embodiment of the present invention.
Fig. 5 is that the form of CCU in the embodiment of the present invention (master control) board 1588 frame payload shows
It is intended to.
Fig. 6 is CCU board 1588 frame format schematic diagram in the embodiment of the present invention.
Fig. 7 is the form schematic diagram of CCU board PTP message frame in the embodiment of the present invention.
Detailed description of the invention
Below in conjunction with the accompanying drawings and specific embodiment the present invention is described in further detail.
The embodiment of the present invention is applied to communication network device so that it is support 1588 functions.Propping up
When holding 1588 function, current embodiment require that and software and other 1588 related functional components, example
As: 1PPS (Pulse per Second, pulse per second (PPS))+TOD (Time of Day, Time of Day)
Interface, the synthetic operation such as synchronous ethernet.
Shown in Figure 1, the embodiment of the present invention provides the process of a kind of multiport PTP message
System, this system includes cpu i/f module (CPU_IF), real-time time generation module
(REALTIME_GEN), send mark and serial number generation module (ST_SID_GEN),
Sync frame sending module, Delay_Req frame sending module, Delay_Resp frame sending module,
Announce frame sending module, Sync frame receiver module, Delay_Req frame receiver module,
Delay_Resp frame receiver module, Announce frame receiver module, Multiplexing module, demultiplexing
Module, frame monitoring module, wherein:
Sync is a kind of sync message for Frequency Synchronization of 1588v2 protocol definition；
Delay_Req is a kind of time delay calculated for chain-circuit time delay of 1588v2 protocol definition
Computation requests message；
Delay_Resp is a kind of time delay calculated for chain-circuit time delay of 1588v2 protocol definition
Calculate response message；
Announce be 1588v2 protocol definition a kind of master-salve clock between reciprocally negotiate disappear
Breath message；
Cpu i/f module (CPU_IF:CPU interface, cpu i/f) is used for: to
Need the variable distribution register address of configuration, it is achieved readable/writeable depositor；Give and need to read
The variable taken or constant distribution register address, it is achieved read-only register；Connect to possessing CPU
Other submodules chip selection signal of offer of mouth and data input/output interface, wherein 128
The configuration register of PTP passage use BRAM (Block Random Access Memory,
Block storage) realize, and by sending mark and serial number generation module (ST_SID_GEN)
The PTP passage indication signal read-out channel in a time multiplexed manner configuration data generated；
Real-time time generation module (REALTIME_GEN) is used for: according to the second arteries and veins of input
The second value rushing signal (PPS_IN) and CPU configuration generates real-time time, has at PPS_IN
The when of effect, sampling TOD_TIME is as time second, and nanoseconds is zero, the most often comes one
The rising edge of individual clock, nanoseconds adds 8；
Send mark and serial number generation module (ST_SID_GEN) is used for: to each passage
All kinds of PTP messages provide send mark and transmit Sequence Number, send mark process be:
The time slot of 256 3.91ms within 1 second, will be divided into reference to PPS_IN signal, lead to if N1 is certain
What the Sync frame in road was per second send out frame number, N1=1/2,1,2,4,8,16,32,64,128,
256, first time slot in certain is 1 second sends out frame, then interval 256/N 3.91ms time
Gap sends out next frame；If what the Delay_Req/Announce frame that N2 is certain passage was per second sends out frame
Number, N2=1/16,1/8/, 1/4,1/2,1,2,4,8,16, first in certain is 1 second
Individual time slot sends out frame, and then the time slot of 256/N the 3.91ms in interval sends out next frame, basis simultaneously
The maximum PTP port number 128 that master control board card is supported, does into one the time slot of each 3.91ms
Step segmentation, the corresponding PTP passage of the time slot of the 30.52us of each segmentation, it is used for transmitting this
The corresponding PTP message of passage；Can be defeated in the 128th clock cycle of each segmentation time slot
Going out Sync frame and send mark, the 128+512 clock cycle can export
Delay_Req/Delay_Resp sends mark, and the 128+1024 clock cycle is exportable
Announce frame sends mark；Shown in Figure 2, produce PTP frame and send the basic of mark
Enabling signal, PTP frame to be produced sends mark and also needs to meet other conditions；Send sequence
Number process be: according to transmission mark and the PTP of Sync/Delay_Req/Announce frame
Passage indication signal, produces the transmission of time-multiplexed Sync/Delay_Req/Announce frame
Serial number；
Sync frame sending module is used for: complete according to the Sync frame relevant parameter of CPU configuration
Packet framing and transmission, detailed process is as follows: first send mark and serial number according to higher level
The enabling signal that generation module provides, generates a transmitting counter；Then according to enumerator
Value delta frame beginning flag, content frame and data valid signal, finally generate after framing completes
Frame end signal；
Delay_Req frame sending module is used for: according to the Delay_Req frame phase of CPU configuration
Related parameter completes packet framing and transmission, and detailed process is as follows: first send mark according to higher level
The enabling signal that will and serial number generation module provide, generates a transmitting counter；Then root
According to value delta frame beginning flag, content frame and the data valid signal of enumerator, finally at framing
Delta frame end signal after completing；Delay_Req frame sending module also receives to Delay_Req
When module provides Delay_Req frame transmit Sequence Number (claim frame serial number) and send accordingly
Stamp T3, T4 time stamp and the total CF territory from clock to master clock direction: T4-T4`+T3-T3`,
It is easy to Slave port and reports T3；Wherein, when T3 is master control board card transmission Delay_Req frame
The time stamp beaten, T3 ' is the time stamp beaten during line card transmission Delay_Req frame, and T4 is master control borad
The time stamp that card is beaten when receiving Delay_Req frame, T4 ' is to beat during line card reception Delay_Req frame
Time stamp；
Delay_Resp frame sending module is used for: according to the Delay_Resp frame phase of CPU configuration
Related parameter and the part field extracted from Delay_Req frame complete packet framing and transmission,
Detailed process is as follows: first send mark and the startup of serial number generation module offer according to higher level
Signal and Delay_Req receive indication signal, generate Delay_Resp frame and send initial signal,
And join counter initialization, safeguard enumerator according to the length of Delay_Resp frame；Then root
According to change delta frame content and the data valid signal of enumerator, finally generate after framing completes
Frame end signal.
Announce frame sending module is used for: be correlated with according to the Announce frame of CPU configuration
Parameter completes packet framing and transmission, and detailed process is as follows: first send mark according to higher level
The enabling signal provided with serial number generation module, generates a transmitting counter；Then basis
Value delta frame beginning flag, content frame and the data valid signal of enumerator, finally complete at framing
Delta frame end signal after one-tenth；
Sync frame receiver module is used for: according to Slave_port_num (CPU configuration from end
Slogan) with Channel_ID (channel number that PTP message is corresponding), from input data stream
Identify the Sync frame that Slave port receives, generate Sync frame and receive time stamp T2, and from reception
PTP message in extract time stamp T1, T2` and CF territory, then report T1, T2 to CPU
Time stamp and master clock are to the total CF territory from clockwise: T1`-T1+T2-T2`, wherein,
T1 is the time stamp beaten during master control board card transmission Sync message, and T1` is that line card sends Sync message
Time the time stamp beaten, T2 is the time stamp that master control board card is beaten when receiving Sync message, and T2` is line card
The time stamp beaten when receiving Sync message, shown in Figure 3；
Delay_Req frame receiver module is used for: according to Slave_port_num and Channel_ID,
From the data stream of input, identify the Delay_Req message that Master port receives, generate
The reception time stamp T4 of Delay_Req message, and extraction please from the Delay_Req message received
Ask port-mark, T4` and CF territory, then by request port-mark, T4 and total CF territory:
T4-T4`+T3`-T3, output sends out frame module to Delay_Resp, shown in Figure 4；
Delay_Resp frame receiver module is used for: according to Slave_port_num and
Channel_ID, identifies the Delay_Resp frame that Slave port receives from the data stream of input,
And from the Delay_Resp frame received, extract claim frame serial number, time stamp T4 and revise territory
CF；Then by receive claim frame serial number and caching in from Delay_Req sending module
Claim frame serial number compare, if both values are equal, then to CPU report T3,
T4 time stamp and total CF territory: T4-T4`+T3-T3`；If the claim frame serial number received
Value is relatively big, then mean that the Delay_Req frame that Slave port sends has loss, can continue
Transmission claim frame serial number is taken, until both values are equal, then on CPU from caching
Report T3, T4 time stamp and T4-T4`+T3-T3`；If the value of the claim frame serial number received is relatively
Little, then mean that link delay is too big, and receive the transmission claim frame that claim frame serial number is equal
Serial number reads from caching, needs again to receive Delay_Resp message；
Announce frame receiver module is used for: turned by the message of each passage according to Channel_ID
Deposit into corresponding memory space in dual port RAM, read for CPU；
MUX module (Multiplexing module) is used for: by the Sync of each passage, Delay_Req,
Delay_Resp and Announce message is first multiplexed into a road, 1588 the most as shown in Figure 5
Frame payload form is packaged: front 14 bytes of 1588 frame payloads are extended head, respectively
For transmitting the 1588 frame signal flow directions, PTP channel number, loaded length and time stamp, load,
The byte number of extended head can be adjusted as required；Last band as shown in Figure 6
The Ethernet encapsulation format of VLAN is packaged；
DEMUX module (demultiplexing module) is used for: to 1588 frames received, first root
Carry out 1588 frame decapsulations according to the Ethernet encapsulation format of the band VLAN shown in Fig. 6, obtain
1588 frame payloads shown in Fig. 5, then decapsulate PTP Packet, obtain such as figure
PTP message frame shown in 7, PTP message frame is added extended head by the PTP message frame of standard
Composition, the extended head of extended head and 1588 frame payloads is consistent；
MONITOR module (frame monitoring module) is used for: according to the configuration of depositor from receiving/
1588 frames sent out select a road to carry out packet capturing operation, all kinds of messages that transmit/receive is counted simultaneously
Number.
Those skilled in the art can carry out various modifications and variations to the embodiment of the present invention, if
If these amendment and modification within the scope of the claims in the present invention and equivalent technologies thereof, then this
A little amendments and modification are also within protection scope of the present invention.
The prior art that the content not described in detail in description is known to the skilled person.
Claims (9)
1. the processing system of a multiport PTP message, it is characterized in that, this system includes cpu i/f module, real-time time generation module, sends mark and serial number generation module, Sync frame sending module, Delay_Req frame sending module, Delay_Resp frame sending module, Announce frame sending module, Sync frame receiver module, Delay_Req frame receiver module, Delay_Resp frame receiver module, Announce frame receiver module, Multiplexing module, demultiplexing module, frame monitoring module, wherein:
Sync is a kind of sync message for Frequency Synchronization of 1588v2 protocol definition；
Delay_Req is a kind of time-delay calculation request message calculated for chain-circuit time delay of 1588v2 protocol definition；
Delay_Resp is a kind of time-delay calculation response message calculated for chain-circuit time delay of 1588v2 protocol definition；
Announce is the message packet reciprocally negotiated between a kind of master-salve clock of 1588v2 protocol definition；
Cpu i/f module is used for: give the variable distribution register address needing configuration, it is achieved readable/writeable depositor；Give the variable needing to read or constant distribution register address, it is achieved read-only register；There is provided sub-chip selection signal and data input/output interface to other submodules possessing cpu i/f, wherein the configuration register of 128 Precision Time Protocol PTP passages uses block storage to realize, and the PTP passage indication signal read-out channel in a time multiplexed manner configuration data generated by transmission mark and serial number generation module；
Real-time time generation module is used for: generate real-time time according to the second value of pps pulse per second signal PPS_IN and the CPU configuration of input, sample Time of Day TOD_TIME as time second when PPS_IN is effective, nanoseconds is zero, the most often carrys out the rising edge of a clock, and nanoseconds adds 8；
Sending mark to be used for serial number generation module: provide to all kinds of PTP messages of each passage and send mark and transmit Sequence Number, produce PTP frame transmission mark enables signal substantially；
Sync frame sending module is used for: complete packet framing and transmission according to the Sync frame relevant parameter of CPU configuration；
Delay_Req frame sending module is used for: complete packet framing and transmission according to the Delay_Req frame relevant parameter of CPU configuration；Delay_Req frame sending module also provides Delay_Req frame to transmit Sequence Number to Delay_Req receiver module and sends time stamp T3, T4 time stamp and the total CF territory from clock to master clock direction: T4-T4`+T3-T3` accordingly, wherein, T3 is the time stamp beaten during master control board card transmission Delay_Req frame, T3 ' is the time stamp beaten during line card transmission Delay_Req frame, T4 is the time stamp beaten during master control board card reception Delay_Req frame, and T4 ' is the time stamp beaten during line card reception Delay_Req frame；
Delay_Resp frame sending module is used for: complete packet framing and transmission according to the Delay_Resp frame relevant parameter of CPU configuration and the part field extracted from Delay_Req frame；
Announce frame sending module is used for: complete packet framing and transmission according to the Announce frame relevant parameter of CPU configuration；
nullSync frame receiver module is used for: according to the channel number Channel_ID corresponding with PTP message from port numbers Slave_port_num of CPU configuration，The Sync frame that Slave port receives is identified from the data stream of input，Generate Sync frame and receive time stamp T2，And from the PTP message received, extract time stamp T1、T2` and CF territory，Then T1 is reported to CPU，T2 time stamp and master clock are to the total CF territory from clockwise: T1`-T1+T2-T2`，Wherein，T1 is the time stamp beaten during master control board card transmission Sync message，T1` is the time stamp beaten during line card transmission Sync message，T2 is the time stamp beaten during master control board card reception Sync message，T2` is the time stamp beaten during line card reception Sync message；
Delay_Req frame receiver module is used for: according to Slave_port_num and Channel_ID, the Delay_Req message that Master port receives is identified from the data stream of input, generate the reception time stamp T4 of Delay_Req message, and from the Delay_Req message received, extract request port-mark, T4` and CF territory, then by request port-mark, T4 and total CF territory: T4-T4`+T3`-T3, output sends out frame module to Delay_Resp；
Delay_Resp frame receiver module is used for: according to Slave_port_num and Channel_ID, from the data stream of input, identify the Delay_Resp frame that Slave port receives, and from the Delay_Resp frame received, extract claim frame serial number, time stamp T4 and revise territory CF；Then by the claim frame serial number of reception and caching compare from the claim frame serial number of Delay_Req sending module, if both values are equal, then T3, T4 time stamp and total CF territory: T4-T4`+T3-T3` are reported to CPU；If the value of the claim frame serial number received is relatively big, then continues from caching, take transmission claim frame serial number, until both values are equal, then report T3, T4 time stamp and T4-T4`+T3-T3` to CPU；If the value of the claim frame serial number received is less, the most again receive Delay_Resp message；
Announce frame receiver module is used for: according to Channel_ID, the message unloading of each passage is entered corresponding memory space in dual port RAM, reads for CPU；
Multiplexing module is used for: Sync, Delay_Req, Delay_Resp and Announce message of each passage is first multiplexed into a road, is then packaged by 1588 frame payload forms, be finally packaged by the Ethernet encapsulation format of band VLAN；
Demultiplexing module is used for: to 1588 frames received, and first carries out 1588 frame decapsulations according to the Ethernet encapsulation format of band VLAN, obtains 1588 frame payloads, then decapsulate PTP Packet, obtain PTP message frame；
Frame monitoring module is used for: selects a road to carry out packet capturing operation from 1588 frames transmitted/received according to the configuration of depositor, counts all kinds of messages that transmit/receive simultaneously.
2. the processing system of multiport PTP message as claimed in claim 1, it is characterised in that: described transmission indicates that the process with serial number generation module transmission mark is: within 1 second, will be divided into the time slot of 256 3.91ms with reference to PPS_IN signal, if the frame number that the Sync frame that N1 is certain passage is per second, N1=1/2,1,2,4,8,16,32,64,128,256, first time slot in certain is 1 second sends out frame, and then the time slot of 256/N the 3.91ms in interval sends out next frame；If what the Delay_Req/Announce frame that N2 is certain passage was per second sends out frame number, Delay_Req/Announce is the message packet reciprocally negotiated between a kind of master-salve clock of 1588v2 protocol definition, N2=1/16, 1/8/, 1/4, 1/2, 1, 2, 4, 8, 16, first time slot in certain is 1 second sends out frame, then the time slot of 256/N the 3.91ms in interval sends out next frame, the maximum PTP port number 128 simultaneously supported according to master control board card, the time slot of each 3.91ms is done segmentation further, the corresponding PTP passage of the time slot of the 30.52us of each segmentation, for transmitting the corresponding PTP message of this passage；The 128th the clock cycle output Sync frame at each segmentation time slot sends mark, and the 128+512 clock cycle output Delay_Req/Delay_Resp sends mark, and the 128+1024 clock cycle output Announce frame sends mark.
3. the processing system of multiport PTP message as claimed in claim 1, it is characterized in that: described transmission indicates that the process transmitted Sequence Number with serial number generation module is: according to transmission mark and the PTP passage indication signal of Sync/Delay_Req/Announce frame, produce transmitting Sequence Number of time-multiplexed Sync/Delay_Req/Announce frame.
4. the processing system of multiport PTP message as claimed in claim 1, it is characterized in that: it is as follows with the process of transmission that described Sync frame sending module completes packet framing according to the Sync frame relevant parameter that CPU configures: first send mark and the enabling signal of serial number generation module offer according to higher level, generate a transmitting counter；Then according to value delta frame beginning flag, content frame and the data valid signal of enumerator, finally delta frame end signal after framing completes.
5. the processing system of multiport PTP message as claimed in claim 1, it is characterized in that: it is as follows with the detailed process of transmission that described Delay_Req frame sending module completes packet framing according to the Delay_Req frame relevant parameter that CPU configures: first send mark and the enabling signal of serial number generation module offer according to higher level, generate a transmitting counter；Then according to value delta frame beginning flag, content frame and the data valid signal of enumerator, finally delta frame end signal after framing completes.
6. the processing system of multiport PTP message as claimed in claim 1, it is characterized in that: it is as follows with the detailed process of transmission that Delay_Resp frame relevant parameter that described Delay_Resp frame sending module configures according to CPU and the part field extracted from Delay_Req frame complete packet framing: first send mark and the enabling signal of serial number generation module offer and Delay_Req reception indication signal according to higher level, generate Delay_Resp frame and send initial signal, and join counter initialization, safeguard enumerator according to the length of Delay_Resp frame；Then according to change delta frame content and the data valid signal of enumerator, finally delta frame end signal after framing completes.
7. the processing system of multiport PTP message as claimed in claim 1, it is characterized in that: it is as follows with the detailed process of transmission that described Announce frame sending module completes packet framing according to the Announce frame relevant parameter that CPU configures: first send mark and the enabling signal of serial number generation module offer according to higher level, generate a transmitting counter；Then according to value delta frame beginning flag, content frame and the data valid signal of enumerator, finally delta frame end signal after framing completes.
8. the processing system of multiport PTP message as claimed in claim 1, it is characterized in that: front 14 bytes of described 1588 frame payloads are extended head, it is respectively used for transmitting the 1588 frame signal flow directions, PTP channel number, loaded length and time stamp, load, the byte number of extended head is adjusted as required.
9. the processing system of multiport PTP message as claimed in claim 1, it is characterised in that: described PTP message frame is added extended head by the PTP message frame of standard and forms, and the extended head of extended head and 1588 frame payloads is consistent.
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