CN107688551A - Data interaction control method and system between primary processor and coprocessor - Google Patents
Data interaction control method and system between primary processor and coprocessor Download PDFInfo
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- CN107688551A CN107688551A CN201611208202.0A CN201611208202A CN107688551A CN 107688551 A CN107688551 A CN 107688551A CN 201611208202 A CN201611208202 A CN 201611208202A CN 107688551 A CN107688551 A CN 107688551A
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- primary processor
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- coprocessor
- data interaction
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/167—Interprocessor communication using a common memory, e.g. mailbox
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
- G06F13/1663—Access to shared memory
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- General Engineering & Computer Science (AREA)
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Abstract
The invention discloses the data interaction control method between a kind of primary processor and coprocessor and system, this method comprises the following steps：One or more clusters are established, wherein, each cluster includes the related primary processor of processing function and multiple coprocessors；For the corresponding shared storage of one or more of cluster configurations；Primary processor and multiple coprocessors in one or more of clusters is controlled to be stored in row data interaction with corresponding described share.The present invention does not need the process of middle write-in internal memory, saves substantial amounts of data transmission period, while improve processing speed and running efficiency of system.
Description
Technical field
The present invention relates to communication technique field, the data interaction control between more particularly to a kind of primary processor and coprocessor
Method and system processed.
Background technology
In the processor system of processing complex transaction, multiple processors and multiple coprocessors often be present, at association
Manage device and be responsible for specific association's processing function.Coprocessor is when performing its specific association's processing function, between multiple coprocessors
Shared and data the transmission of resource is needed, between coprocessor and control processor corresponding to it, also may require that being total to for resource
Enjoy the interaction with result.When producing data correlation in calculating affairs, it is necessary to realize that data relay operates by internal memory, often
Secondary that result of calculation is write into internal memory after calculating terminates, the latter coprocessor initiates reading source behaviour before calculating starts to internal memory
The application counted.Thus cause to calculate the processing being required for by multi-level bus each time.
The shortcomings that prior art be present and it is that processor and each data interaction of coprocessor are required for by interior
Deposit realization.Because the reading speed of internal memory is very slow, writing speed is slower, and internal memory also has Refresh Data cycle etc. and asked in itself
Topic, causes the time overhead of data transfer very big.And internal memory application each time, it is required for by system bus, is calculating thing
When the data volume of business is larger, the bandwidth of system bus can be caused to increase sharply, processing speed will be by the shadow of system bus disposal ability
Ring, if carrying out the processing of other control affairs in system simultaneously, the competition of bus can not only influence to calculate the speed of affairs, can also
Operation to system impacts.
The content of the invention
It is contemplated that at least solves one of technical problem in above-mentioned correlation technique to a certain extent.
Therefore, it is an object of the present invention to propose that the data interaction between a kind of primary processor and coprocessor controls
Method.Data interaction control method between the primary processor and coprocessor does not need the process of middle write-in internal memory, saves
Substantial amounts of data transmission period, while improve processing speed and running efficiency of system.
It is another object of the present invention to the data interaction proposed between a kind of primary processor and coprocessor to control system
System.
To achieve these goals, an aspect of of the present present invention discloses the data between a kind of primary processor and coprocessor
Interaction control method, methods described following steps：One or more clusters are established, wherein, each cluster includes processing function phase
The primary processor of pass and multiple coprocessors；Storage is shared correspondingly for one or more of cluster configurations；Control institute
State primary processor and multiple coprocessors in one or more clusters and be stored in row data interaction with corresponding described share.
According to the data interaction control method between the primary processor and coprocessor of the present invention, carried out using shared storage
The interworking of data, the intermediate processing results of primary processor and multiple coprocessors need not can again be carried out to the write-in of internal memory
And readout, the substantial amounts of time is saved, further, data in the cluster do not need the processing of uniformity, save
Time, meanwhile, also without the distribution of system bus, transmission speed will not influenceed by system bus bandwidth, and can be kept away
Exempt to compete with other processing affairs in bus, influence system operation.
In addition, the data interaction control method between primary processor according to the above embodiment of the present invention and coprocessor is also
There can be technical characteristic additional as follows：
Further, in addition to：Ensure the uniformity of the data of the primary processor in one or more of clusters.
Further, in addition to：The data handled in one or more of clusters are preserved into internal memory.
Further, the data handled in the cluster include primary data, last result and interim processing
As a result.
Another aspect of the present invention discloses the data interaction control system between a kind of primary processor and coprocessor, institute
The system of stating includes：One or more clusters, wherein, each cluster includes the related primary processor of processing function and the processing of multiple associations
Device；The shared storage of one or more, wherein, it is the one-to-one shared storage of one or more of cluster configurations；One
Individual or multiple control modules, each control module is connected with the cluster and corresponding shared storage respectively, for controlling
Primary processor and multiple coprocessors are stored in row data interaction with corresponding described share in the cluster.
According to the data interaction control system between the primary processor and coprocessor of the present invention, carried out using shared storage
The interworking of data, the intermediate processing results of primary processor and multiple coprocessors need not can again be carried out to the write-in of internal memory
And readout, the substantial amounts of time is saved, further, data in the cluster do not need the processing of uniformity, save
Time, meanwhile, also without the distribution of system bus, transmission speed will not influenceed by system bus bandwidth, and can be kept away
Exempt to compete with other processing affairs in bus, influence system operation.
In addition, the data interaction control system between primary processor according to the above embodiment of the present invention and coprocessor is also
There can be technical characteristic additional as follows：
Further, in addition to：Uniformity bus between processor, from the primary processor phase in the different clusters
Even, the uniformity of the data for ensureing the primary processor in one or more of clusters.
Further, in addition to：System bus, uniformity bus is connected between the primary processor, for the main place
Manage device and control the multiple coprocessor.
Further, in addition to：Internal memory, the internal memory are connected with the system bus, for will be one or more of
The data handled in cluster are preserved into internal memory.
Further, the data handled in the cluster include primary data, last result and interim processing
As a result.
The additional aspect and advantage of the present invention will be set forth in part in the description, and will partly become from the following description
Obtain substantially, or recognized by the practice of the present invention.
Brief description of the drawings
The above-mentioned and/or additional aspect and advantage of the present invention will become in the description from combination accompanying drawings below to embodiment
Substantially and it is readily appreciated that, wherein：
Fig. 1 is the data interaction control method between primary processor and coprocessor according to an embodiment of the invention
Flow chart；
Fig. 2 is the data interaction control method between primary processor and coprocessor in accordance with another embodiment of the present invention
Flow chart；
Fig. 3 is the flow chart of multiple cluster intermediate data interactions according to an embodiment of the invention；And
Fig. 4 is the data interaction control system between primary processor and coprocessor according to an embodiment of the invention
Structure chart.
Embodiment
Embodiments of the invention are described below in detail, the example of the embodiment is shown in the drawings, wherein from beginning to end
Same or similar label represents same or similar element or the element with same or like function.Below with reference to attached
The embodiment of figure description is exemplary, is only used for explaining the present invention, and is not considered as limiting the invention.
Data interaction control between primary processor and coprocessor according to embodiments of the present invention is described below in conjunction with accompanying drawing
Method and system processed.
Fig. 1 is the data interaction control method between primary processor and coprocessor according to an embodiment of the invention
Flow chart.
As shown in figure 1, the data interaction control between primary processor according to an embodiment of the invention and coprocessor
Method, comprise the following steps：
S110：One or more clusters are established, wherein, each cluster includes the related primary processor of processing function and multiple
Coprocessor.
Wherein, the related primary processor of processing function and multiple coprocessors refer to that primary processor and multiple coprocessors exist
It is related to produce data.The related primary processor of data will be produced and multiple coprocessors establish a cluster, to facilitate to data
Shared.
S120：For the corresponding shared storage of one or more cluster configurations.
Specifically, the shared and intermediate processing results of resource are needed between primary processor and coprocessor in the cluster
Interaction, by these in the cluster between data a shared storage is separately configured, complete the transfer behaviour of data within the system
Make.
S130：Primary processor and multiple coprocessors in one or more clusters is controlled to be stored in line number with corresponding share
According to interaction.
As shown in Fig. 2 cluster includes primary processor 1, coprocessor 1 and 2, storage 1 and shared system controller 1 are shared.
For the cluster when processing calculates affairs, it is necessary to which multiple coprocessors cooperate, primary processor 1 writes initial calculation data altogether
Storage 1 is enjoyed, coprocessor 1 obtains data from shared storage 1, and coprocessor 1 is after the completion of issued transaction is calculated, by calculating
The shared storage 1 of intermediate result write-in, coprocessor 2 obtain data from shared storage 1, and coprocessor 2 is calculating issued transaction
After the completion of, interim result of calculation is write and shares storage 1, primary processor 1 obtains interim calculating knot from shared storage 1
Fruit, continue follow-up work.
Further, in addition to：Ensure the uniformity of the data of the primary processor in one or more clusters, by one or
The data handled in multiple clusters are preserved into internal memory, wherein, the data in internal memory include primary data, last result
With interim result, interim result refers to the data that can be needed by other clusters.With reference to shown in Fig. 3, the He of cluster 1
The being consistent property of data of primary processor between cluster 2, by the uniformity bus between processor, and primary processor passes through system
Multiple coprocessors in the cluster of the bus marco primary processor, and the result of primary processor and coprocessor is led to
The communication that system bus with internal memory read still write-in is crossed, wherein, a shared storage is only the master in corresponding cluster
Processor and coprocessor work, it is not relevant between multiple shared storages.
It is worth noting that, primary processor and coprocessor count all with being stored to shared all with two-way read-write capability
Do not fix according to flow direction between the host processor and the coprocessor, determined by the processing procedure in specific affairs.
Data interaction control method between treatment in accordance with the present invention device and coprocessor, line number is stored in using shared
According to interworking, the intermediate processing results of primary processor and multiple coprocessors can need not be carried out again internal memory write-in and
Readout, the substantial amounts of time is saved, further, data in the cluster do not need the processing of uniformity, when having saved
Between, meanwhile, also without the distribution of system bus, transmission speed will not influenceed by system bus bandwidth, and can be avoided
Competed with other processing affairs in bus, influence system operation.
Fig. 4 is the knot of the data interaction control system between processor and coprocessor according to an embodiment of the invention
Composition.
As shown in figure 4, the data interaction control system 400 between primary processor and coprocessor, system 400 include：Collection
Group 410, shared storage 420 and control module 430.
Wherein, cluster 410, wherein, each cluster includes the related primary processor of processing function and multiple coprocessors；Altogether
Storage 420 is enjoyed, for for the one-to-one shared storage of one or more cluster configurations；Control module 430, respectively with collection
Group 410 is connected with shared storage 420 is corresponded to therewith, for controlling primary processor and multiple coprocessors in one or more clusters
Row data interaction is stored in corresponding share.
Data interaction control system between treatment in accordance with the present invention device and coprocessor, line number is stored in using shared
According to interworking, the intermediate processing results of primary processor and multiple coprocessors can need not be carried out again internal memory write-in and
Readout, the substantial amounts of time is saved, further, data in the cluster do not need the processing of uniformity, when having saved
Between, meanwhile, also without the distribution of system bus, transmission speed will not influenceed by system bus bandwidth, and can be avoided
Competed with other processing affairs in bus, influence system operation.
In certain embodiments, the system 400 also includes：Uniformity bus between processor, and in the different clusters
The primary processor be connected, the uniformity of the data for ensureing the primary processor in one or more of clusters,
System bus, uniformity bus is connected between the primary processor, and the multiple coprocessor is controlled for the primary processor,
Further, in addition to：Internal memory, the internal memory are connected with the system bus, for will locate in one or more of clusters
The data of reason are preserved into internal memory.Wherein, the data handled in the cluster include primary data, last result and rank
Section property result.
It should be noted that data interaction control system between the primary processor and coprocessor of the embodiment of the present invention
The specific reality of data interaction control method between specific implementation and the primary processor and coprocessor of the embodiment of the present invention
Existing mode is similar, specifically refers to the description of method part, in order to reduce redundancy, does not repeat herein.
In addition, term " first ", " second " are only used for describing purpose, and it is not intended that instruction or hint relative importance
Or the implicit quantity for indicating indicated technical characteristic.Thus, define " first ", the feature of " second " can be expressed or
Implicitly include at least one this feature.In the description of the invention, " multiple " are meant that at least two, such as two, three
It is individual etc., unless otherwise specifically defined.
In the present invention, unless otherwise clearly defined and limited, term " installation ", " connected ", " connection ", " fixation " etc.
Term should be interpreted broadly, for example, it may be fixedly connected or be detachably connected, or integrally；Can be that machinery connects
Connect or electrically connect；Can be joined directly together, can also be indirectly connected by intermediary, can be in two elements
The connection in portion or the interaction relationship of two elements, limited unless otherwise clear and definite.For one of ordinary skill in the art
For, the concrete meaning of above-mentioned term in the present invention can be understood as the case may be.
In the description of this specification, reference term " one embodiment ", " some embodiments ", " example ", " specifically show
The description of example " or " some examples " etc. means specific features, structure, material or the spy for combining the embodiment or example description
Point is contained at least one embodiment or example of the present invention.In this manual, to the schematic representation of above-mentioned term not
Identical embodiment or example must be directed to.Moreover, specific features, structure, material or the feature of description can be with office
Combined in an appropriate manner in one or more embodiments or example.In addition, in the case of not conflicting, the skill of this area
Art personnel can be tied the different embodiments or example and the feature of different embodiments or example described in this specification
Close and combine.
Although embodiments of the invention have been shown and described above, it is to be understood that above-described embodiment is example
Property, it is impossible to limitation of the present invention is interpreted as, one of ordinary skill in the art within the scope of the invention can be to above-mentioned
Embodiment is changed, changed, replacing and modification.
Claims (9)
1. the data interaction control method between a kind of primary processor and coprocessor, it is characterised in that comprise the following steps：
One or more clusters are established, wherein, each cluster includes the related primary processor of processing function and multiple coprocessors；
For the corresponding shared storage of one or more of cluster configurations；
Primary processor and multiple coprocessors in one or more of clusters is controlled to be stored in line number with corresponding described share
According to interaction.
2. the data interaction control method between primary processor according to claim 1 and coprocessor, it is characterised in that
Also include：
Ensure the uniformity of the data of the primary processor in one or more of clusters.
3. the data interaction control method between primary processor according to claim 2 and coprocessor, it is characterised in that
Also include：
The data handled in one or more of clusters are preserved into internal memory.
4. the data interaction control method between primary processor and coprocessor according to right wants 3, it is characterised in that institute
The data stated in internal memory include primary data, last result and interim result.
A kind of 5. data interaction control system between primary processor and coprocessor, it is characterised in that including：
One or more clusters, wherein, each cluster includes the related primary processor of processing function and multiple coprocessors；
The shared storage of one or more, wherein, it is the one-to-one shared storage of one or more of cluster configurations；
One or more control modules, corresponding shared storage is connected each control module with the cluster and therewith respectively, is used for
Primary processor and multiple coprocessors in the cluster is controlled to be stored in row data interaction with corresponding described share.
6. the data interaction control system between primary processor according to claim 5 and coprocessor, it is characterised in that
Also include：
Uniformity bus between processor, it is connected from the primary processor in the different clusters, it is one for ensureing
Or the uniformity of the data of the primary processor in multiple clusters.
7. the data interaction control system between primary processor according to claim 6 and coprocessor, it is characterised in that
Also include：
System bus, uniformity bus is connected between the primary processor, is controlled for the primary processor at the multiple association
Manage device.
8. the data interaction control system between primary processor according to claim 7 and coprocessor, it is characterised in that
Also include：
Internal memory, the internal memory are connected with the system bus, and the data for will be handled in one or more of clusters preserve
Into internal memory.
9. the data interaction control system between primary processor according to claim 8 and coprocessor, it is characterised in that
Data in the internal memory include primary data, last result and interim result.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611208202.0A CN107688551A (en) | 2016-12-23 | 2016-12-23 | Data interaction control method and system between primary processor and coprocessor |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201611208202.0A CN107688551A (en) | 2016-12-23 | 2016-12-23 | Data interaction control method and system between primary processor and coprocessor |
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| CN107688551A true CN107688551A (en) | 2018-02-13 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109542830A (en) * | 2018-11-21 | 2019-03-29 | 北京灵汐科技有限公司 | A kind of data processing system and data processing method |
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| CN101114272A (en) * | 2007-01-22 | 2008-01-30 | 北京中星微电子有限公司 | Chip capable of realizing communications between multiple cores in chip and method for communication |
| US20090282211A1 (en) * | 2008-05-09 | 2009-11-12 | International Business Machines | Network On Chip With Partitions |
| CN102226895A (en) * | 2011-06-01 | 2011-10-26 | 展讯通信（上海）有限公司 | System with memorizer shared by coprocessor and master processor, and access method of system |
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2016
- 2016-12-23 CN CN201611208202.0A patent/CN107688551A/en not_active Withdrawn
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1601511A (en) * | 2003-09-25 | 2005-03-30 | 国际商业机器公司 | System and method for manipulating data with a plurality of processors |
| CN101114272A (en) * | 2007-01-22 | 2008-01-30 | 北京中星微电子有限公司 | Chip capable of realizing communications between multiple cores in chip and method for communication |
| US20090282211A1 (en) * | 2008-05-09 | 2009-11-12 | International Business Machines | Network On Chip With Partitions |
| CN102226895A (en) * | 2011-06-01 | 2011-10-26 | 展讯通信（上海）有限公司 | System with memorizer shared by coprocessor and master processor, and access method of system |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109542830A (en) * | 2018-11-21 | 2019-03-29 | 北京灵汐科技有限公司 | A kind of data processing system and data processing method |
| CN109542830B (en) * | 2018-11-21 | 2022-03-01 | 北京灵汐科技有限公司 | Data processing system and data processing method |
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