CN101114272A - Chip capable of realizing communications between multiple cores in chip and method for communication - Google Patents
Chip capable of realizing communications between multiple cores in chip and method for communication Download PDFInfo
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Abstract
The invention discloses a chip together with the communication method to realize the communication among a plurality of nucleus inside a chip, such as the communication between an ARM nuclear and a DSP nuclear, comprising the ARM nuclear, the DSP nuclear and a shared memory. The chip is internally provided with a shared memory to provide a buffer space for receiving the data, in particular to a shared channel for the data. The ARM nuclear and the DSP nuclear write the data on an address unit presupposed by the ARM nuclear and the DSP nuclear in the shared memory and notify the other party to read the data to do the receiving, sending and interaction of the data in the shared memory, so as to realize the communication mechanism of data sharing, data interaction and interruption and interaction between two nucleus with high reading-writing operation speed, short delayed time and strong real-time performance.
Description
Technical field
The present invention relates to the mobile radio terminal communication technology, between particularly a kind of multinuclear of realizing in the chip, the chip and the communication means of communication between particularly ARM nuclear and DSP examine.
Background technology
Along with developing rapidly of large scale integrated circuit technology and mobile communication technology, people are to intelligence instrument, test macro, the requirement that communication system and control system Real time signal are handled also improves constantly, to system's high-performance, two-forty, the requirement of low delay is also more and more urgent, based on senior reduced instruction set computer (ARM, Advanced RISC Machines) technology and digital signal processor (DSP, DigitalSignal Processor) chip system (SOC that gets up of technical development, System On Chip) technology can satisfy the requirement of people to real time signal processing preferably, satisfies in industry spot and various surveying instrument and the intelligence control system real-time to data, the communicating requirement of high efficiency.
In the SOC system, ARM nuclear is as primary processor, a series of kernels, system expansion, microprocessor and System on Chip/SoC scheme are provided, realization is to the management and the control of system transaction, DSP nuclear is as coprocessor, adopt Harvard's bus structure of strengthening, have powerful data-handling capacity and higher travelling speed, handle bulk information with digital signal, the operation of execution computation-intensive, finish signal Processing, analysis and information fusion, digital signal after will handling then and ARM nuclear communicate, again by management of ARM nuclear and control external unit.
ARM nuclear has oneself bus respectively with DSP nuclear, so the communication between them and exchanges data are generally carried out the carrying and the transmission of data by the external direct memory (DMA, Direct Memory Access) outside the chip.
Therefore in above-mentioned communication and the data exchange process, relate to comparatively complicated control logic circuit and agreement.And DMA adopts external, has certain distance with ARM nuclear and DSP nuclear power road; In addition, generally need carry out the data-moving of bulk in the DSP computing, these factors have strengthened time delay of data transmission, therefore, between causing ARM nuclear and DSP examining communicate by letter and there is certain time-delay in exchanges data, real-time is good inadequately, has influenced the communication speed and the communication quality of system.
In addition, all hang with some peripheral hardwares on the ARM nuclear in the current chip and the bus of DSP nuclear, in the audio frequency and video process chip, ARM nuclear has universal asynchronous receiving-transmitting (URAT, Universal AsynchronousReceiver-Transmitters) serial ports, pulse width modulator (PWM, Pulse Width Modulation) peripheral hardware such as, DSP nuclear has audio frequency apparatus (Audio Device), comprises peripheral hardwares such as Mike's grade, I2S interface.ARM nuclear and DSP endorse independently to visit the peripheral hardware of oneself separately by the bus of oneself, operate on it.If but ARM nuclear/DSP nuclear will but can only arrive data transmission on the DSP nuclear/ARM nuclear by DMA to the other side's peripheral hardware transmission data, the form that changes the peripheral hardware of DSP nuclear/ARM nuclear operation oneself into realizes.The process of this visit obviously also influences the communication speed of system.
Summary of the invention
In view of this, a fundamental purpose of the present invention is to provide a kind of ARM of realization nuclear to examine the chip of communicating by letter with DSP, reduces the delay that signal is handled in real time.
Another object of the present invention is to provide a kind of realize ARM nuclear and DSP nuclear method for communicating in the chip, improve the real-time processing speed of signal.
A further object of the present invention is to provide a kind of chip of communicating by letter between the multi-kernel in chip realized.
Be first aspect that achieves the above object, the invention provides the chip that a kind of ARM of realization nuclear is communicated by letter with DSP nuclear, wherein be provided with ARM nuclear and DSP nuclear, also be provided with shared storage in this chip, wherein,
Shared storage is connected with DSP nuclear with ARM nuclear respectively, and the reading and writing data that is used to accept from ARM nuclear and DSP nuclear instructs, and data sharing is provided;
ARM nuclear, the address location of being preset by ARM nuclear in shared storage writes data, and notice DSP nuclear is from this default address location reading of data after finishing; Or obtain the notice of examining from DSP, and according to this notice, the address location sense data of from shared storage, presetting by DSP nuclear;
DSP nuclear writes data by the default address location of DSP nuclear in shared storage, notice ARM nuclear is from this default address location reading of data after finishing; Or obtain the notice of examining from ARM, and according to this notice, the address location sense data of from shared storage, presetting by ARM nuclear.
Further, interrupt register can be provided with in the described shared storage, interrupt control unit ICU and interruptable controller ICTL can also be provided with in the described chip, wherein,
The interrupt register of shared storage is used for receiving second interrupt request singal of authorizing out to DSP nuclear/ARM from ARM nuclear/DSP nuclear, and produces corresponding look-at-me output;
ICU, be connected with described DSP nuclear and interrupt register, be used to receive described interrupt register according to the look-at-me sharm_dsp_intr that exports from second interrupt request singal of ARM nuclear, call corresponding service routine preface, to the output of DSP nuclear, DSP nuclear is carried out the service routine preface that receives, the address location sense data of being preset by ARM nuclear from shared storage;
ICTL, be connected with described ARM nuclear and interrupt register, be used to receive described interrupt register according to the look-at-me sharm_arm_intr that exports from second interrupt request of DSP nuclear, call corresponding service routine preface, to the output of ARM nuclear, ARM nuclear is carried out the service routine preface that receives, the address location sense data of being preset by DSP nuclear from shared storage.
Preferable, described interrupt register further can be used to receive first interrupt request singal of ARM nuclear output, and examine to DSP as ARM nuclear interrupt control signal forwarding, after the DSP stone grafting is received ARM nuclear interrupt control signal, will do not carried out any operation by what ARM nuclear carried out write operation by the default address location of ARM nuclear to current in the shared storage;
Described interrupt register also can be used for receiving first interrupt request singal of DSP nuclear output, and examine to ARM as DSP nuclear interrupt control signal forwarding, after the ARM stone grafting is received DSP nuclear interrupt control signal, will do not carried out any operation by what DSP nuclear carried out write operation by the default address location of DSP nuclear to current in the shared storage.
Preferable, described DSP nuclear/ARM nuclear further can be used for removing interrupt request singal to the interrupt register output of ICU/ICTL and shared storage after having read the data of shared storage by the default address location of ARM nuclear/DSP nuclear;
The interrupt register of shared storage receives removes interrupt request singal, removes look-at-me sharm_arm_intr and look-at-me sharm_dsp_intr;
ICU/ICTL is according to the removing interrupt request singal that receives, with its signal removal to the output of DSP nuclear/ARM nuclear.
Preferable, described shared storage comprises: ARM shared region, DSP shared region and RAM Shared district, wherein,
The ARM shared region receives the data and the storage of the output of ARM nuclear, and data are outputed to DSP nuclear;
The DSP shared region receives the data and the storage of the output of DSP nuclear, and data are outputed to ARM nuclear;
The RAM Shared district, be provided with DSP interrupt register and ARM interrupt register, wherein, the ARM that the DSP interrupt register is used to receive the output of ARM nuclear examines first interrupt request singal and ARM examines second interrupt request singal, corresponding generation ARM nuclear interrupt control signal and look-at-me sharm_dsp_intr export ICU to; The DSP that the ARM interrupt register is used to receive the output of DSP nuclear examines first interrupt request singal and DSP examines second interrupt request singal, and corresponding generation DSP nuclear interrupt control signal and look-at-me sharm_arm_intr export ICTL to.
Preferable, described shared storage further can comprise the Bridge module, further store the address mapping table of the peripheral hardware and the peripheral hardware that DSP examines of ARM nuclear in the described shared storage, the Bridge module, the operation requests information of the peripheral hardware of DSP nuclear/ARM nuclear is checked in reception from ARM nuclear/DSP, according to this operation requests information, address mapping table finds out the physical address that is operated peripheral hardware from shared storage, and to this physical address output function request to realize interleaving access to peripheral hardware, simultaneously authorize out the operation ban to DSP nuclear/ARM, DSP nuclear/ARM stone grafting will no longer be operated this peripheral hardware after receiving the operation ban.
Further, described built-in chip type has current status register CPR, is used to monitor ARM nuclear/DSP nuclear current state, output monitoring clock signal;
Described Bridge module is further used for the overtime protection of interleaving access peripheral hardware:
The monitoring clock signal of CPR output in the Bridge module receiving chip, and monitoring is to the operation of the physical address execution of described peripheral hardware, if the operation requests in the monitoring clock of predetermined number is not finished, the Bridge module is with automatic abort operation request, return miscue to ARM nuclear/DSP nuclear, export the information that lifts a ban to DSP nuclear/ARM nuclear simultaneously, remove the operation ban that DSP nuclear/ARM checks peripheral hardware.
Preferable, described shared storage can be Double Port Random Memory DRAM or twoport direct memory DDMA or twoport flash memory DFLASH or twoport synchronous dynamic random access memory DSDRAM.
Preferable, described ARM nuclear connects shared storage by the ARM bus, and described DSP nuclear is connected with described shared storage by dsp bus; Described Bridge module adopts the peripheral logical circuit of shared storage to realize.
Be another aspect that achieves the above object, the invention provides a kind of interior ARM nuclear of the chip realized and DSP nuclear method for communicating of chip as previously mentioned of being used for, this method comprises:
The address location by ARM nuclear/DSP nuclear preset of A:ARM nuclear/DSP nuclear in shared storage writes data, and notice DSP nuclear/ARM nuclear is from this default address location reading of data after finishing;
B:DSP nuclear/ARM nuclear obtains the notice from ARM nuclear/DSP nuclear, and according to this notice, the address location sense data of from shared storage, presetting by ARM nuclear/DSP nuclear.
Described steps A further can comprise: the address location by ARM nuclear/DSP nuclear preset of ARM nuclear/DSP nuclear in shared storage writes data, initiate ARM nuclear/DSP to the DSP/ARM of shared storage interrupt register and examine first interrupt request, DSP/ARM interrupt register output ARM nuclear/DSP nuclear interrupt control signal, be forwarded to DSP nuclear/ARM nuclear through ICU/ICTL, after DSP nuclear/ARM stone grafting is received ARM nuclear/DSP nuclear interrupt control signal, will be not do not examined the default address location that carries out write operation by ARM nuclear/DSP and carry out any operation current in the shared storage; After finishing, write data initiates interrupt request to the DSP/ARM of shared storage interrupt register, the DSP/ARM interrupt register of shared storage is exported look-at-me to ICU/ICTL, ICU/ICTL receives look-at-me, service routine preface information is called in output, and notice DSP nuclear/ARM nuclear is from this default address location reading of data;
Described step B further can comprise: DSP nuclear/ARM stone grafting is received the service routine preface information of calling, enter corresponding interruption subroutine, the address location sense data of from shared storage, presetting by ARM nuclear/DSP nuclear, initiate DSP nuclear/ARM to the ARM/DSP of shared storage interrupt register and examine first interrupt request, ARM/DSP interrupt register output DSP nuclear/ARM nuclear interrupt control signal, be forwarded to ARM nuclear/DSP nuclear through ICTL/ICU, after ARM nuclear/DSP stone grafting is received DSP nuclear/ARM nuclear interrupt control signal, will be not do not examined the default address location that carries out read operation by DSP nuclear/ARM and carry out any operation current in the shared storage.
Described ICU/ICTL receives look-at-me, and output is called service routine preface information and further can be comprised: if the look-at-me number that ICU/ICTL receives is one, call corresponding service routine preface according to look-at-me, service routine preface information is called in output; If the look-at-me number of ICU/ICTL reception is more than one, the corresponding service routine preface of output after look-at-me is interrupted arbitrating.
It is described that interrupt arbitrating back output specifically can be: default software interruption arbitration mode to look-at-me, by software setting look-at-me priority among the ICU/ICTL, according to look-at-me prioritized order, call corresponding service routine preface with the priority sequencing, service routine preface information is called in output.
The step that further can comprise interleaving access the other side peripheral hardware, be that described ARM nuclear/DSP nuclear is examined peripheral hardware/DSP nuclear peripheral hardware by the Bridge module to ARM and operated, it is specifically as follows: in advance in the address mapping table of shared storage stored ARM nuclear peripheral hardware and DSP nuclear peripheral hardware; During the visit peripheral hardware, ARM nuclear/DSP authorizes the operation requests information of sending, the Bridge module receives operation requests information, from shared storage, search address mapping table, obtain the physical address of corresponding peripheral hardware, and, authorize out the operation ban to DSP nuclear/ARM simultaneously to this physical address output function solicited message, described DSP nuclear/ARM stone grafting will no longer be operated this peripheral hardware after receiving the operation ban.
Described Bridge module further can comprise after receiving operation requests information: the monitoring clock signal that receives CPR output, the operation that monitoring is carried out the physical address of described peripheral hardware, if the operation requests in the monitoring clock of predetermined number is not finished, the Bridge module is with automatic abort operation request, return miscue to ARM nuclear/DSP nuclear, export the information that lifts a ban to DSP nuclear/ARM nuclear, remove the operation ban that DSP nuclear/ARM checks described peripheral hardware.
Described ARM nuclear peripheral hardware/DSP nuclear peripheral hardware is operated further and can be comprised: after ARM nuclear/DSP examines the executable operations request and finishes, finish information to Bridge module transmit operation request, the Bridge module is transmitted, DSP nuclear/ARM stone grafting is brought drill to an end and is made to ask to finish information, removes the operation ban that DSP nuclear/ARM checks described peripheral hardware.
The described address location sense data of being preset by ARM nuclear/DSP nuclear from shared storage further can comprise: after DSP nuclear/ARM nuclear runs through default address location data, remove look-at-me sharm_arm_intr and look-at-me sharm_dsp_intr; Be mainly: DSP nuclear/ARM nuclear is removed interrupt request singal to the interrupt register output of ICU/ICTL and shared storage, ICU/ICTL is according to removing interrupt request singal with its signal removal to the output of DSP nuclear/ARM nuclear, the interrupt register of shared storage receives removes interrupt request singal, removes look-at-me sharm_arm_intr and look-at-me sharm_dsp_intr.
In order to reach the 3rd purpose of the present invention, the present invention also provides a kind of chip of communicating by letter between the multi-kernel in chip realized, wherein be provided with first process nuclear and second process nuclear at least, and described first process nuclear has first bus, second process nuclear has second bus, also be provided with shared storage in this chip, wherein:
Shared storage is connected by the chip internal bus with second process nuclear with first process nuclear respectively, is used to accept the reading and writing data instruction of first process nuclear and second process nuclear, and data sharing is provided;
First process nuclear, the address location of being preset by first process nuclear in shared storage writes data, notifies second process nuclear from this default address location reading of data after finishing; Or obtain notice from second process nuclear, and according to this notice, from shared storage by the default address location sense data of second process nuclear;
Second process nuclear writes data by the default address location of second process nuclear in shared storage, notify first process nuclear from this default address location reading of data after finishing; Or obtain notice from first process nuclear, and according to this notice, from shared storage by the default address location sense data of first process nuclear.
Described shared storage further comprises the Bridge module, further store the address mapping table of the peripheral hardware of the peripheral hardware of first process nuclear and second process nuclear in the described shared storage, described Bridge module, reception is from the operation requests information of first process nuclear/second process nuclear to the peripheral hardware of second process nuclear/first process nuclear, according to this operation requests information, address mapping table finds out the physical address that is operated peripheral hardware from shared storage, and operation requests sent to realize the interleaving access to peripheral hardware to this physical address, simultaneously send the operation ban to second process nuclear/first process nuclear, described second process nuclear/first process nuclear will no longer be operated this peripheral hardware after receiving the operation ban.
Preferable, also can comprise the 3rd process nuclear, described the 3rd process nuclear is connected with described shared storage by its 3rd bus, and shares the data in the described shared storage;
Described first process nuclear, second process nuclear, the 3rd process nuclear all have interruptable controller, to realize the visit to the data in the described shared storage by interrupt mode and interruption arbitration.
As seen from the above technical solutions, the provided by the invention realization between multi-kernel in chip, as examining and internuclear chip of communicating by letter of DSP and communication means at ARM, it is provided with shared storage in chip, the data transmit-receive buffer zone is provided, the passage of data sharing particularly is provided, ARM nuclear and DSP nuclear write data by the address location of being preset by ARM nuclear/DSP nuclear in shared storage, and notify the other side to read, communication modes can pass through interrupt mode, DSP nuclear/ARM nuclear enters the respective interrupt subroutine according to look-at-me, and the transmitting-receiving of carrying out data in shared storage is with mutual.Further; the present invention also can utilize the Bridge module that is provided with in the shared storage; set up the data channel of direct interleaving access the other side peripheral hardware in the chip; realized that data sharing between double-core and the multinuclear, data interaction, interruption are mutual, interlock protection and interrupt the communication mechanism of arbitration and effectively exchange visits, data read-write operation is fast, time-delay is little, real-time.
Description of drawings
Fig. 1 is the structural representation that the present invention can realize the preferred embodiment of chip that ARM nuclear is communicated by letter with DSP nuclear;
Fig. 2 is the structural representation that the present invention can realize another preferred embodiment of chip that ARM nuclear is communicated by letter with DSP nuclear;
Fig. 3 is the structural representation that the present invention can realize the specific embodiment of the chip realization interlock protection that ARM nuclear is communicated by letter with DSP nuclear;
Fig. 4 is the specific embodiment schematic flow sheet that the present invention can realize ARM nuclear and DSP nuclear method for communicating
Fig. 5 is the schematic flow sheet that ARM nuclear of the present invention and DSP examine the specific embodiment of the method for visiting peripheral hardware.
Embodiment
Core concept of the present invention is: shared storage is set in chip, the data transmit-receive buffer zone is provided, the passage of data sharing particularly is provided, different disposal nuclear in the chip writes data by the default address location in shared storage, and notify the other side to read, thereby the transmitting-receiving of carrying out data in shared storage realizes the communication between the different disposal nuclear with mutual, data read-write operation is fast, and is real-time.
Further, by this shared storage, and the Bridge module of shared storage, set up the data channel of the direct interleaving access the other side of different kernels peripheral hardware in the chip.
For making the purpose, technical solutions and advantages of the present invention clearer, the present invention is described in further detail below in conjunction with the accompanying drawings and the specific embodiments.
Fig. 1 is the structural representation that the present invention can realize the preferred embodiment of chip that ARM nuclear is communicated by letter with DSP nuclear, as shown in Figure 1, this system comprises ARM nuclear, DSP nuclear, interrupt control unit (ICU, Interrupt Control Unit), interruptable controller (ICTL, Interrupt Controller) and shared storage, wherein
ARM nuclear by ARM high performance bus (AHB, Advanced High-performanceBus), writes and sense data to shared storage, the output interrupt request singal; Receive ICTL output, export to ICTL;
DSP nuclear by DSP high performance bus AHB, writes and sense data to shared storage, the output interrupt request singal; Receive ICU output, export to ICU;
Shared storage, be used for the data sharing of ARM nuclear and DSP nuclear, according to interrupt request singal inner interrupt register be set, the data of reception ARM nuclear/DSP nuclear output are also stored, export corresponding look-at-me to ICU/ICTL, output data is examined to DSP nuclear/ARM;
In the practical application, shared storage can be Double Port Random Memory (DRAM, DoubleRandom Access Memory) or twoport direct memory DDMA, also can be twoport flash memory DFLASH or twoport synchronous dynamic random access memory (DSDRAM, Double SynchronizationDynamic RAM), can also be other storage organization with shared memory function.
ICU receives the removing interrupt request singal of DSP nuclear output and the look-at-me sharm_dsp_intr of shared storage output, calls corresponding service routine preface, receives the interrupt control signal of shared storage output, transmits, to the output of DSP nuclear;
ICTL receives the removing interrupt request singal of ARM nuclear output and the look-at-me sharm_arm_intr of shared storage output, calls corresponding service routine preface, receives the interrupt control signal of shared storage output, transmits, to the output of ARM nuclear.
In the practical application, ICU and ICTL also can be integrated in the corresponding D SP nuclear/ARM nuclear.
The principle of work of system shown in Figure 1 is:
When ARM examines as the communication initiator, ARM nuclear is carried out write operation, communication data is stored into by default address location in the shared storage of its appointment, interrupt register output ARM to shared storage examines first interrupt request singal simultaneously, triggers the interrupt register output ARM nuclear interrupt control signal of shared storage.ICU receives ARM nuclear interrupt control signal and transmits, to the output of DSP nuclear.After the DSP stone grafting is received ARM nuclear interrupt control signal, will the current default address location that is carried out write operation by ARM nuclear in the shared storage not carried out any operation.When ARM nuclear finishes the communication data storage, examine second interrupt request singal to the interrupt register output ARM of shared storage, trigger the interrupt register output look-at-me sharm_dsp_intr of shared storage.ICU will call corresponding service routine preface after receiving look-at-me sharm_dsp_intr, to the output of DSP nuclear.After the DSP stone grafting is received described service routine preface, enter corresponding interruption subroutine, read the data of the nuclear of ARM in the shared storage in described default address location stored, initiate DSP to the ARM of shared storage interrupt register and examine first interrupt request, ARM interrupt register output DSP nuclear interrupt control signal, be forwarded to ARM nuclear through ICTL, after the ARM stone grafting is received DSP nuclear interrupt control signal, will the current default address location that is carried out read operation by DSP nuclear in the shared storage do not carried out any operation.After the relevant treatment of interruption subroutine was finished, DSP nuclear was removed interrupt request singal to the interrupt register output of ICU and shared storage, and ICU removes its signal to the output of DSP nuclear according to removing interrupt request singal, discharges the interrupt control to DSP nuclear; The interrupt register of shared storage receives removes interrupt request singal, removes look-at-me sharm_dsp_intr, discharges the interrupt control to ICU.
When DSP examines as the communication initiator, DSP nuclear stores communication data by the default address location in the shared storage of its appointment into by write operation, interrupt register output DSP to shared storage examines first interrupt request singal simultaneously, triggers the interrupt register output DSP nuclear interrupt control signal of shared storage.ICTL receives DSP nuclear interrupt control signal and transmits, to the output of ARM nuclear.After the ARM stone grafting is received DSP nuclear interrupt control signal, with not to current default address location executable operations of being carried out write operation by DSP nuclear in the shared storage.When DSP nuclear finishes the communication data storage, examine second interrupt request singal to the interrupt register output DSP of shared storage, trigger the interrupt register output look-at-me sharm_arm_intr of shared storage.ICTL receives look-at-me sharm_arm_intr, calls corresponding service routine preface, to the output of ARM nuclear.After the ARM stone grafting is received described service routine preface, enter corresponding interruption subroutine, read the data of DSP nuclear storage in the shared storage, initiate ARM to the DSP of shared storage interrupt register and examine first interrupt request, DSP interrupt register output ARM nuclear interrupt control signal, be forwarded to DSP nuclear through ICU, after the DSP stone grafting is received ARM nuclear interrupt control signal, will the current default address location that is carried out read operation by ARM nuclear in the shared storage do not carried out any operation.After the relevant treatment of interruption subroutine was finished, ARM nuclear was removed interrupt request singal to the interrupt register output of ICTL and shared storage, and ICTL discharges the interrupt control to ARM nuclear according to removing the signal of interrupt request singal removing to the output of ARM nuclear; The interrupt register of shared storage receives removes interrupt request singal, removes look-at-me sharm_arm_intr, discharges the interrupt control to ICTL.
Fig. 2 is the structural representation that the present invention can realize another preferred embodiment of chip that ARM nuclear is communicated by letter with DSP nuclear, and as shown in Figure 2, this system comprises ARM nuclear, DSP nuclear, ICU, ICTL and DRAM, wherein,
DRAM comprises: ARM shared region, DSP shared region and RAM Shared district;
The ARM shared region receives the data and the storage of the output of ARM nuclear, and data are outputed to DSP nuclear, and its big I is according to the size of data volume, the speed and the transmitting speed decision of data processing;
The DSP shared region receives the data and the storage of the output of DSP nuclear, and data are outputed to ARM nuclear, and its big I is according to the size of data volume, the speed and the transmitting speed decision of data processing;
The RAM Shared district, be provided with DSP interrupt register and ARM interrupt register, wherein, the ARM that the DSP interrupt register is used to receive the output of ARM nuclear examines first interrupt request singal and ARM examines second interrupt request singal, produce corresponding ARM nuclear interrupt control signal and look-at-me sharm_dsp_intr, export ICU to; The DSP that the ARM interrupt register is used to receive the output of DSP nuclear examines first interrupt request singal and DSP examines second interrupt request singal, produces corresponding D SP nuclear interrupt control signal and look-at-me sharm_arm_intr, exports ICTL to;
ARM nuclear by ARM high performance bus AHB, writes data to the ARM shared region, reads data in the DSP shared region, the DSP interrupt register output interrupt request singal in the RAM Shared district; Receive ICTL output, remove interrupt request singal to ICTL output;
DSP nuclear by DSP high performance bus AHB, writes data to the ARM shared region, reads data in the DSP shared region, the ARM interrupt register output interrupt request singal in the RAM Shared district; Receive ICU output, remove interrupt request singal to ICU output;
ICU, the look-at-me sharm_dsp_intr of DSP interrupt register output calls corresponding service routine preface in the removing interrupt request singal of reception DSP nuclear output and the RAM Shared district, receives the ARM nuclear interrupt control signal that interrupt register is exported, transmit, to the output of DSP nuclear;
ICTL, the look-at-me sharm_arm_intr of ARM interrupt register output calls corresponding service routine preface in the removing interrupt request singal of reception ARM nuclear output and the RAM Shared district, receives the DSP nuclear interrupt control signal that the ARM interrupt register is exported, transmit, to the output of ARM nuclear.
ICU can be the built-in interrupt control unit of DSP nuclear, also can be the interrupt control unit that the outside logical circuit of DSP nuclear constitutes; Equally, ICTL can be the built-in interruptable controller of ARM nuclear, also can be the interruptable controller that the outside logical circuit of ARM nuclear constitutes.
When ARM examines as the communication initiator, ARM nuclear is carried out write operation, communication data is stored in the address location default in the ARM shared region, examine first interrupt request singal to the DSP in RAM Shared district interrupt register output ARM simultaneously, trigger DSP interrupt register output ARM nuclear interrupt control signal.ICU receives ARM nuclear interrupt control signal and transmits, to the output of DSP nuclear.After the DSP stone grafting is received ARM nuclear interrupt control signal, will the current default address location that is carried out write operation by ARM nuclear in the ARM shared region not carried out any operation.When ARM nuclear finished the communication data storage, ARM examined second interrupt request singal to the output of the DSP in RAM Shared district interrupt register, and the DSP interrupt register produces look-at-me sharm_dsp_intr and exports ICU to.ICU calls corresponding service routine preface according to look-at-me sharm_dsp_intr, to the output of DSP nuclear.The DSP stone grafting enters corresponding interruption subroutine after receiving described service routine preface, reads the data of default address location stored in the ARM shared region.DSP nuclear also can adopt the mode of interruption in reading of data, notice ARM nuclear forbids that ARM checks this default address location and operates.
After the relevant treatment of interruption subroutine was finished, DSP nuclear was removed interrupt request singal to ICU and the output of DSP interrupt register, and ICU is according to removing interrupt request singal with its signal removal to the output of DSP nuclear; The DSP interrupt register receives removes interrupt request singal, removes look-at-me sharm_dsp_intr.In addition, DSP nuclear also can notify ARM nuclear reading of data to finish by the mode of interrupting, thereby discharges the interrupt control that DSP checks described default address location in the ARM shared region.
When DSP nuclear as the communication initiator, its principle of work does not repeat them here with above-mentioned similar when ARM examines as the communication initiator.
In the practical application, for correctness and the integrality of data in communication process, can adopt packet to add the method for checking data, the big I of packet decides according to the base unit of data transmission, base unit herein is meant an independently data structure, such as time data structure, date data structure etc., purpose be make this class formation can be in a bag end of transmission, avoid the unnecessary dispersion of data; The mode of verification then can be selected according to the situation of reality, such as adopting common verification and (CheckSum) verification.
In the practical application, ARM shared region and DSP shared region can take the different address locations of DRAM respectively, ARM shared region and DSP shared region non-overlapping copies, also can be that ARM shared region and DSP shared region combine, system adopts the mode of interrupting to avoid ARM nuclear and DSP nuclear to carry out accessing operation to the same address location of DRAM simultaneously.
Fig. 3 is the structural representation that the present invention can realize the specific embodiment of the chip realization interlock protection that ARM nuclear is communicated by letter with DSP nuclear; as shown in Figure 3; this system comprises ARM nuclear, DSP nuclear, ARM nuclear peripheral hardware, DSP nuclear peripheral hardware, present procedure status register (CPR; Current Program Register) and DRAM; wherein
ARM nuclear is used for sending operation requests information and operation requests is finished information to DRAM, receives the DRAM feedback information;
DSP nuclear is used for sending operation requests information and operation requests is finished information to DRAM, receives the DRAM feedback information;
CPR is used to write down ARM nuclear/DSP nuclear current state, current state in the chip monitored, and output monitoring clock signal;
DRAM has the Bridge module, and the Bridge module can be built in DRAM, also can be the outer logic circuit of DRAM.Store ARM nuclear peripheral hardware and DSP nuclear peripheral hardware physical address corresponding mapping relations in the DRAM in advance.The Bridge module can receive the operation requests of authorizing out from ARM nuclear/DSP, to DSP nuclear peripheral hardware/ARM nuclear peripheral hardware and the output of DSP nuclear/ARM nuclear, receive the ARM nuclear monitoring clock signal arm_unlock and the DSP nuclear monitoring clock signal dsp_unlock of CPR output, operation is monitored, handle monitoring result, to ARM nuclear/DSP nuclear output feedback information;
ARM nuclear peripheral hardware, DSP examine peripheral hardware, can be the peripherals of ARM nuclear in the existing and following chip and DSP nuclear respectively.As URAT (serial ports), the PWM (pulse width modulator) etc. of ARM nuclear, the Audio Device (comprising audio frequency apparatuses such as Mike) of DSP nuclear, I2S interface etc.
ARM nuclear sends operation requests to DSP nuclear peripheral hardware, the Bridge module receives operation requests information, receive the ARM nuclear monitoring clock signal arm_unlock of CPR output simultaneously, according to operation requests information, from DRAM, find out the physical address of corresponding DSP nuclear peripheral hardware, and to this physical address output function request, thereby realization is to the interleaving access of the other side's peripheral hardware.Also can comprise the operation ban of DSP nuclear peripheral hardware physical address simultaneously to the output of DSP nuclear, after the DSP stone grafting is received this operation ban, avoid this DSP nuclear peripheral hardware executable operations, anti-locking system enters deadlock state owing to initiating operation requests to the other side's peripheral hardware simultaneously; After the Bridge module output function request, also in the monitoring clock period of predetermined number, detect the operation that the physical address of DSP nuclear peripheral hardware is carried out according to the ARM nuclear monitoring clock signal arm_unlock that receives, if operation overtime is not finished, the Bridge module is with automatic abort operation request, and returning miscue to ARM nuclear, ARM examines end operation; To the DSP nuclear output information that lifts a ban, remove the operation ban that DSP checks DSP nuclear peripheral hardware, avoid the reactionless and phenomenon of occupying system resources always of ARM nuclear operation.
After the request of ARM nuclear executable operations finished, information was finished in the transmit operation request, removes the operation ban that DSP checks DSP nuclear peripheral hardware.
Similarly, when ARM examines when ARM nuclear peripheral hardware sends operation requests, also can examine peripheral hardware physical address executable operations to ARM by DRAM and Bridge module, and forbid that DSP checks this ARM nuclear peripheral hardware and redos, under ARM nuclear monitoring clock signal arm_unlock monitoring, avoid the reactionless and phenomenon of occupying system resources always of ARM nuclear operation.
DSP has authorized operation requests, and process is identical when having authorized operation requests with ARM, and just monitoring clock signal is DSP nuclear monitoring clock signal dsp_unlock, does not repeat them here.
Among the present invention; ARM nuclear is shared DRAM with DSP nuclear; DRAM has the Bridge module; the Bridge module receives the monitoring clock signal of CPR output; store ARM nuclear peripheral hardware and DSP nuclear peripheral hardware physical address corresponding mapping relations in the DRAM in advance; ARM nuclear/DSP nuclear is by Bridge module and DRAM; can visit the other side's external unit; effectively reduce the time delay that existing ARM nuclear/DSP nuclear visit the other side peripheral hardware causes; strengthen the real-time of communication, simultaneously, prevented that ARM nuclear/DSP nuclear is owing to initiate the deadlock that operation requests causes to the other side's peripheral hardware simultaneously; and ARM nuclear/DSP is examined operation overtime effectively protect, avoid ARM nuclear/DSP nuclear occupying system resources.
The embodiment that provides above is at nuclear of the ARM in the chip and DSP nuclear, but those skilled in the art should expect, structure of the foregoing description and principle also can be expanded and be used for carrying out mutual data communication by sharing DRAM between the multi-kernel in chip, its chip structure can with similar in the foregoing description, all having separately bus, interruptable controller, peripheral hardware etc. as each process nuclear, can be interrupt register of each process nuclear configuration among the corresponding D RAM.ARM nuclear and DSP examine when communicating by letter similar in its principle of work and the foregoing description, different is, because the intercommunication of multinuclear, therefore interruptable controller may receive the look-at-me of sharing a plurality of interrupt register outputs among the DRAM at one time, at this moment, interruptable controller need be selected look-at-me by the mode of interrupting arbitration, the mode of interrupting arbitration can adopt the software arbitration method, by interruptable controller software setting look-at-me priority, according to look-at-me prioritized order, thereby transfer corresponding Interrupt Service Routine preface visit with different priorities; When the interruption controller receives a plurality of look-at-me, search the interrupt priority table of storage in advance, according to information in the interrupt priority table look-at-me being made priority judges, call corresponding with service routine preface with the priority sequencing, to each process nuclear output, each process nuclear receives and calls service routine preface information, enters corresponding interruption subroutine.
Fig. 4 is the schematic flow sheet that the present invention can realize the specific embodiment of ARM nuclear and DSP nuclear method for communicating, and as shown in Figure 4, this flow process comprises:
Step 401～403, ARM nuclear outputs to DRAM with data, initiates interrupt request;
In this step, the communication data that ARM nuclear will need to transmit stores address location default among the DRAM into, interrupt register output ARM to DRAM examines first interrupt request singal simultaneously, trigger the interrupt register of DRAM, output ARM nuclear interrupt control signal, ICU receives ARM nuclear interrupt control signal and transmits, to the output of DSP nuclear, the DSP stone grafting is received ARM nuclear interrupt control signal, avoid default address location executable operations, when ARM nuclear finishes the communication data storage, initiate interrupt request to the interrupt register of DRAM once more storing communication data in the shared storage, output ARM examines second interrupt request singal, trigger the interrupt register of DRAM, produce look-at-me sharm_dsp_intr, ICU receives look-at-me sharm_dsp_intr, call corresponding service routine preface, call service routine preface information to the output of DSP nuclear;
Step 404～405, DSP nuclear has read among the DRAM and has removed look-at-me after the default address location data.
In this step, the DSP stone grafting is received the service routine preface information of calling, enter corresponding interruption subroutine, read default address location data among the DRAM, initiate DSP to the ARM of DRAM interrupt register simultaneously and examine first interrupt request, ARM interrupt register output DSP nuclear interrupt control signal is forwarded to ARM nuclear through ICTL, after the ARM stone grafting is received DSP nuclear interrupt control signal, will the current default address location that is carried out read operation by DSP nuclear in the shared storage not carried out any operation.After the relevant treatment of interruption subroutine was finished, DSP nuclear was removed interrupt request singal to the interrupt register output of ICU and DRAM, and ICU removes its signal to the output of DSP nuclear according to removing interrupt request singal, discharges the interrupt control to DSP nuclear; The interrupt register of DRAM receives removes interrupt request singal, removes look-at-me sharm_dsp_intr, discharges the interrupt control to ICU.
In the practical application, can authorize interrupt request by DSP, step does not repeat them here with 401～405 yet; In multiple nucleus system, also can utilize said method to set up the communication mechanism of data sharing between the multinuclear, data interaction, interruption, when ICU/ICTL receives a plurality of look-at-me, by interruption arbitration mode is set at ICU/ICTL look-at-me is dispatched: look-at-me priority is set, according to look-at-me prioritized order, transfer corresponding Interrupt Service Routine preface visit with the priority sequencing, improved data transmission efficiency, propagation delay time is little, and real time of data transmission strengthens.
In addition, DRAM can also be by being provided with the Bridge module, and ARM nuclear/DSP nuclear is realized visit the other side's external unit by the Bridge module.Fig. 5 is the schematic flow sheet that ARM nuclear of the present invention and DSP examine the specific embodiment of the method for visiting peripheral hardware, and as shown in Figure 5, this flow process comprises:
In this step, the Bridge module receives operation requests information, according to operation requests information, address mapping table finds out the physical address of corresponding DSP nuclear peripheral hardware from DRAM, and, comprise the operation ban that is used for interlocking of DSP nuclear peripheral hardware physical address information simultaneously to the output of DSP nuclear to this physical address output function request.
In this step, the DSP stone grafting is received interlock information, according to the DSP nuclear peripheral hardware physical address information that comprises in the operation ban, forbids this DSP nuclear peripheral hardware of DSP nuclear visit.When DSP nuclear visit DSP nuclear peripheral hardware/ARM nuclear peripheral hardware, similarly, forbid that this DSP nuclear of ARM nuclear visit peripheral hardware/ARM examines peripheral hardware.
In the practical application, the Bridge module can also receive the monitoring clock signal from CPR output, in the predetermined clock period, detect the operation that the physical address of DSP nuclear peripheral hardware is carried out, if operation overtime and not finishing, the Bridge module is with automatic abort operation request, and returning miscue to ARM nuclear, ARM examines end operation; To the DSP nuclear output information that lifts a ban, remove the operation ban that DSP checks DSP nuclear peripheral hardware, avoid the reactionless and phenomenon of occupying system resources always of ARM nuclear operation.
More than lift preferred embodiment; the purpose, technical solutions and advantages of the present invention are further described; institute is understood that; the above only is preferred embodiment of the present invention; not in order to restriction the present invention; within the spirit and principles in the present invention all, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (20)
1. the chip that can realize that ARM nuclear is communicated by letter with DSP nuclear wherein is provided with ARM nuclear and DSP nuclear, it is characterized in that, also is provided with shared storage in this chip, wherein,
Shared storage is connected with DSP nuclear with ARM nuclear respectively, and the reading and writing data that is used to accept from ARM nuclear and DSP nuclear instructs, and data sharing is provided;
ARM nuclear, the address location of being preset by ARM nuclear in shared storage writes data, and notice DSP nuclear is from this default address location reading of data after finishing; Or obtain the notice of examining from DSP, and according to this notice, the address location sense data of from shared storage, presetting by DSP nuclear;
DSP nuclear writes data by the default address location of DSP nuclear in shared storage, notice ARM nuclear is from this default address location reading of data after finishing; Or obtain the notice of examining from ARM, and according to this notice, the address location sense data of from shared storage, presetting by ARM nuclear.
2. chip as claimed in claim 1 is characterized in that: is provided with interrupt register in the described shared storage, also is provided with interrupt control unit ICU and interruptable controller ICTL in the described chip, wherein,
The interrupt register of described shared storage is used for receiving second interrupt request singal of authorizing out to DSP nuclear/ARM from ARM nuclear/DSP nuclear, and produces corresponding look-at-me output;
ICU, be connected with described DSP nuclear and interrupt register, be used to receive described interrupt register according to the look-at-me sharm_dsp_intr that exports from second interrupt request singal of ARM nuclear, call corresponding service routine preface, to the output of DSP nuclear, described DSP nuclear is carried out the service routine preface that receives, the address location sense data of being preset by ARM nuclear from shared storage;
ICTL, be connected with described ARM nuclear and interrupt register, be used to receive described interrupt register according to the look-at-me sharm_arm_intr that exports from second interrupt request of DSP nuclear, call corresponding service routine preface, to the output of ARM nuclear, described ARM nuclear is carried out the service routine preface that receives, the address location sense data of being preset by DSP nuclear from shared storage.
3. chip as claimed in claim 2, it is characterized in that: described interrupt register is further used for receiving first interrupt request singal of ARM nuclear output, and examine to DSP as ARM nuclear interrupt control signal forwarding, after described DSP stone grafting is received ARM nuclear interrupt control signal, will do not carried out any operation by what ARM nuclear carried out write operation by the default address location of ARM nuclear to current in the described shared storage;
Described interrupt register also is used to receive first interrupt request singal of DSP nuclear output, and examine to ARM as DSP nuclear interrupt control signal forwarding, after described ARM stone grafting is received DSP nuclear interrupt control signal, will do not carried out any operation by what DSP nuclear carried out write operation by the default address location of DSP nuclear to current in the described shared storage.
4. as claim 1,2 or 3 described chips, it is characterized in that, described DSP nuclear/ARM nuclear is further used for after the data that read the address location of being preset by ARM nuclear/DSP nuclear described in the shared storage, removes interrupt request singal to the interrupt register output of ICU/ICTL and shared storage;
The interrupt register of described shared storage receives removes interrupt request singal, removes look-at-me sharm_arm_intr and look-at-me sharm_dsp_intr;
Described ICU/ICTL is according to the removing interrupt request singal that receives, with its signal removal to the output of DSP nuclear/ARM nuclear.
5. chip as claimed in claim 1 is characterized in that, described shared storage comprises: ARM shared region, DSP shared region and RAM Shared district, wherein,
The ARM shared region receives the data and the storage of the output of ARM nuclear, and data are outputed to DSP nuclear;
The DSP shared region receives the data and the storage of the output of DSP nuclear, and data are outputed to ARM nuclear;
The RAM Shared district, be provided with DSP interrupt register and ARM interrupt register, wherein, the ARM that the DSP interrupt register is used to receive the output of ARM nuclear examines first interrupt request singal and ARM examines second interrupt request singal, corresponding generation ARM nuclear interrupt control signal and look-at-me sharm_dsp_intr export ICU to; The DSP that the ARM interrupt register is used to receive the output of DSP nuclear examines first interrupt request singal and DSP examines second interrupt request singal, and corresponding generation DSP nuclear interrupt control signal and look-at-me sharm_arm_intr export ICTL to.
6. chip as claimed in claim 1 or 2 is characterized in that,
Described shared storage further comprises the Bridge module, further store the address mapping table of the peripheral hardware and the peripheral hardware that DSP examines of ARM nuclear in the described shared storage, described Bridge module, the operation requests information of the peripheral hardware of DSP nuclear/ARM nuclear is checked in reception from ARM nuclear/DSP, according to this operation requests information, address mapping table finds out the physical address that is operated peripheral hardware from shared storage, and to this physical address output function request to realize interleaving access to peripheral hardware, simultaneously authorize out the operation ban to DSP nuclear/ARM, described DSP nuclear/ARM stone grafting will no longer be operated this peripheral hardware after receiving the operation ban.
7. chip as claimed in claim 6 is characterized in that: described built-in chip type has current status register CPR, is used to monitor ARM nuclear/DSP nuclear current state, output monitoring clock signal;
Described Bridge module is further used for the overtime protection of interleaving access peripheral hardware:
The monitoring clock signal of CPR output in the Bridge module receiving chip, and monitoring is to the operation of the physical address execution of described peripheral hardware, if the operation requests in the monitoring clock of predetermined number is not finished, the Bridge module is with automatic abort operation request, return miscue to ARM nuclear/DSP nuclear, export the information that lifts a ban to DSP nuclear/ARM nuclear simultaneously, remove the operation ban that DSP nuclear/ARM checks described peripheral hardware.
8. chip as claimed in claim 1 is characterized in that, described shared storage is Double Port Random Memory DRAM or twoport direct memory DDMA or twoport flash memory DFLASH or twoport synchronous dynamic random access memory DSDRAM.
9. chip as claimed in claim 7 is characterized in that: described ARM nuclear connects shared storage by the ARM bus, and described DSP nuclear is connected with described shared storage by dsp bus; Described Bridge module adopts the peripheral logical circuit of shared storage to realize.
10. one kind is used for the interior ARM nuclear of the chip realized and the DSP nuclear method for communicating of chip according to claim 1, it is characterized in that this method comprises:
The address location by ARM nuclear/DSP nuclear preset of A:ARM nuclear/DSP nuclear in shared storage writes data, and notice DSP nuclear/ARM nuclear is from this default address location reading of data after finishing;
B:DSP nuclear/ARM nuclear obtains the notice from ARM nuclear/DSP nuclear, and according to this notice, the address location sense data of from shared storage, presetting by ARM nuclear/DSP nuclear.
11. method as claimed in claim 10 is characterized in that, described steps A further comprises:
The address location by ARM nuclear/DSP nuclear preset of ARM nuclear/DSP nuclear in shared storage writes data, initiate ARM nuclear/DSP to the DSP/ARM of shared storage interrupt register and examine first interrupt request, DSP/ARM interrupt register output ARM nuclear/DSP nuclear interrupt control signal, be forwarded to DSP nuclear/ARM nuclear through ICU/ICTL, after DSP nuclear/ARM stone grafting is received ARM nuclear/DSP nuclear interrupt control signal, will be not do not examined the default address location that carries out write operation by ARM nuclear/DSP and carry out any operation current in the shared storage; After finishing, write data initiates interrupt request to the DSP/ARM of shared storage interrupt register, the DSP/ARM interrupt register of described shared storage is exported look-at-me to ICU/ICTL, described ICU/ICTL receives look-at-me, service routine preface information is called in output, and notice DSP nuclear/ARM nuclear is from this default address location reading of data;
Described step B further comprises:
DSP nuclear/ARM stone grafting is received the service routine preface information of calling, enter corresponding interruption subroutine, the address location sense data of from shared storage, presetting by ARM nuclear/DSP nuclear, initiate DSP nuclear/ARM to the ARM/DSP of shared storage interrupt register and examine first interrupt request, ARM/DSP interrupt register output DSP nuclear/ARM nuclear interrupt control signal, be forwarded to ARM nuclear/DSP nuclear through ICTL/ICU, after ARM nuclear/DSP stone grafting is received DSP nuclear/ARM nuclear interrupt control signal, will be not do not examined the default address location that carries out read operation by DSP nuclear/ARM and carry out any operation current in the shared storage.
12. method as claimed in claim 11, it is characterized in that, described ICU/ICTL receives look-at-me, output is called service routine preface information and is further comprised: if the look-at-me number that ICU/ICTL receives is one, call corresponding service routine preface according to look-at-me, service routine preface information is called in output; If the look-at-me number of ICU/ICTL reception is more than one, the corresponding service routine preface of output after look-at-me is interrupted arbitrating.
13. method as claimed in claim 12, it is characterized in that, it is described that interrupt arbitrating back output is specially: default software interruption arbitration mode to look-at-me, by software setting look-at-me priority among the ICU/ICTL, according to look-at-me prioritized order, call corresponding service routine preface with the priority sequencing, service routine preface information is called in output.
14. method as claimed in claim 10, it is characterized in that, the step that further comprises interleaving access the other side peripheral hardware, be that described ARM nuclear/DSP nuclear is examined peripheral hardware/DSP nuclear peripheral hardware by the Bridge module to ARM and operated, it is specially: in advance in the address mapping table of shared storage stored ARM nuclear peripheral hardware and DSP nuclear peripheral hardware; During the visit peripheral hardware, ARM nuclear/DSP authorizes the operation requests information of sending, the Bridge module receives operation requests information, from shared storage, search address mapping table, obtain the physical address of corresponding peripheral hardware, and, authorize out the operation ban to DSP nuclear/ARM simultaneously to this physical address output function solicited message, described DSP nuclear/ARM stone grafting will no longer be operated this peripheral hardware after receiving the operation ban.
15. method as claimed in claim 14, it is characterized in that, described Bridge module further comprises after receiving operation requests information: the monitoring clock signal that receives CPR output, the operation that monitoring is carried out the physical address of described peripheral hardware, if the operation requests in the monitoring clock of predetermined number is not finished, the Bridge module is with automatic abort operation request, return miscue to ARM nuclear/DSP nuclear, export the information that lifts a ban to DSP nuclear/ARM nuclear, remove the operation ban that DSP nuclear/ARM checks described peripheral hardware.
16. method as claimed in claim 14, it is characterized in that, described ARM nuclear peripheral hardware/DSP nuclear peripheral hardware is operated further and comprised: after ARM nuclear/DSP examines the executable operations request and finishes, finish information to Bridge module transmit operation request, the Bridge module is transmitted, DSP nuclear/ARM stone grafting is brought drill to an end and is made to ask to finish information, removes the operation ban that DSP nuclear/ARM checks described peripheral hardware.
17. as claim 10 or 11 described methods, it is characterized in that, the described address location sense data of being preset by ARM nuclear/DSP nuclear from shared storage further comprises: after DSP nuclear/ARM nuclear runs through default address location data, remove look-at-me sharm_arm_intr and look-at-me sharm_dsp_intr; Be mainly: DSP nuclear/ARM nuclear is removed interrupt request singal to the interrupt register output of ICU/ICTL and shared storage, ICU/ICTL is according to removing interrupt request singal with its signal removal to the output of DSP nuclear/ARM nuclear, the interrupt register of shared storage receives removes interrupt request singal, removes look-at-me sharm_arm_intr and look-at-me sharm_dsp_intr.
18. the chip of an implementing communicating between multi-kernel wherein is provided with first process nuclear and second process nuclear at least, and described first process nuclear has first bus, second process nuclear has second bus, it is characterized in that, also is provided with shared storage in this chip, wherein
Shared storage is connected with first process nuclear by first bus, and is connected with second process nuclear by second bus, is used to accept the reading and writing data instruction of first process nuclear and second process nuclear, and data sharing is provided;
First process nuclear, the address location of being preset by first process nuclear in shared storage writes data, notifies second process nuclear from this default address location reading of data after finishing; Or obtain notice from second process nuclear, and according to this notice, from shared storage by the default address location sense data of second process nuclear;
Second process nuclear writes data by the default address location of second process nuclear in shared storage, notify first process nuclear from this default address location reading of data after finishing; Or obtain notice from first process nuclear, and according to this notice, from shared storage by the default address location sense data of first process nuclear.
19. chip as claimed in claim 18, it is characterized in that: described shared storage further comprises the Bridge module, further store the address mapping table of the peripheral hardware of the peripheral hardware of first process nuclear and second process nuclear in the described shared storage, described Bridge module, reception is from the operation requests information of first process nuclear/second process nuclear to the peripheral hardware of second process nuclear/first process nuclear, according to this operation requests information, address mapping table finds out the physical address that is operated peripheral hardware from shared storage, and operation requests sent to realize the interleaving access to peripheral hardware to this physical address, simultaneously send the operation ban to second process nuclear/first process nuclear, described second process nuclear/first process nuclear will no longer be operated this peripheral hardware after receiving the operation ban.
20. chip as claimed in claim 18 is characterized in that: also comprise the 3rd process nuclear, described the 3rd process nuclear is connected with described shared storage by its 3rd bus, and shares the data in the described shared storage;
Described first process nuclear, second process nuclear, the 3rd process nuclear all have interruptable controller, to realize the visit to the data in the described shared storage by interrupt mode and interruption arbitration.
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