CN107423227A - Memory device, memory controller and its control method - Google Patents
Memory device, memory controller and its control method Download PDFInfo
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- CN107423227A CN107423227A CN201610351733.9A CN201610351733A CN107423227A CN 107423227 A CN107423227 A CN 107423227A CN 201610351733 A CN201610351733 A CN 201610351733A CN 107423227 A CN107423227 A CN 107423227A
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- memory cell
- memory
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- data transmission
- transmission state
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
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Abstract
A kind of control method of memory body discloses herein.Control method includes following operation.Detect the operational order to the first memory cell.Suspend the mode of operation of the second memory cell.Operational order is assigned to the first memory cell.The mode of operation of the second memory cell is replied, wherein the first memory cell and the second memory cell correspond to same passage.By above-mentioned control method, the efficiency of transmission of memory body is improved.
Description
Technical field
This case relates to a kind of memory device, and is controlled in particular to memory controller and its
Method processed.
Background technology
Flash type memory body has been widely used in the recent period.In general, memory device has memory
Body controller, it is controlling multiple flash type memory bodys in multiple passages.
In general, memory controller need to wait for fast flash memory bank an access instruction perform terminate after
Another access instruction can be just performed to it.In addition, in particular point in time, memory controller is only capable of allowing
Multiple fast flash memory bank one of which in single channel carry out data transmission.And in the prior art, note
Recall body controller and can try to allow and multiple fast flash memory banks in single channel while enter busy condition, but
The limitation of above-mentioned memory controller is limited to, and is coupled to the data of the processor of memory device
It is big to handle quantitative change, hardly possible is made into multiple fast flash memory banks in single channel while enters busy condition, is entered
And efficiency of transmission is reduced.
The content of the invention
In order to solve the above problems, an aspect of this case is to provide a kind of control method.Control method
Include following multiple operations.Detect the operational order to the first memory cell；Suspend the second memory body
The mode of operation of unit；Operational order is assigned to the first memory cell；And reply the second memory body
Mode of operation of unit, wherein the first memory cell and the second memory cell correspond to same lead to
Road.
One aspect of this case is to provide a kind of memory controller.Memory controller includes instruction electricity
Road and circuit for detecting.Instruction circuit according to external command transfer operation instructing to a plurality of memories
The first memory cell in body unit, wherein a plurality of memory cells correspond in same passage.
Circuit for detecting is detecting the mode of operation of the second memory cell.Wherein instruction circuit is more interrupting
The mode of operation of second memory cell, to assign operational order to the first memory cell, and grasping
The mode of operation of the second memory cell is replied in work instruction after assigning to the first memory cell.
In summary, the memory controller that this case is provided can immediately detect note with control method
The mode of operation of body unit is recalled, to accelerate the time that memory cell is assigned order.Consequently, it is possible to
The efficiency of transmission of memory device is improved.
Brief description of the drawings
For the above and other purpose, feature, advantage and embodiment of this case can be become apparent, institute
Accompanying drawings are described as follows：
Fig. 1 is a kind of schematic diagram of memory device according to depicted in this case some embodiments；
Fig. 2A is to illustrate the shape that memory cell in Fig. 1 is read according to this case some embodiments
State timing diagram；
Fig. 2 B are that the memory cell illustrated according to this case some embodiments in Fig. 1 carries out write operation
State timing chart；
Fig. 3 is that some embodiments illustrate a kind of flow for the method for controlling memory device according to this case
Figure；
Fig. 4 is to illustrate memory device in Fig. 1 according to this case some embodiments to be read twice in succession
The state timing chart of operation；And
Fig. 5 is to illustrate memory device in Fig. 1 according to this case some embodiments to be write twice in succession
The state timing chart of operation.
Embodiment
On " first " used herein, " second " ... etc., not especially censure order
Or the meaning of cis-position, also it is not used to limit this case, it is retouched just for the sake of difference with constructed term
The element stated or operation.
In addition, on " coupling " used herein or " connection ", it can refer to two or multiple members
Part mutually directly makees entity or in electrical contact, or mutually puts into effect body or in electrical contact indirectly, is also referred to as
Two or multiple element mutual operation or action.
Reference picture 1, Fig. 1 are a kind of memory device 100 according to depicted in this case some embodiments
Schematic diagram.Memory device 100 includes memory controller 120 and multiple memory body groups 140.
Memory controller 120 is coupled to host interface 101, to receive external command CH.In some
In embodiment, host interface 101 is more coupled to a processing unit and/or at least an input/output device,
To transmit external command CH.In some embodiments, host interface 101 includes the small-sized calculating of list type
Advanced additional (the Serial Advanced of machine interface (Serial Attached SCSI, SAS), list type
Technology Attachment, SATA) interface and/or advanced console controller interface (Advanced
Host Controller Interface,AHCI)。
Memory controller 120 is coupled to multiple memory body groups 140.Multiple memory body groups 140
Correspond to multiple channel C H0~CHN, and include multiple memory cells 142 respectively.In some realities
Apply in example, memory cell 142 is flash type memory body.In other embodiments, flash type note
Recall body and include NAND fast flash memory bank.The above-mentioned embodiment on memory cell 142 is only
Example, various types of memory cells 142 are all the scope that this case is covered.
In some embodiments, memory controller 120 includes instruction circuit 122 and circuit for detecting
124.Instruction circuit 122 is coupled to multiple memory cells 142.Instruction circuit 122 is coupled to main frame
Interface 101 produces operational order CO to right to receive external command CH according to external command CH
The memory cell 142 answered.In some embodiments, operational order CO, which is included, reads instruction, write-in
Instruct and/or erase instruction etc..
Circuit for detecting 124 is coupled to multiple memory cells 142, and sets to detect multiple memory bodys
The mode of operation OS of unit 142.In some embodiments, circuit for detecting 124 is set with poll
(polling) multiple memory cells 142, to obtain the operation shape for detecting multiple memory cells 142
State OS.In some embodiments, circuit for detecting 124 is coupled to instruction circuit 122, foregoing to return
Mode of operation OS to instruction circuit 122.In some embodiments, instruction circuit 122 is set with root
Decide whether to interrupt the memory cell 142 currently operated according to mode of operation OS, with peace
New operational order CO is inserted to another memory cell 142.Related operation will be carried out with reference to aftermentioned Fig. 3
Describe in detail.In some embodiments, it is different that memory cell 142 can pass through the output of index buffer
Flag, to reflect its mode of operation OS.In other embodiments, memory cell 142 can be saturating
Triggering (toggle) at least outside hardware pin is crossed (such as comprising connection address lines and/or control line
Deng pin) to reflect mode of operation OS.
Above-mentioned detecting mode of operation OS set-up mode is merely illustrative.The various memory bodys that are applied to control
The interaction mode of device 120 and multiple memory cells 142 is all the scope that this case is covered.
Reference picture 2A, Fig. 2A are some embodiments illustrate memory cell 142 in Fig. 1 according to this case
The state timing chart being read.As it was earlier mentioned, instruction circuit 122 is according to external command CH
Transfer operation instructs CO to corresponding memory cell 142.For Fig. 2A example, operation refers to
CO is made to be instructed to read.As shown in Figure 2 A, order is entered in time T1, memory cell 142
State SCMD.In some embodiments, coomand mode SCMDTo indicate corresponding memory cell
142, which are just being commanded circuit 142, assigns operational order CO.In time T2, memory cell 142 enters
Enter busy condition SBUSY.In some embodiments, busy condition SBUSYTo indicate corresponding memory
Its data is just loaded into a buffer (not illustrating) by body unit 142.In time T3, memory body list
Member 142 enters data transmission state SDATA.In some embodiments, data transmission state SDATAWith
The data that buffer is loaded in instruction is just read.
Reference picture 2B, Fig. 2 B are that the memory cell 142 in Fig. 1 is illustrated according to this case some embodiments
Carry out the state timing chart of write operation.For Fig. 2 B example, operational order CO refers to for write-in
Order.As shown in Figure 2 B, coomand mode S is entered in time T0, memory cell 142CMD.Yu Shi
Between T1, memory cell 142 enters data transmission state SDATA.In some embodiments, data
Transmission state SDATATo indicate that the data to be written into just is being loaded on corresponding memory cell 142
An interior buffer (not illustrating).In time T2, memory cell 142 enters busy condition SBUSY。
In some embodiments, busy condition SBUSYTo indicate the data for being loaded in buffer be just written into
Corresponding memory cell 142.
In some technologies, same passage is arranged in the single time, memory controller is only capable of allowing
Multiple memory cells 142 of (that is, belonging to same memory body group 140) (that is, belong to same note
Yi Ti groups 140) one of carry out data transmission operation.In above-mentioned technology, memory body control
Device after the busy condition of memory cell terminates, must could perform the action of data access, and right
Another memory cell of same passage assigns order.
As it was earlier mentioned, instruction circuit 122 can decide whether to interrupt at present according to mode of operation OS
The memory cell 142 operated, to assign new operational order CO to another memory cell
142.By above-mentioned set-up mode, another memory cell 142 can quickly enter busy condition
SBUSYAnd/or data transmission state SDATA.Compared to above-mentioned technology, the memory device 100 of this case
The efficiency of transmission of single channel be improved.
Fig. 3 is that some embodiments illustrate a kind of stream for the method 300 for controlling memory device according to this case
Cheng Tu.Fig. 4 is to illustrate memory device 100 in Fig. 1 according to this case some embodiments to carry out continuous two
The state timing chart of secondary read operation.Reference picture 1, Fig. 3 and Fig. 4 in the lump, to illustrate memory body control
The associative operation of device 120 processed.In some embodiments, control method 300 include multiple operation S310~
S360。
In operation S310, instruction circuit 122 assigns operational order CO to right according to external command CH
The memory cell 142 answered.For Fig. 4 example, external command CH instructs to read, and passes through
The memory cell 142 to channel C H0 is assigned (to claim memory cell afterwards by instruction circuit 122
142A).As shown in figure 4, enter coomand mode S in time T1, memory cell 142ACMD。
In operation S320, the poll memory cell 142A of circuit for detecting 124, to detect memory body list
First 142A mode of operation OS.As shown in figure 4, enter in time T2, memory cell 142A
Busy condition SBUSY.Enter data transmission state S in time T3, memory cell 142ADATA。
As it was earlier mentioned, in some embodiments, circuit for detecting 124 can poll memory cell 142A, with
Learn which kind of mode of operation current memory cell 142A is in.
In operation S330, instruction circuit 122 receives another memory cell corresponding to same passage
142 another external command CH.For Fig. 4 examples, in time T4, instruction circuit 122 connects
Receive the reading for another memory cell 142 (rear to claim memory cell 142B) for being intended to access path CH0
Instruction fetch.
In operation S340, instruction circuit 122 judges that memory cell 142A mode of operation OS is
It is no to be suspended.If so, then perform step S350.If it is not, Ze Chong Complex perform S320.In operation
S350, the interrupt memory body unit 142A of instruction circuit 122 mode of operation, and assign new operation to refer to
CO is made to memory cell 142B.
For Fig. 4 example, in time T4, instruction circuit 122, which receives, is intended to access/memory body list
First 142B external command CH.Meanwhile circuit for detecting 124 can learn memory cell 142A mesh
It is preceding still in data transmission state SDATA, and learn that memory cell 142B is in idle state SIDLE。
Therefore, in time T4, data transmission shape current the interrupt memory body unit 142A of instruction circuit 122
State SDATA, to assign corresponding operational order CO to memory cell 142B.Accordingly, memory body
Unit 142B enters coomand mode SCMD。
In operation S360, instruction circuit 122 replys memory cell 142A mode of operation, so that
Memory cell 142A, which continues, performs prior operation.For example, as shown in figure 4, in time T5, refer to
Circuit 122 is made to reply memory cell 142A data transmission state SDATA, so that memory cell
142A continues previous data transmission operation.
By aforesaid operations, memory cell 142A and memory cell 142B are in can in certain time
Operated simultaneously, to increase channel C H0 efficiency of transmission.For example, when time T5,
Memory cell 142A is responded to data transmission state SDATA, with via respective channel CH0 money
Expect bus-bar data transmission.It is responded in memory cell 142A to data transmission state SDATAPhase
Between, memory cell 142B has been enter into busy condition SBUSY.In time T6, memory cell 142A
Data be transmitted, and enter idle state SIDLE.Therefore, memory cell 142B's
Busy condition SBUSYAfter end, memory cell 142 can immediately enter data transmission shape in time T7
State SDATA, with via respective channel CH0 data bus data transmission.For equivalent, passage
CH0 is increased in the data quantity transmitted in same time.
Fig. 5 is to illustrate memory device in Fig. 1 according to this case some embodiments to be write twice in succession
The state timing chart of operation.Reference picture 1, Fig. 3 and Fig. 5 in the lump, to illustrate memory controller
120 associative operation.For Fig. 5 example, external command CH is write instruction, and via finger
Circuit 122 is made to assign to channel C H0 memory cell 142A (that is, operation S310).Such as figure
Shown in 5, enter coomand mode S in time T1, memory cell 142ACMD.In time T2, note
Recall body unit 142A and enter data transmission state SDATA。
In time T3, instruction circuit 122, which receives, to be intended to write channel C H0 memory cell 142B
Enter the write instruction (that is, operation S330) of data.Meanwhile circuit for detecting 124 learns memory body list
First 142A is at present still in data transmission state SDATA(that is, operation S320), and learn memory body
Unit 142B is in idle state SIDLE.Therefore, in time T3, the interrupt memory of instruction circuit 122
Data transmission state S current body unit 142ADATA, to assign corresponding operational order CO to note
Recall body unit 142B (that is, operation S340 and S350).Accordingly, memory cell 142B enters
Coomand mode SCMD.Then, reply memory cell 142A's in time T4, instruction circuit 122
Data transmission state SDATA, so that memory cell 142A continues previous data transmission operation (also
Operate S360).In this example, memory cell 142B waits memory cell 142A data
Transmission state SDATAAfter T5 terminates in the time, data transmission state S is entered back intoDATA。
Or in other embodiments, in time T4, instruction circuit 122 can allow memory cell
142B is introduced into data transmission state SDATA, and enter busy condition S in memory cell 142BBUSY
Reply memory cell 142A data transmission state S again afterwardsDATA。
Fig. 2A, Fig. 2 B, Fig. 4 and Fig. 5 are merely illustrative.For it can be readily appreciated that in above-mentioned each schema
The buffer time switched between each mode of operation or transient state time are not showed that.In addition, above-mentioned each schema
In each mode of operation time interval it is also merely illustrative.The usual skill in this area should be understood to remember
Each mode of operation of body device can have a different time section according to practical application, therefore each mode of operation
Various time intervals are all the scope that this case is covered.
For example, in other embodiments, the time T6 in Fig. 4 can align with time T7, that is,
In the data transmission state S that memory cell 142A is extendedDATAAfter end, memory cell 142B
Soon enter data transmission state SDATA.One skilled in the art should can be according to above-mentioned
Other set-up modes of each mode of operation of schema understanding, therefore this case and the embodiment for not only stating schema above
Limited.
In each embodiment, the embodiment of memory controller 120 can be software, hardware with/
Or a piece of wood serving as a brake to halt a carriage body.For example, memory controller 120 can be realized by the software of execution method 300.Or
Person, memory controller 120 can be realized by the digit circuit of execution method 300.In other implementations
In example, the unit in memory controller 120 can also use software, hardware and a piece of wood serving as a brake to halt a carriage body association simultaneously
Same operation.The tool of the visual actual demand selection memory controller 120 of one skilled in the art
Body embodiment.
It is above-mentioned only to be illustrated with reading instruction twice in succession with write instruction twice in succession.All kinds
Operational order CO and execution sequence be all scope that this case is covered.Finger in the various embodiments described above
Make execution sequence to include and continuously perform once reading instruction and write-once instruction, and read instruction
Busy condition SBUSYPeriod is suspended, to assign write instruction.Or the finger in the various embodiments described above
Make execution sequence also to include and continuously perform write-once instruction with once reading instruction, and
In the data transmission state S of write operationDATAOr busy condition SBUSYPeriod is suspended, and is read with assigning
Instruction.In other embodiments, above-mentioned instruction execution sequence can include continuously perform write instruction with
Erase instruction, and in the data transmission state S of write operationDATAOr busy condition SBUSYPeriod is suspended,
To assign instruction of erasing.In other embodiment, above-mentioned instruction execution sequence can be included and continuously performed
Instruction and instruction of erasing are read, and in the data transmission state S of read operationDATAOr busy condition
SBUSYPeriod is suspended, to assign instruction of erasing.
In summary, the memory controller that this case is provided can immediately detect note with control method
The mode of operation of body unit is recalled, to accelerate the time that memory cell is assigned order.Consequently, it is possible to
The efficiency of transmission of memory device is improved.
Although this case is disclosed above with embodiment, so itself and non-limiting this case is any to be familiar with this skill
Skill person, in the spirit and scope for not departing from this case, when can be used for a variety of modifications and variations, therefore this
The protection domain of case is worked as to be defined depending on appended claims institute defender.
Claims (10)
1. a kind of control method, comprising：
Detect the operational order to one first memory cell；
Suspend a mode of operation of one second memory cell；
The operational order is assigned to first memory cell；And
The mode of operation of second memory cell is replied,
Wherein first memory cell corresponds to same passage with second memory cell.
2. control method according to claim 1, wherein suspending being somebody's turn to do for second memory cell
The operation of mode of operation includes：
Whether judge the mode of operation of second memory cell can be suspended；And
When the mode of operation of second memory cell is a data transmission state, suspend this second
The mode of operation of memory cell.
3. control method according to claim 2, wherein judging being somebody's turn to do for second memory cell
The operation of mode of operation includes：
Poll (polling) second memory cell, to detect the behaviour of second memory cell
Make state.
Instructed 4. control method according to claim 1, the wherein operational order are a reading,
The mode of operation is a data transmission state, and the control method includes：
After data transmission state being extended of second memory cell terminates, make first note
Recall body unit and enter the data transmission state.
5. control method according to claim 4, wherein in the money of second memory cell
During material transmission state is responded, first memory cell enters a busy condition.
6. a kind of memory controller, comprising：
One instruction circuit, to according to an external command, to transmit an operational order to a plurality of memories
One first memory cell in body unit, wherein those memory cells correspond in same passage；
And
One circuit for detecting, to detect a behaviour of one second memory cell in those memory cells
Make state；
Wherein the instruction circuit is more to interrupt the mode of operation of second memory cell, to assign
The operational order is assigned to the first memory body list to first memory cell, and in the operational order
The mode of operation of second memory cell is replied after member.
7. memory controller according to claim 6, the wherein instruction circuit are in second note
When the mode of operation for recalling body unit is a data transmission state, suspend being somebody's turn to do for second memory cell
Mode of operation.
8. memory controller according to claim 6, wherein the circuit for detecting is to poll
(polling) second memory cell, to detect the mode of operation of second memory cell.
Refer to 9. memory controller according to claim 6, the wherein operational order are a reading
Order, the mode of operation is a data transmission state, and the instruction circuit is more in second memory body
After data transmission state being extended of unit terminates, first memory cell is set to enter the data
Transmission state.
10. memory controller according to claim 9, wherein in second memory cell
The data transmission state be responded during, first memory cell enters a busy condition.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610351733.9A CN107423227A (en) | 2016-05-24 | 2016-05-24 | Memory device, memory controller and its control method |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610351733.9A CN107423227A (en) | 2016-05-24 | 2016-05-24 | Memory device, memory controller and its control method |
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| US20140215175A1 (en) * | 2013-01-31 | 2014-07-31 | Apple Inc. | Efficient suspend-resume operation in memory devices |
| CN104520932A (en) * | 2012-05-23 | 2015-04-15 | Sk海尼克斯存储技术公司 | Flash memory controller |
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| US20130198451A1 (en) * | 2009-09-09 | 2013-08-01 | Fusion-Io | Erase suspend/resume for memory |
| CN104520932A (en) * | 2012-05-23 | 2015-04-15 | Sk海尼克斯存储技术公司 | Flash memory controller |
| US20140215175A1 (en) * | 2013-01-31 | 2014-07-31 | Apple Inc. | Efficient suspend-resume operation in memory devices |
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Effective date of registration: 20190419 Address after: 230012 Hefei Intelligent Industrial Park Standardized Workshop No. 11 at the junction of Wenzhong Road and Qianjiang Road, Xinzhan District, Hefei City, Anhui Province Applicant after: Hefei Peirui Microelectronics Co., Ltd. Address before: No. 2 Innovation Road, Xinzhu Science Industrial Park Applicant before: Ruiyu Semiconductor Co., Ltd. |
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Application publication date: 20171201 |