CN104238957A - Serial peripheral interface controller, serial peripheral interface flash memory, access method and access control method - Google Patents
Serial peripheral interface controller, serial peripheral interface flash memory, access method and access control method Download PDFInfo
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Abstract
The invention provides at least a serial peripheral interface controller, a serial peripheral interface flash memory, an access method and an access control method. The access method is used for the serial peripheral interface flash memory. The serial peripheral interface flash memory comprises a flash memory array and supports a plurality of data flows. The access method comprises: a flow starting instruction is received for the data flows of the plurality of data flows, and the flow starting instruction comprises access type and an identification code of the data flow; address information is received, the address information comprises the page address of the page of the flash memory array and an address pointer; data is read from the flash memory array to a flow register corresponding to the data flow according to the flow starting instrument and the page address, or according to the flow starting instrument, the data to be written into the flash memory array us stored into the flow register corresponding to the data flow. High-efficiency operation for data flow storage can be achieved and processing time can be shortened.
Description
Technical field
The invention relates to a kind of storage arrangement, especially in regard to a kind of serial flash memory (serial flash memory) device.
Background technology
Flash memory device is generally used for electronic application, as personal computer, personal digital assistant (Personal Digital Assistants, PDAs), digital camera and mobile phone.Usually, flash memory device is divided into parallel flash memory (parallel flash memory) device and serial flash memory device.Compared with parallel flash memory, serial flash memory has less transmission line (tramsmission lines) and pin (pin) number.Therefore, the package dimension of serial flash memory can reduce relatively, and serial flash memory can be used as the leading storer (dominant memory) of portable electron device.
Tradition 8 pin (8-pin) serial peripheral interface (Serial Peripheral Interface, a SPI) NAND quick-flash memory comprises chip selection pin CS#, serial clock pin SCK, serial date transfer/serial date transfer and output connecting pin SI/SO0, serial data output/serial date transfer and output connecting pin SO/SO1, write protection/serial date transfer and output connecting pin WP#/SO2, maintenance/serial date transfer and output connecting pin HOLD#/SO3, electric power supply pin VCC and ground connection pin GND.In this specification; for purpose of brevity, serial date transfer/serial date transfer and output connecting pin SI/SO0, serial data output/serial date transfer and output connecting pin SO/SO1, write protection/serial date transfer and output connecting pin WP#/SO2 and maintenance/serial date transfer and output connecting pin HOLD#/SO3 also can be described as serial input and output connecting pin.Storer selects signal by chip selection pin CS# receiving chip.When chip select signal becomes low level, under storer is in active power pattern (active power mode).When chip select signal becomes high level, storer anergy (disabled), and serial data output connecting pin SO is placed in high impedance status High-z.Storer receives serial clock signal, for providing serial line interface sequential for storer by serial clock pin SCK.Address information, instruction and data latch (latch) or fetch (retrieve) in the rising edge of serial clock signal, and the output of data triggered after the drop edge of serial clock signal.
Figure 1A, Figure 1B and Fig. 1 C shows the sequential chart of the page read operation of above-mentioned traditional SPI NAND quick-flash memory.Page read operation performs in order to the data in NAND flash array are sent to cache memory (cache).First, when after chip select signal enable (enabled), storer receives page reading command CMD-PR by serial date transfer pin SI.Then, storer receives block/page address ADD-P.When after block/page address ADD-P registered (registered), storer starts to transmit data to cache memory by NAND flash array, and work (busy) continues duration t
cS.After this, initiate (issue) and obtain feature instruction CMD-GF to detect mode of operation.Based on the status register address AD D-SR received, by the status register data D-SR reading instruction mode of operation in status register (rigister), then exported by serial data output connecting pin SO.
After being successfully completed state, initiate random data read operation to read the data in cache memory.Random data read operation can be single read operation (single read operation), dual read operation (dual read operation) or quadruple read operation (quad read operation).In single read operation, serial input and output connecting pin SI/SO0 are for inputting instruction, and serial input and output connecting pin SI/SO1 are for exporting reading data, and thus the bandwidth of output stream is 2 bits (bits).In addition, in quadruple read operation, serial input and output connecting pin SI/SO0, SI/SO1, WP#/SO2 and HOLD#/SO3 all use, and to export reading data, thus the bandwidth of output stream is 4 bits.
Fig. 2 A and Fig. 2 B shows the sequential chart of the quadruple read operation of above-mentioned traditional SPI NAND quick-flash memory.In quadruple read operation, storer receives quadruple reading command CMD-RC by serial input and output connecting pin SI/SO0 after chip select signal is enable.After position PS is selected in three virtual bit DB and plan, storer receives column address (column address) ADD-C.Then, after a dummy bytes DBy, according to column address ADD-C, the reading data (as the byte B1 in Fig. 2 B, B2, B3 and B4) in cache memory are exported by serial input and output connecting pin SI/SO0, SI/SO1, WP#/SO2 and HOLD#/SO3 by storer.
But, possessing in the electronic installation processing multiple data stream ability, when electronic installation by carrying out switching to read data or write data in SPI NAND quick-flash memory in by SPI NAND quick-flash memory between different data streams, likely there is many latent periods (wait cycles).Such as, when reading data by the first data stream, the page read operation about first page and random data read operation is performed, to read data by storer.When switching to by the second data stream reading data, perform the page read operation about second page and random data read operation.After this, when switching back through the first data stream reading data, the data of second page are stored because cache memory is current, need again to perform the page read operation about first page, with by the digital independent of first page to cache memory, then perform random data read operation to read the data in cache memory.In other words, likely again initiate page reading command, block/page address, obtain feature instruction, status register address and column address.Therefore, do not reused owing to adding latent period and repeat to send some information (as address, instruction, previously reading data etc.), particularly under performing the condition of access, likely wasting much time and accessing resource by frequent switching between different data streams.
Summary of the invention
In view of this, the invention provides access method and the access control method of at least one serial peripheral interface flash memory, serial peripheral interface controller and serial peripheral interface flash memory.
The invention provides a kind of access method, for a serial peripheral interface flash memory, wherein this serial peripheral interface flash memory comprises a flash memory array and supports multiple data stream, this access method comprises: receive first-class startup (stream initiate) instruction, for the data stream in the plurality of data stream, wherein this stream enabled instruction comprises an access type and the identification code of this data stream; Receiver address information, wherein this address information comprises page address and an address pointer (address pointer) of a page of this flash memory array; And according to this stream enabled instruction and this page address, by reading data in this flash memory array to the stream register corresponding to this data stream, or according to this stream enabled instruction, the data storing of this flash memory array to be written is entered in this stream registers corresponding to this data stream.
The present invention separately provides a kind of access control method, for a serial peripheral interface flash memory, wherein this serial peripheral interface flash memory comprises a flash memory array and supports multiple data stream, this access method comprises: send first-class enabled instruction to this serial peripheral interface flash memory, wherein this stream enabled instruction is used for the data stream in the plurality of data stream, and this stream enabled instruction comprises an access type and an identification code of this data stream; Send address information to this serial peripheral interface flash memory, wherein this address information comprises a page address and an address pointer of a page of this flash memory array; And according to this stream enabled instruction and this page address, control this serial peripheral interface flash memory by reading data in this flash memory array to the stream register corresponding to this data stream, or according to this stream enabled instruction, control this serial peripheral interface flash memory and the data storing of this memory array to be written is entered this stream registers corresponding to this data stream.
The present invention separately provides a kind of serial peripheral interface flash memory, supports multiple data stream, and this serial peripheral interface flash memory comprises: a flash memory array; Multiple stream registers, each stream registers corresponds to one in the plurality of data stream; And a steering logic, be coupled to this flash memory array and the plurality of stream registers, receive first-class enabled instruction and the address information of the data stream be used in the plurality of data stream, wherein this stream enabled instruction comprises an access type and an identification code of this data stream, and this address information comprises a page address and an address pointer of a page of this flash memory array; Wherein, data are according to this stream enabled instruction and this page address by the stream register read in this flash memory array corresponding to this data stream, or data are stored in this stream registers corresponding to this data stream according to this stream enabled instruction.
The present invention separately provides a kind of serial peripheral interface controller, be coupled to a serial peripheral interface flash memory, to control the accessing operation of this serial peripheral interface flash memory, wherein this serial peripheral interface flash memory comprises a flash memory array, and support multiple data stream, this serial peripheral interface controller comprises: a steering logic, send the first-class enabled instruction of the data stream be used in the plurality of data stream and address information to this serial peripheral interface flash memory, wherein this stream enabled instruction comprises an access type and an identification code of this data stream, and this address information comprises a page address and an address pointer of a page of this flash memory array, and this steering logic controls this serial peripheral interface flash memory by reading data in this flash memory array to the stream register corresponding to this data stream according to this stream enabled instruction and this page address, or the data storing of this flash memory array to be written to be entered this stream registers corresponding to this data stream according to this stream enabled instruction by this steering logic.
Utilize serial peripheral interface controller provided by the present invention, serial peripheral interface flash memory and access method thereof and access control method, the efficient operation of data stream access can be realized, and shorten the processing time.
Accompanying drawing explanation
Figure 1A, Figure 1B and Fig. 1 C shows the sequential chart of the page (page) read operation of traditional SPI NAND quick-flash memory.
Fig. 2 A and Fig. 2 B shows the sequential chart of the quadruple read operation of traditional SPI NAND quick-flash memory.
Fig. 3 A and Fig. 3 B shows the sequential chart of the stream start-up operation of SPI NAND quick-flash memory according to an embodiment of the invention.
Fig. 4 shows the sequential chart of the continuous read operation of SPI NAND quick-flash memory according to an embodiment of the invention.
Fig. 5 shows the block schematic diagram of SPI controller 50 according to an embodiment of the invention.
Fig. 6 shows the block schematic diagram of SPI storer 60 according to an embodiment of the invention.
Embodiment
Some vocabulary is employed to censure specific assembly in the middle of instructions and claim.Those skilled in the art should understand, and hardware manufacturer may call same assembly with different nouns.This specification and claims are not used as with the difference of title the mode distinguishing assembly, but are used as the criterion of differentiation with assembly difference functionally." comprising " and " comprising " mentioned in the middle of instructions and claim is in the whole text an open term, therefore should be construed to " comprise but be not limited to "." roughly " refer to that in acceptable error range, those skilled in the art can solve the technical problem within the scope of certain error, reach described technique effect substantially.In addition, " couple " word comprise directly any at this and be indirectly electrically connected means.Therefore, if describe a first device in literary composition to be coupled to one second device, then represent this first device and directly can be electrically connected at this second device, or be indirectly electrically connected to this second device by other device or connection means.The following stated is for implementing preferred mode of the present invention, and object is spirit of the present invention is described and is not used to limit protection scope of the present invention, and protection scope of the present invention is when being as the criterion depending on the accompanying claim person of defining.
One embodiment of the invention provide a kind of access method, for SPI flash memory.SPI flash memory comprises flash memory array and supports multiple data stream.SPI flash memory comprises multiple stream registers further, and each stream registers corresponds to one in multiple data stream.This access method comprises the operation of stream start-up operation, page access operations and consecutive access (continuous access), wherein flows start-up operation for starting in multiple data stream.The number of above-mentioned data stream can be 4 to 8.
Fig. 3 A and Fig. 3 B shows the sequential chart of the stream start-up operation of SPI NAND quick-flash memory according to an embodiment of the invention.First, receive for the data stream in multiple data stream (as X
thdata stream) stream enabled instruction CMD-SI.Stream enabled instruction CMD-SI comprises the access type of data stream and the identification code of data stream.Access type can be and reads type or write type, and the accessing operation wherein reading type indicator data stream is read operation, and the access type of write type indicator data stream is write operation, and for single data stream, only have an access type.The access type of data stream and identification code can decide according to the instruction word (command word) of stream enabled instruction CMD-SI.Such as, instruction word 4Xh instruction is used for X
thdata stream also performs the stream enabled instruction of read operation.Then, receiver address information ADD-I.Address information ADD-I comprises page address and the address pointer of the page of flash memory array.Access type and the address information ADD-I received can be stored in the stream registers corresponding to data stream, and address pointer is used in reference to the data to being stored in stream registers.Therefore, address information ADD-I can be the combination of the page address ADD-P in Figure 1A and Figure 1B and the column address ADD-C in 2A figure.When SPI flash memory receives stream enabled instruction for data stream and address information, and after access type has been stored into corresponding stream registers, the startup of data stream completes, and in other words, stream start-up operation terminates.
Page access operations follows stream start-up operation closely, for according to stream enabled instruction and page address by reading page data in flash memory array to corresponding to the stream registers of data stream, or the data storing of flash memory to be written entered the stream registers corresponding to data stream according to stream enabled instruction.Page access operations spontaneous (spontaneously) after the stream startup for data stream terminates for data stream performs.Such as, if first-class enabled instruction instruction is used for the first data stream and performs the stream start-up operation of read operation, then after the first data stream starts, read page data according to the page address in address information by flash memory, and the page data of reading is stored in the first-class register corresponding to the SPI flash memory of the first data stream.If second enabled instruction indicates the stream enabled instruction the stream enabled instruction performing write operation that are used for the second data stream, then after the second data stream starts, send the page data of flash memory array to be written, and be stored in the second register corresponding to the SPI flash memory of the second data stream.
Consecutive access operation follows page access operations closely, for according to address pointer by exporting the page data (continuous read operation) read in stream registers, or according to address pointer by stream registers page data write flash memory array (continuous write operation).In consecutive access operation, first receive the consecutive access instruction being used for data stream.Consecutive access instruction comprises the identification code of data stream.In continuous read operation, according to address pointer, read by SPI flash memory by the page data of reading corresponded in the stream registers of data stream, wherein stream registers can decide according to the identification code of data stream, and address pointer increases after data export.In continuous write operation, according to page address and address pointer, by the page data write flash memory corresponded in the stream registers of data stream, wherein stream registers can decide according to the identification code of data stream, and address pointer increases after the data writing is finished.
Fig. 4 shows the sequential chart of the continuous read operation of SPI NAND quick-flash memory according to an embodiment of the invention.First, receiving package is containing the continuous reading command CMD-ID of the identification code of data stream.Such as, instruction word 5Xh instruction is used for X
ththe continuous reading command of data stream.Then, according to being stored in X
thaddress pointer in stream registers, by X
ththe page data of reading (output data word joint B1, B2, B3 and B4 as in Fig. 4) in stream registers reads by SPI flash memory, and is stored in X
thaddress pointer in stream registers is at X
ththe page data of reading in stream registers increases after exporting.Such as, for X
ththe X received in the stream start-up operation of data stream
ththe initial address pointer of data stream points to X
ththe first byte reading page data in stream registers.By X
thafter exporting the first byte, the second byte, the 3rd byte and nybble in stream registers, be stored in X
thaddress pointer in data stream is increased to and points to X
ththe 5th byte of page data has been read in stream registers.Therefore, X is worked as
thafter four bytes reading page data in stream registers export, if SPI flash memory is by X
thdata flow handoff to another data stream, and then switches back X
thdata stream, then X
ththe 5th byte reading page data in stream registers directly can export according to address pointer, and without the need to sending row address.Further, X is worked as
thafter data stream starts, due to for X
ththe page data of reading of data stream is stored in X
thin stream registers, thus when switching back X
thwithout the need to again initiating page address and page read operation during data stream.Correspondingly, processing time of comparing spent by prior art of above-mentioned accessing operation is less.
In addition, during consecutive access operation, if when the address pointer be stored in stream registers enters page boundary region (the boundary zone) of the page be stored in stream registers, to look ahead (pre-fetch) data of another page near this page, thus when crossing over page boundary, data can consecutive access, and without the need to waiting for the page wait cycle at page boundary place.Page boundary region can be the N bit in page boundary front.Such as, N can be 16 or 32.
In one embodiment, the stream start-up operation for multiple data stream can (successively) be initiated successively.Can decide based on the reception order of stream enabled instruction for the sequence of operation of the startup of the plurality of data stream and page access operations.In addition, before terminating for the startup of data stream and page access operations, the consecutive access operation for data stream cannot perform.In addition, if when the consecutive access operation for data stream is initiated, the stream start-up operation of this data stream and page access operations not yet complete, then can suspend vector (pending vector) by exporting in SPI flash memory one, informing that SPI controller and/or primary processor (host processor) operation do not complete.As mentioned above, such as, operate for the stream start-up operation of the first data stream, the stream start-up operation for the second data stream, the stream start-up operation for the 3rd data stream, the consecutive access for the first data stream, operate for the consecutive access of the second data stream, operate for the consecutive access of the first data stream, the consecutive access operation for the 3rd data stream and the consecutive access operation for the first data stream initiate successively.Therefore, compared with prior art, the initiation of the operation of multiple data stream is more efficient, and the processing time shortens relatively.
Fig. 5 shows the block schematic diagram of SPI controller 50 according to an embodiment of the invention, and wherein SPI controller 50 performs the access control method being used for SPI flash memory 60.SPI controller 50 is coupled to primary processor 30, SPI controller 50 by host processor bus 35 and is coupled to primary memory 40, and is coupled to SPI flash memory 60 by spi bus 56.SPI flash memory 60 comprises flash memory array and supports multiple data stream (being 8 data stream in the present embodiment).SPI controller 50 accessible site is in primary processor 30, or accessible site is in the part of outside SPI interface being coupled to primary processor 30.SPI controller 50 receives the access instruction of host processor 30, with the accessing operation of control SPI flash memory 60.Data (the write data WD of Tathagata autonomous memory 40) to be written are sent to SPI flash memory 60 by SPI controller 50, or the data read in SPI flash memory 60 are sent to primary processor 30.
SPI controller 50 comprises steering logic 500, stream registers group 510, multiplexer (multiplexers) 521,522 and 523, serial/parallel converter 530 and input/output (i/o) buffer 540, wherein stream registers group 510 comprises stream registers 511 ~ 518, serial/parallel converter 530 comprises and walks to and encloses interface (Quad Peripheral Interface all round, QPI) converter 531 and QPI are to parallel converters 532, and input/output (i/o) buffer 540 comprises three-state buffer (tri-state buffer) 541 and impact damper 542.Each stream registers of stream registers group 510 stores the instruction of the corresponding data stream of multiple data stream, state and address information.Instruction stored in each stream registers of stream registers group 510 is coupled to multiplexer 521, and in each stream registers being stored in stream registers group 510, stored address information is coupled to multiplexer 522.Multiplexer 521 exports instruction/state CS of having selected to steering logic 500, and multiplexer 522 exports the address information ADD that the selected input end to multiplexer 523.Another input end of multiplexer 523 receives the write data WD of the SPI flash memory 60 to be written of autonomous memory 40.Primary memory 40 can comprise the data buffer for multiple data stream, as data buffer 410 ~ 480.The output of multiplexer 523 is coupled to and walks to QPI converter 531, and and walks to QPI converter 531 and be coupled to three-state buffer 541.Steering logic 500 is coupled to multiplexer 521,522 and 523, to select the instruction of multiple data stream, state, address information according to the access instruction carrying out host processor 30 and to write data.Steering logic 500 also controls serial/parallel converter 530 and three-state buffer 541.Reading data from SPI flash memory 60 are sent to impact damper 542 by spi bus 56, and in being after this sent to QPI to parallel converters 532.QPI exports to parallel converters 532 and reads data RD, and has read data RD and be sent to primary processor 30 by host processor bus 35.
The assembly of steering logic 500 control SPI controller 50 is with the accessing operation of control SPI flash memory 60.The address information of stream enabled instruction and this data stream that steering logic 500 sends the data stream be used in multiple data stream, to SPI flash memory 60, performs stream start-up operation for this data stream and page access operations with control SPI flash memory 60 according to stream enabled instruction and address information.Stream enabled instruction comprises the access type of data stream and the identification code of data stream.Address information comprises page address and the address pointer of the page of the flash memory array of SPI flash memory 60.When the access type instruction read operation of data stream, according to stream enabled instruction and page address, steering logic 500 control SPI flash memory 60 is by reading data in flash memory to the stream registers in the SPI flash memory 60 corresponding to this data stream.Alternatively, when the access type instruction write operation of data stream, according to stream enabled instruction, the data storing of flash memory array to be written enters corresponding to the stream registers in the SPI flash memory 60 of this data stream by steering logic 500 control SPI flash memory 60.The details of stream start-up operation and page access operations has described as above, for purpose of brevity, repeats no more herein.
Steering logic 500 further transmission is used for the consecutive access instruction of data stream to SPI flash memory 60, operates with the consecutive access that control SPI flash memory 60 performs for data stream.Consecutive access instruction comprises the identification code of data stream.When the access type instruction read operation of data stream, according to address pointer stored in the stream registers corresponded in the SPI flash memory 60 of this data stream, steering logic 500 control SPI flash memory 60 exports data to SPI controller 50 by the stream registers corresponded in the SPI flash memory 60 of this data stream, and address pointer increases after data export.Alternatively, when the access type instruction write operation of data stream, according to page address stored in the stream registers corresponded in the SPI flash memory 60 of this data stream and address pointer, data stored in the stream registers corresponded in the SPI flash memory 60 of this data stream are write flash memory array by steering logic 500 control SPI flash memory 60, and address pointer increases after the data writing is finished.The details of consecutive access operation and address pointer has described as above, for purpose of brevity, repeats no more herein.
When address pointer stored in the stream registers in the SPI flash memory 60 corresponding to this data stream enters the page boundary region of this page, steering logic 500 can be looked ahead near the data of another page corresponding to the page stored in the stream registers in the SPI flash memory 60 of this data stream by control SPI flash memory 60 further.Therefore, when crossing over page boundary, data can consecutive access, without the need to waiting for the page wait cycle at page boundary place.Page boundary region can be the N bit in page boundary front.Such as, N can be 16 or 32.
Note that the SPI controller 50 in Fig. 5 is only better citing, the present invention is not as limit.Such as, SPI controller 50 can comprise the signal generation unit for generation of signal further, as serial clock signal generation unit.
Fig. 6 shows the block schematic diagram of SPI storer 60 according to an embodiment of the invention.Multiple data stream (being 8 data stream in the present embodiment) supported by SPI storer 60, and comprise steering logic 600, stream registers group 610, multiplexer 620, page cache memory 630, input/output (i/o) buffer 640, order register 650, address register 660, data register 670 and memory core 680, wherein stream registers group 610 comprises stream registers 611 ~ 618, input/output (i/o) buffer 640 comprises impact damper 641 and three-state buffer 642, memory core 680 comprises flash memory array 682, row (row) demoder 684 and row (column) demoder 686.Steering logic 600 performs accessing operation according to the assembly of the instruction and information control SPI flash memory 60 that are received from SPI controller 50.Input/output (i/o) buffer 640 is coupled to spi bus 56.Order register 650, address register 660 and data register 670 are coupled to impact damper 641.Address register 660 and data register 670 are coupled to memory core 680 further.The instruction for data stream being received from SPI controller 50 is temporarily stored in order register 650, and then sends and be stored to the corresponding stream registers in stream registers group 610.The address information being received from the data stream of SPI controller 50 is temporarily stored in address register 660, and then sends and be stored to the corresponding stream registers in stream registers group 610.When the consecutive access operation for data stream is initiated, be sent to address register 660 corresponding to address information stored in the stream registers of this data stream, thus consecutive access operation can perform according to this address information.The data being received from the flash memory array to be written 682 of SPI controller 50 are temporarily stored in data register 670, and then send and be stored to the corresponding stream registers in stream registers group 610.When the continuous write operation for data stream is initiated, be sent in data register 670, to write flash memory array 682 corresponding to data stored in the stream registers of this data stream.
Steering logic 60 receive from SPI controller 50 for the stream enabled instruction of the data stream in multiple data stream and the address information for this data stream, and perform the stream start-up operation and page access operations that are used for this data stream according to the assembly of this stream enabled instruction and address information control SPI flash memory 60.Stream enabled instruction comprises the access type of this data stream and the identification code of this data stream.Address information comprises page address and the address pointer of the page of flash memory array 682.Access type and the address information received are stored in corresponding to the stream registers in the stream registers group 610 of this data stream.When access type instruction read operation, according to stream enabled instruction and page address, steering logic 600 control SPI flash memory 60 is by reading data in flash memory array 682 to page cache memory 630, then, according to the identification code of this data stream, the page data in page cache memory 630 sends and is stored to corresponding to the stream registers in the stream registers group 610 of this data stream.Alternatively, when access type instruction write operation, according to stream enabled instruction, the data storing of flash memory array 682 to be written enters corresponding to the stream registers in the stream registers group 610 of this data stream by steering logic 600 control SPI flash memory 60.The details of stream start-up operation and page access operations has described as above, for purpose of brevity, repeats no more herein.
Steering logic 600 receives the consecutive access instruction for data stream from SPI controller 50 further, and the consecutive access that control SPI flash memory 60 performs for this data stream operates.Consecutive access instruction comprises the identification code of data stream.When the access type instruction read operation of data stream, according to address pointer stored in the stream registers corresponded in the stream registers group 610 of this data stream, steering logic 600 control SPI flash memory 60 exports data to three-state buffer 642 by the stream registers corresponded in the stream registers group 610 of this data stream, and steering logic 600 increases address pointer after data export.Alternatively, when access type instruction write operation, according to page address stored in the stream registers corresponded in the stream registers group 610 of this data stream and address pointer, data stored in the stream registers corresponded in the stream registers group 610 of this data stream are write flash memory array 682 by steering logic 600 control SPI flash memory 60.Consecutive access operation and address pointer have described as above, for purpose of brevity, repeat no more herein.
When being stored in the address pointer in stream registers and entering the page boundary region of the page stored in stream registers, the data pre-fetching near another page of this page enters stream registers.Therefore, when crossing over page boundary, data can consecutive access, and without the need to waiting for the page wait cycle at page boundary place.Page boundary region can be the N bit in page boundary front.Such as, N is 16 or 32.
Note that above-mentioned SPI flash memory and SPI controller backwards-compatible (backward compatible).Such as, in one embodiment, the accessing operation of high amount of traffic amount (data traffic), accessing operation if any pass startup (booting) and the data about multiple data block are downloaded or data Replica (copy), can perform according to above-mentioned access protocol, the accessing operation of other small data flows can perform according to known access protocol.
As mentioned above, the invention provides multiple data stream serial flash memory device and multiple data stream access protocol thereof, efficiently to initiate the operation of data stream and to shorten the processing time.
Although the present invention discloses as above with preferred embodiment; so itself and be not used to limit the present invention, any those skilled in the art, without departing from the spirit and scope of the present invention; when doing a little change and retouching, therefore protection scope of the present invention is when being as the criterion depending on the accompanying claim person of defining.
Claims (12)
1. an access method, for serial peripheral interface flash memory, wherein said serial peripheral interface flash memory comprises flash memory array and supports multiple data stream, and described access method comprises:
Receive stream enabled instruction, for the data stream in described multiple data stream, wherein said stream enabled instruction comprises access type and the identification code of described data stream;
Receiver address information, wherein said address information comprises page address and the address pointer of the page of described flash memory array; And
According to described stream enabled instruction and described page address, by reading data in described flash memory array to the stream registers corresponding to described data stream, or according to described stream enabled instruction, the data storing of described flash memory array to be written is entered in the described stream registers corresponding to described data stream.
2. access method according to claim 1, is characterized in that comprising further:
Receive consecutive access instruction, for described data stream, wherein said consecutive access instruction comprises the described identification code of described data stream; And
According to described access type and described address pointer, described data are exported by corresponding in the described stream registers of described data stream, or described data are write described flash memory array;
Wherein said address pointer exports in described data or increases after write.
3. access method according to claim 2, is characterized in that comprising further:
When described address pointer enters the page boundary region of the described page, look ahead near the data of another page of the described page.
4. an access control method, for serial peripheral interface flash memory, wherein said serial peripheral interface flash memory comprises flash memory array and supports multiple data stream, and described access method comprises:
Send stream enabled instruction to described serial peripheral interface flash memory, wherein said stream enabled instruction is used for the data stream in described multiple data stream, and described stream enabled instruction comprises access type and the identification code of described data stream;
Send address information to described serial peripheral interface flash memory, wherein said address information comprises page address and the address pointer of the page of described flash memory array; And
According to described stream enabled instruction and described page address, control described serial peripheral interface flash memory by reading data in described flash memory array to the stream registers corresponding to described data stream, or according to described stream enabled instruction, control described serial peripheral interface flash memory and the data storing of described memory array to be written is entered described stream registers corresponding to described data stream.
5. access control method according to claim 4, is characterized in that comprising further:
Send consecutive access instruction to described serial peripheral interface flash memory, wherein said consecutive access instruction is used for described data stream, and described consecutive access instruction comprises the described identification code of described data stream; And
According to described access type and described address pointer, control described serial peripheral interface flash memory and export described data by corresponding in the described stream registers of described data stream, or described data are write described flash memory array;
Wherein, described address pointer exports in described data or increases after write.
6. access control method according to claim 5, is characterized in that comprising further:
When described address pointer enters the page boundary region of the described page, control described serial peripheral interface flash memory and look ahead near the data of another page of the described page.
7. a serial peripheral interface flash memory, supports multiple data stream, and described serial peripheral interface flash memory comprises:
Flash memory array;
Multiple stream registers, each stream registers corresponds to one in described multiple data stream; And
Steering logic, be coupled to described flash memory array and described multiple stream registers, receive stream enabled instruction and the address information of the data stream be used in described multiple data stream, wherein said stream enabled instruction comprises access type and the identification code of described data stream, and described address information comprises page address and the address pointer of the page of described flash memory array;
Wherein, data are according to described stream enabled instruction and described page address by the stream registers read in described flash memory array corresponding to described data stream, or data are stored in the described stream registers corresponding to described data stream according to described stream enabled instruction.
8. serial peripheral interface flash memory according to claim 7, be characterised in that, described steering logic receives the consecutive access instruction for described data stream further, described consecutive access instruction comprises the described identification code of described data stream, wherein, data are according to described access type and described address pointer by exporting in the described stream registers corresponding to described data stream or writing described flash memory array, and described steering logic exports in described data or increases described address pointer after write.
9. serial peripheral interface flash memory according to claim 8, is characterised in that, the data near another page of the described page are looked ahead when described address pointer enters the page boundary region of the described page.
10. a serial peripheral interface controller, be coupled to serial peripheral interface flash memory, to control the accessing operation of described serial peripheral interface flash memory, wherein said serial peripheral interface flash memory comprises flash memory array, and support multiple data stream, described serial peripheral interface controller comprises:
Steering logic, send stream enabled instruction and the address information extremely described serial peripheral interface flash memory of the data stream be used in described multiple data stream, wherein said stream enabled instruction comprises access type and the identification code of described data stream, and described address information comprises page address and the address pointer of the page of described flash memory array, and described steering logic controls described serial peripheral interface flash memory by reading data in described flash memory array to the stream registers corresponding to described data stream according to described stream enabled instruction and described page address, or the data storing of described flash memory array to be written to be entered the described stream registers corresponding to described data stream according to described stream enabled instruction by described steering logic.
11. serial peripheral interface controllers according to claim 10, be characterised in that, described steering logic sends the consecutive access instruction extremely described serial peripheral interface flash memory for described data stream further, wherein said consecutive access instruction comprises the described identification code of described data stream, and described steering logic controls described serial peripheral interface flash memory according to described access type and described address pointer and exports described data to described serial peripheral interface controller or described data are write described flash memory array by the described stream registers corresponding to described data stream, wherein said address pointer exports in described data or increases after write.
12. according to the serial peripheral interface controller described in claim 11, be characterised in that, when described address pointer enters the page boundary region of the described page, described steering logic controls described serial peripheral interface flash memory and looks ahead near the data of another page of the described page.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| IN2016/MUM/2013 | 2013-06-13 | ||
| IN2016MU2013 IN2013MU02016A (en) | 2013-06-13 | 2013-06-13 |
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| CN104238957B CN104238957B (en) | 2018-03-09 |
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| CN201310712743.7A Active CN104238957B (en) | 2013-06-13 | 2013-12-23 | SPI controller, SPI flash memory and its access method and access control method |
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| Country | Link |
|---|---|
| CN (1) | CN104238957B (en) |
| BR (1) | BR102013022935A2 (en) |
| IN (1) | IN2013MU02016A (en) |
| TW (1) | TWI534615B (en) |
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Also Published As
| Publication number | Publication date |
|---|---|
| TW201447573A (en) | 2014-12-16 |
| IN2013MU02016A (en) | 2015-06-05 |
| TWI534615B (en) | 2016-05-21 |
| BR102013022935A2 (en) | 2015-07-28 |
| CN104238957B (en) | 2018-03-09 |
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