CN107370578B - Multi-redundancy Ethernet controller based on hardware fast autonomous switching - Google Patents
Multi-redundancy Ethernet controller based on hardware fast autonomous switching Download PDFInfo
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Abstract
A multi-redundancy Ethernet controller based on hardware fast autonomous switching comprises a bus protocol controller, wherein the bus protocol controller is connected with a DMA controller module, an interrupt management module, a PHY monitoring management module and a control/status register module in a bidirectional mode; the DMA controller module is connected with the descriptor access control module in a bidirectional way, and is respectively connected with the redundancy switching management module through the sending control module and the receiving control module, and the redundancy switching management module is connected with a plurality of MAC protocol controllers which are arranged in parallel; the DMA controller module, the descriptor access control module, the redundancy switching management module and the MAC protocol controller are all connected with the control/status register module in a bidirectional mode, and the descriptor access control module is connected with the sending control module and the receiving control module in a bidirectional mode. The invention not only improves the reliability and fault tolerance of the product by increasing the redundancy, but also improves the switching speed by combining the interrupt switching mode and the query switching mode.
Description
Technical Field
The invention relates to the field of data communication, in particular to a multi-redundancy Ethernet controller based on hardware fast autonomous switching.
Background
Redundant ethernet is suitable for applications with high requirements on reliability and fault tolerance. At present, the redundancy mode which is applied more is double redundancy, the used double redundancy Ethernet system is mostly divided into two types, one type is switching through upper layer driving software, the switching speed can reach 30 ms-90 ms, the switching efficiency is low, the switching condition is single, and the software burden is heavy; the other method is to replace upper-layer software switching by hardware switching, and obtain link state information of a PHY state register when a PHY chip sends an error warning (interrupt mode) to control link switching, but PHY chips of different brands have different characteristics and interrupt initiation speeds are greatly different at different network speeds, and the switching performance of the mode depends on the performance of an external PHY chip, so that the switching speed can only reach 1ms to 5ms, for example, patent "dual redundant ethernet media access controller IP core based on FPGA" (patent number CN 105406998A). Taking 88E1111 of a conventional PHY chip MARVELL as an example, when the speed is in a hundred mega mode, the interruption can be reflected immediately when the link state changes, but when the speed is in a giga mode and the link state changes, the interruption reflection time is not fixed, about several tens of millimeters or even higher, and at this time, the switching speed of 1ms to 5ms cannot be achieved at all.
Disclosure of Invention
The present invention is directed to solve the above problems in the prior art, and an object of the present invention is to provide a hardware-based fast autonomous switching multi-redundancy ethernet controller, which not only improves the reliability and fault tolerance of the product by increasing redundancy, but also combines an interrupt switching manner and an inquiry switching manner to implement nanosecond-level redundancy channel switching.
In order to achieve the purpose, the invention adopts the technical scheme that: the system comprises a bus protocol controller connected with an external processor through a system bus, wherein the bus protocol controller is connected with a DMA controller module used for controlling the data transmission process of DMA blocks in a two-way manner, an interrupt management module used for generating an interrupt output or cancellation instruction, a PHY monitoring management module used for carrying out function configuration and real-time monitoring on an external PHY chip, and a control/status register module which can receive and transmit data according to setting information and return working status information to the external processor; the DMA controller module is connected with the descriptor access control module in a bidirectional way, and is respectively connected with the redundancy switching management module through the sending control module and the receiving control module, and the redundancy switching management module is connected with a plurality of MAC protocol controllers which are arranged in parallel; the DMA controller module, the descriptor access control module, the redundancy switching management module and the MAC protocol controller are all connected with the control/status register module in a bidirectional mode, and the descriptor access control module is connected with the sending control module and the receiving control module in a bidirectional mode.
And a sending buffer module is arranged between the sending control module and the redundancy switching management module, and a receiving buffer module is arranged between the receiving control module and the redundancy switching management module.
The sending buffer module has a 4KB sending buffer, and the receiving buffer module has a 16KB receiving buffer.
The PHY monitoring management module is connected with an external PHY chip register management interface.
And each MAC protocol controller is connected with the GMII or MII interface of the external PHY chip.
The DMA block data transfer rate supports 10/100/1000Mbps adaptation.
The switching time of the redundant channel is less than 1 microsecond.
The functions that the MAC protocol controller can realize include MAC layer data framing in the sending process, MAC layer data frame analysis in the receiving process, CRC (cyclic redundancy check) generation of data, CDMA/CD (code division multiple Access/compact disc) function, data validity check and address filtering.
Compared with the prior art, the bus protocol controller realizes system bus protocol conversion, supports flow control, and automatically inserts and unloads a lead code and a start frame identifier, and automatically inserts and unloads a CRC check code and filling, and the lead code and frame interval can be set in a programmable way, and can independently acquire the state of an external PHY chip. The Ethernet controller can be used for processing a multi-redundancy Ethernet data link layer protocol and a media access layer digital part, completes nanosecond-level redundancy channel switching, provides a standard external interface and is convenient for constructing a terminal system. Because the redundancy switching control is independent of the MAC protocol control, the invention only needs to increase the number of the MAC protocol controllers according to the redundancy number and does not need to modify the design framework aiming at different requirements of reliability and fault tolerance, and the working reliability is high. The protocol processing is completely realized by hardware logic language, the sending/receiving delay is about 6.5/2.5us respectively, and DMA block data transmission is adopted, so that the data transmission efficiency is high, and the data processing capability is strong.
Drawings
FIG. 1 is a functional block diagram of the system of the present invention;
in the drawings: 1. a bus protocol controller; a DMA controller module; 3. a descriptor access control module; 4. a transmission control module; 5. a receiving control module; 6. a transmission buffer module; 7. a receiving buffer module; 8. a redundant switching management module; 9, MAC protocol controller A; 10, a MAC protocol controller B; MAC protocol controller N; 11. a control/status register module; 12. an interrupt management module; PHY monitoring management module; 14. a system bus; 15. GMII or MII interface of external PHY chip; 16. an external PHY chip register management interface.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings.
Referring to fig. 1, the ethernet controller of the present invention structurally includes a system bus 14, a GMII or MII interface 15 for an external PHY chip, and an external PHY chip register management interface 16. The bus protocol controller 1 interacts data and control information with the controller. The bus protocol controller 1 completes system bus data communication protocol processing and bus master-slave mode operation control, responds to the access of an external processor to the control/status register module 11, and generates a block data transmission time sequence according to a DMA access control signal output by the DMA controller module 2.
The DMA controller module 2 is used for process control during DMA block data transmission, and after receiving the control information of the control/status register module 11, the DMA controller module 2 reads the descriptor from the system memory initialized by the external processor through the bus protocol controller 1, and then reads frame data to be transmitted from the system memory initialized by the external processor or fills the received frame data into the system memory according to the content of the descriptor, thereby realizing DMA block data transmission under the coordination of each control module.
The descriptor access control module 3 controls the DMA controller module 2 to initiate DMA operations, performs DMA block transfer of send/receive descriptors with an external system, transfers control information to the send control module 4 and the receive control module 5 according to the obtained descriptor contents, and returns the states of the send control module 4 and the receive control module 5 to the DMA controller module 2 and the control/state register module 11.
The transmission control module 4 controls the DMA controller module 2 to initiate a DMA operation, and carries the transmission frame data and the transmission descriptor from the external system memory, and stores the transmission frame data in the transmission buffer module 6.
The receiving control module 5 controls the DMA controller module 2 to initiate DMA operation, obtains the received data in the receiving buffer module 7, and carries the received data and the receiving descriptor to the external system memory, after the data transmission is completed, sets a status flag, and applies for the completion of receiving interrupt to the external processor through the interrupt management module 12.
The PHY monitoring management module 13 is connected to an external PHY chip through an external PHY chip register management interface 16, and is mainly used for an external system to perform function configuration on the external PHY chip through the bus protocol controller 1 during the initialization process of the controller. And the external PHY is monitored in real time in the communication process, and when the physical link state changes, the PHY state is automatically accessed and the external link state is returned to the redundancy switching management module 8.
The redundancy switching management module 8 is mainly used for redundancy autonomous switching and redundancy management control. According to the configuration information of the control/status register module 11, if the current configuration is the autonomous switching mode, when the redundant network link status changes, the link status returned by the PHY monitoring management module 13 is intelligently switched to one of the communication channels from the MAC protocol controller a to the MAC protocol controller N with a good link status. In the process of sending frame data, the redundancy switching management module 8 reads data to be sent in the sending buffer module 6, performs redundancy scheduling according to an autonomous switching result, transmits the frame data to one of the optimized link MAC protocol controller a to the optimized link MAC protocol controller N, sets a status flag after judging that the data transmission of the optimized link is completed, and applies for sending completion interrupt to the external processor through the interrupt management module 12. In the frame data receiving process, the redundancy switching management module 8 performs redundancy scheduling according to the autonomous switching result, transmits the frame data received by the preferred link from the MAC protocol controller a to the MAC protocol controller N to the receiving buffer module 7, and discards the channel data that is not preferred. If the current configuration is a manual switching mode, in the frame data sending process, the redundancy switching management module 8 reads data to be sent in the sending buffer module 6, performs redundancy scheduling according to the configuration information of the control/status register module 11, transmits the frame data to one of the manually configured link MAC protocol controller a to the MAC protocol controller N, sets a status flag after data transmission is judged to be completed, and applies for sending completion interrupt to the external processor through the interrupt management module 12. In the process of receiving frame data, the redundancy switching management module 8 performs redundancy scheduling according to the configuration information of the control/status register module 11, transmits the received frame data of the manually configured link to the receiving buffer module 7, and discards non-preferred channel data at the same time.
The MAC protocol controllers a to N are used for MAC layer protocol control in the ethernet data communication process, including MAC layer data framing in the transmission process, MAC layer data frame parsing in the reception process, frame filtering, and the like, and perform protocol processing on frame data processed by the transmission control module 4, the reception control module 5, the transmission buffer module 6, and the reception buffer module 7 to generate a data stream conforming to the ethernet protocol specification, and perform data interaction with an external PHY chip through the GMII or MII interface 15 of the external PHY chip. The number of the MAC protocol controllers can be automatically modified according to the requirements of users, the N MAC protocol controllers have the same function, and the increase and decrease of the redundant channels can be completed only by increasing and decreasing the number of instantiations of the MAC protocol controllers.
The control/status register module 11 outputs user setting information to the corresponding module, controls data transceiving and protocol control, and returns the operating status of the controller to the external processor.
The interrupt management module 12 communicates with the outside through the bus protocol controller 1, and generates effective interrupt output when the corresponding interrupt condition in the control/status register module 11 is satisfied; and when the interrupt cancellation condition is met, the external output interrupt is invalid.
According to the scheme, a logic design of the controller is described by using a Verilog HDL language, and logic synthesis and layout wiring are completed; meanwhile, a terminal system is designed, the controller is designed and mapped into the programmable logic device to be realized, and the functions of the controller are tested. The test result shows that the invention has good implementability and the performance meets the expectation.
Claims (5)
1. A many redundant ethernet controller based on fast autonomic switching of hardware characterized in that: the system comprises a bus protocol controller (1) connected with an external processor through a system bus (14), wherein the bus protocol controller (1) is bidirectionally connected with a DMA controller module (2) used for controlling the data transmission process of DMA blocks, an interrupt management module (12) used for generating an interrupt output or cancellation instruction, a PHY monitoring management module (13) used for carrying out function configuration on an external PHY chip and monitoring in real time, and a control/status register module (11) which can receive and transmit data according to setting information and return working status information to the external processor; the DMA controller module (2) is connected with the descriptor access control module (3) in a bidirectional mode, the DMA controller module (2) is connected with the redundancy switching management module (8) through the sending control module (4) and the receiving control module (5) respectively, and the redundancy switching management module (8) is connected with a plurality of MAC protocol controllers which are arranged in parallel; the DMA controller module (2), the descriptor access control module (3), the redundancy switching management module (8) and the MAC protocol controller are all connected with a control/status register module (11) in a bidirectional way, and the descriptor access control module (3) is connected with a sending control module (4) and a receiving control module (5) in a bidirectional way;
the PHY monitoring management module (13) is connected with an external PHY chip register management interface (16);
each MAC protocol controller is connected with a GMII or MII interface (15) of an external PHY chip;
the switching time of the redundant channel is less than 1 microsecond;
the PHY monitoring management module is a physical link state real-time monitoring module;
the physical link state real-time monitoring module autonomously dynamically collects all external physical link states in real time according to a switching mode pre-configured by the control/state register module (11); when the switching mode is configured as an interrupt switching mode, the external link state changes, including the link disconnection or the link disconnection, the physical layer chip PHY generates the interrupt, the physical link state real-time monitoring module automatically responds and processes the external interrupt, and collects the link state information; when the switching mode is configured to be the query switching mode, the physical link state real-time monitoring module automatically collects link state information in real time according to the configured switching speed;
the redundancy switching management module (8) manages the redundancy backup path data according to a pre-configured switching mode and a switching mode; if the current configuration is an autonomous hardware switching mode, comprehensively considering all external physical link states collected by the physical link state real-time monitoring module in real time, intelligently switching to one of the communication channel MAC protocol controller A to the MAC protocol controller N with good link state when the external physical link is abnormal, and performing redundancy scheduling according to an autonomous switching result; when the controller normally works, only one path works, the rest bypasses are used as backups to keep a silent state, the physical link state real-time monitoring module monitors and collects link state information in real time, and the backup paths with good states wait to be called at any time; in the process of sending frame data, a redundancy switching management module (8) reads data to be sent in a sending buffer module (6), performs redundancy scheduling according to an autonomous switching result, and transmits the frame data to one of an optimal link MAC protocol controller A and an optimal link MAC protocol controller N; in the process of receiving frame data, a redundancy switching management module (8) performs redundancy scheduling according to an autonomous switching result, transmits the frame data received by a preferred link from an MAC protocol controller A to an MAC protocol controller N to a receiving buffer module (7), and discards non-preferred channel data; if the current configuration is the upper software switching mode, in the frame data sending process, the redundancy switching management module (8) reads data to be sent in the sending buffer module (6), performs redundancy scheduling according to the configuration information of the control/status register module (11), and transmits the frame data to one path from the link MAC protocol controller A to the MAC protocol controller N configured by the upper software; in the process of receiving frame data, the redundancy switching management module (8) performs redundancy scheduling according to the configuration information of the control/status register module (11), transmits the received frame data of the upper-layer software configuration link to the receiving buffer module (7), and discards non-preferred channel data at the same time.
2. The hardware fast autonomous switching based multi-redundant ethernet controller of claim 1, wherein: and a sending buffer module (6) is arranged between the sending control module (4) and the redundancy switching management module (8), and a receiving buffer module (7) is arranged between the receiving control module (5) and the redundancy switching management module (8).
3. The hardware fast autonomous switching based multi-redundant ethernet controller of claim 2, wherein: the sending buffer module (6) is provided with a 4KB sending buffer area, and the receiving buffer module (7) is provided with a 16KB receiving buffer area.
4. The hardware fast autonomous switching based multi-redundant ethernet controller of claim 1, wherein: the DMA block data transfer rate supports 10/100/1000Mbps adaptation.
5. The hardware fast autonomous switching based multi-redundant ethernet controller of claim 1, wherein: the functions that the MAC protocol controller can realize include MAC layer data framing in the sending process, MAC layer data frame analysis in the receiving process, CRC (cyclic redundancy check) generation of data, CDMA/CD (code division multiple Access/compact disc) function, data validity check and address filtering.
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| CN108259127B (en) * | 2017-12-08 | 2021-02-19 | 天津津航计算技术研究所 | PCIE dual-redundancy ten-gigabit network IP core |
| CN108173756A (en) * | 2017-12-18 | 2018-06-15 | 天津津航计算技术研究所 | A kind of dual redundant ethernet mac state health control method |
| CN110224846B (en) * | 2018-03-01 | 2022-01-25 | 中兴通讯股份有限公司 | Service protection method based on flexible Ethernet, server and storage medium |
| CN109946955B (en) * | 2019-03-15 | 2022-11-01 | 西安微电子技术研究所 | Linux network card driving controller of dual-network redundant Ethernet controller |
| CN113709013A (en) * | 2021-09-09 | 2021-11-26 | 天津津航计算技术研究所 | 6U-CPCI gigabit network module with dual-redundancy switching function for localization |
| CN114064550A (en) * | 2021-11-27 | 2022-02-18 | 积成电子股份有限公司 | Multi-CPU communication system and method based on FPGA and EMAC/GMAC controller |
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