CN107144821B - Efficient receiving channel based on time delay beam forming in broadband digital array radar - Google Patents

Efficient receiving channel based on time delay beam forming in broadband digital array radar Download PDF

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CN107144821B
CN107144821B CN201710222859.0A CN201710222859A CN107144821B CN 107144821 B CN107144821 B CN 107144821B CN 201710222859 A CN201710222859 A CN 201710222859A CN 107144821 B CN107144821 B CN 107144821B
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邹林
赫肯约翰逊
钱璐
丁凯
周云
于雪莲
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University of Electronic Science and Technology of China
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    • G—PHYSICS
    • G01—MEASURING; TESTING
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Abstract

Compared with a group of sub-filter groups of each receiving channel in a traditional receiving channel structure, the invention is based on the design of a channel filter of a Farrow structure, so that each receiving channel uses the same L +1 sub-filter groups, and the complexity of the whole structure is greatly reduced; because the multiple channels share one group of sub-filters, the frequency response characteristic of the whole receiving channel can be reconstructed only by modifying the fractional delay factor in the fractional delay module, and the flexibility of the system is better.

Description

Efficient receiving channel based on time delay beam forming in broadband digital array radar
Technical Field
The invention belongs to a signal processing technology, and particularly relates to a technology for extracting and time delay synchronous adjustment of multiple receiving channels in a broadband digital array radar.
Background
In order to obtain higher range resolution and improve the identification capability of targets, the wideband digital array radar WBDAR is developed. The broadband signal is adopted to acquire the target information, and the capability of identifying and distinguishing the target is improved while the higher distance resolution is acquired. But also makes WBDAR require large angle electronic scanning over an area using real delay lines TTD instead of phase shifters. Compared with the traditional TTD simulation method, the method adopting the digital delay filter reduces the extra insertion loss, provides continuously variable accurate delay for ensuring that the broadband wave beam faces to the target in any direction, and greatly makes up for the defects of analog delay compensation.
In recent years, with the rapid development of analog and digital chips, the implementation of WADAR has become feasible. But the high signal speed processing speed and the large hardware resource consumption increase the complexity and cost of the system, thereby limiting the implementation of WBDAR. Therefore, how to optimize the system structure and reduce the complexity of the processing procedure is still the focus of research.
In the conventional WBDAR receiving channel, the main structure usually includes a microwave amplifier LNA, a high-speed analog-to-digital conversion ADC module, a quadrature local oscillator mixing unit NCO (NCO), a signal extraction module (subtraction), an amplitude and phase weighting module (Magnitude)&Phase Weighting), integer Delay module (Unit Delay), variable fractional Delay VFD filter as shown in fig. 1. The M times signal extraction module is composed of an anti-aliasing filter and an extraction module. The signal decimation and the design of the VFD filter become key factors to improve the efficiency and reconfigurability of the system. In a traditional channel receiving structure, an antenna receiving signal passes through a microwave amplifier LNA to output a radio frequency signal and then is sampled by an ADC (analog to digital converter) so as to increase a dynamic range and reduce phase noise of a receiver, the sampled signal passes through frequency mixing of a quadrature local oscillator and then is extracted by an extraction module so as to reduce a signal data rate, and the intermediate amplitude weighting and phase weighting are used for suppressing a receiving beam side lobe and compensating a phase difference caused by a time difference of arrival of a multi-channel radio frequency signal. Finally, the delay and the division are carried out through an integerAnd the time delay VFD module outputs corresponding signals finally. The VFD filter adopts Farrow structure, as shown in FIG. 2, and consists of L +1 FIR sub-filters Gk(z) L delay units and L adders, dkIs the fractional delay factor, k is 0,1,2 …, L. It should be noted that the decimation and VFD filter modules are separated, which increases the complexity of the system to some extent, reduces the working efficiency of the system, and has poor reconfigurability.
In a digital signal processing system, the number of multipliers and adders becomes the main resource consumption of the whole hardware, and considering that the system can work at different frequencies, the complexity of the system is evaluated by using multiplication rate and addition rate ratio, wherein the multiplication rate R ismIs represented as follows:
Figure GDA0002243595710000021
wherein M is a decimation factor, CmIs the number of multipliers. Similarly, the addition rate RaIs represented as follows:
Figure GDA0002243595710000022
wherein C isaIs the number of adders.
In the conventional WBDAR channel receiving structure, the number of multipliers C is one stage of extractionmoAnd the number of adders CaoThe following were used:
Cmo＝N[N1+2+3+(L+1)(Ns+1)+2L], (3)
Cao＝N[2N1+5+2Ns(L+1)+2L]+2N-2, (4)
wherein N is1Is the order of the pre-decimation anti-aliasing filter, NsThe order of the sub-filter in the VFD filter is shown, L is the number of parallel branches of a Farrow structure in the VFD filter, N is the number of the whole receiving channels, only even-numbered anti-aliasing filters and odd-numbered sub-filters are considered, and other orders are similar to the order of the sub-filter.
Considering the case of 2-level decimation, RmoAnd RaoIs represented as follows:
Figure GDA0002243595710000023
Figure GDA0002243595710000024
wherein N isiWhere i is 1 and 2 represents the order of the anti-aliasing filter before 1-stage decimation and 2-stage decimation, respectively, and M isiI is 1,2 represents the decimation factor in 1-stage decimation and 2-stage decimation, respectively, and the decimation factor M is M for the whole receiving channel1M2。
From the above analysis, it can be seen that in the conventional receiving channel structure, neither the complexity nor the efficiency is ideal, and there is room for further optimization, and at the same time, its reconfigurability and flexibility are not sufficient, which is also a place to be further improved.
Disclosure of Invention
The invention aims to solve the technical problem of providing a high-efficiency, flexible and reconfigurable receiving channel structure in a broadband digital array radar.
The invention adopts the technical scheme that an efficient receiving channel formed based on a time delay wave beam in a broadband digital array radar comprises N paths of receiving channels, 2 primary adders and 2 groups of FIR sub-filter groups, wherein N paths of I signal outputs in the N paths of receiving channels are connected with the input ends of the 1 primary adders, N paths of Q signals in the N paths of receiving channels are connected with the input ends of the other 1 primary adders, and the output ends of the primary adders are respectively connected with the input ends of the corresponding 1 group of FIR sub-filter groups; the I signal and the Q signal represent mutually orthogonal signals; each receiving channel comprises an analog-to-digital converter, an integer time delay module, an orthogonal local oscillator frequency mixing unit, a multiphase decomposition module, a fraction time delay module, 2 secondary adders and a weighting module; the output end of the analog-to-digital converter is connected with the input end of the integer delay module, the output end of the integer delay module is connected with the input end of the orthogonal local oscillator frequency mixing unit, the I signal and the Q signal of the orthogonal local oscillator frequency mixing unit are connected with the input end of the I signal and the Q signal of the fractional delay module through the multiphase decomposition module, the I signal output end of the fractional delay module is connected with 1 second-stage adder, the Q signal output end of the fractional delay module is connected with the other 1 second-stage adder, the output ends of 2 second-stage adders are connected with the input end of the weighting module, the I signal output in the weighting module is the I signal output of the receiving channel of the path, and the Q signal output in the weighting module is the Q signal output of.
Compared with a group of sub-filter groups of each receiving channel in the traditional receiving channel structure, the invention uses the same L +1 sub-filter groups for each receiving channel based on the design of the channel filter of the Farrow structure, thereby greatly reducing the complexity of the whole structure; because the multiple channels share one group of sub-filters, the frequency response characteristic of the whole receiving channel can be reconstructed only by modifying the fractional delay factor in the fractional delay module, and the flexibility of the system is better.
The invention has the advantages of lower structure complexity, stronger flexibility and reconfigurability.
Drawings
FIG. 1 is a schematic diagram of a conventional WBDAR receiving channel structure;
FIG. 2 is a Farrow basic structure;
FIG. 3 is a schematic diagram of a channel filter in the design process of the present invention;
FIG. 4 is a schematic diagram of a receiving channel structure according to the present invention.
Detailed Description
The key part of the invention comprises a fractional delay extractor based on Farrow structure and the design of a channel filter matched with the fractional delay extractor.
The general structure of the embodiment is as shown in fig. 4, and includes N receiving channels, 2 first-stage adders, and 2 sets of FIR sub-filters, where N I signal outputs in the N receiving channels are connected to input terminals of 1 first-stage adder, N Q signals in the N receiving channels are connected to input terminals of another 1 first-stage adder, and output terminals of the first-stage adder are respectively connected to input terminals of 1 corresponding set of FIR sub-filters; the I signal and the Q signal represent mutually orthogonal signals;
each receiving channel comprises an analog-to-digital converter, an integer time delay module, an orthogonal local oscillator frequency mixing unit, a multiphase decomposition module, a fraction time delay module, 2 secondary adders and a weighting module; the output end of the analog-to-digital converter is connected with the input end of the integer delay module, the output end of the integer delay module is connected with the input end of the orthogonal local oscillator frequency mixing unit, the I signal and the Q signal of the orthogonal local oscillator frequency mixing unit are connected with the input end of the I signal and the Q signal of the fractional delay module through the multiphase decomposition module, the I signal output end of the fractional delay module is connected with 1 second-stage adder, the Q signal output end of the fractional delay module is connected with the other 1 second-stage adder, the output ends of 2 second-stage adders are connected with the input end of the weighting module, the I signal output in the weighting module is the I signal output of the receiving channel of the path, and the Q signal output in the weighting module is the Q signal output of;
the channel filter consists of a fractional delay module, a secondary adder and an FIR sub-filter group, as shown in FIG. 3;
the M-path multiphase decomposition module is used for completing M-path multiphase decomposition and mainly has the main function of reducing the speed of each path of signal to 1/M of the original speed; the channel filter comprises M fractional delay weighting modules, and each phase decomposition factor comprises L +1 parallel multiplication factors
Figure GDA0002243595710000041
Where M is 0,1,2 …, M-1 denotes M factors of the polyphase decomposition, k is 0,1,2 …, and L denotes parallel L +1 multiplication factors in each decomposition path. The two-stage adder is used for adding and summing the respective L +1 paths of parallel branch signals in the M paths of the polyphase decomposition.
G for transfer function of FIR sub-filter groupk(z) denotes, k is 0,1,2 …, L, wherein each Gk(z) is the transfer function of one of the sub-FIR filters. If the channel filter needs to be matched with the fractional delay extractor structure, reasonable fractional delay factors and impulse responses of the channel filter need to be set.
Ideally, the frequency response of the channel filter is expressed as follows:
Figure GDA0002243595710000042
wherein N iscFor the order of the whole channel filter, w is the angular frequency, T is the time variable, wsTo cut off the angular frequency, wsT is pi/M, M is a decimation factor, and d is a fractional delay coefficient of the whole channel. The transfer formula of the multiphase decomposition structure of the whole channel is as follows:
Figure GDA0002243595710000043
where M is a branching variable of the polyphase decomposition, M is 0,1, M-1, z is a z variable, Hm(zM) Is the branch formula for each branch. Here, the multiphase decomposition can be realized by using a Farrow structure as shown in fig. 2, and the transfer formula is:
Figure GDA0002243595710000044
wherein d iskFractional delay factor, G, for the kth parallel branchk(z) is the transfer function of the sub-filter bank in the z transform domain;
therefore, the entire channel multiphase decomposition structure transfer formula (7) can be rewritten as:
Figure GDA0002243595710000045
wherein the content of the first and second substances,
Figure GDA0002243595710000046
for the multi-phase decomposition of the fractional delay factor corresponding to the kth parallel branch in every mth path, M is 0,1, M-1, k is 0,1,2 …, L.
One order of NsThe relation between the FIR sub-filter and the number M of polyphase decomposition branches and the order N of the whole channel filter can be usedExpressed by the following equation:
N＝(Ns+1)M-1 (11)
in conjunction with equations (7), (8) and (11), one can derive:
Figure GDA0002243595710000047
bringing (11) into (12) can result in:
Figure GDA0002243595710000048
wherein d ismFor the fraction delay factor of the mth path of the polyphase decomposition, d is the fraction delay of the entire channel. At this time, the impulse response of each branch after the polyphase decomposition of the whole channel filter can be obtained as follows:
Figure GDA0002243595710000051
wherein N is 0,1 …, N1，m＝0,1…,M-1，N1Order of the Farrow structure sub-filter, gk(n) is the sub-filter time-domain impulse response function.
The complexity of the structure of the invention can be expressed by the number of multipliers and adders of the system, and the result is as follows:
Cmn＝2NLM+3N(L+1)+(Ns+1)(L+1), (15)
Can＝2N(L+1)(M-1)+5N(L+1)+2(N-1)(L+1)+2(L+1)Ns+2L (16)
therefore, the high-efficiency receiving channel structure based on the time delay beam forming, which is designed and obtained by the invention, greatly reduces the realization complexity of the receiving channel structure in the traditional broadband digital array radar. When N is 8, M is 2, Ns＝5，N1＝26，N2When L is equal to 3 and 0, the conventional multiplication rate and addition rate of the receive channel structure are respectively R as can be derived from the formulas (3) and (4)mo＝244，Rao419, and the receiving channel structure of the present invention satisfies the same configuration when N is equal to Ns＝13Then, R can be obtained from the equations (15) and (16)mn＝124，Ran195, which is obviously superior to the traditional structure. The number of the multipliers and the adders is reduced, the times of multiplication and addition operations needing to be completed in unit time are greatly reduced, and the complexity of system implementation is reduced.
By designing the multiphase decomposition module and the channel filter matched with the multiphase decomposition module, the flexibility and the reconfigurability of the whole receiving channel structure are greatly increased. The traditional channel receiving structure needs to be configured with a large number of filter parameters, decomposition factors and fractional delay factors in advance, and the flexibility and the reconfigurability of the whole receiving structure are limited. The structure of the invention replaces the traditional anti-aliasing filter and VFD structure by designing a proper channel filter based on the polyphase decomposition and Farrow structure, reduces the parameter setting, has higher flexibility, and can change the frequency response of the channel only by modifying the fractional delay weighting parameter of the channel filter.
The whole receiving channel structure is realized by the following steps:
step one, a multi-phase decomposition module and a channel filter are arranged to replace the functions of a traditional anti-aliasing filter and a VFD structure. The signal is first decomposed by an M-way polyphase and then enters the designed channel filter. The ideal frequency response function of the channel filter is given by equation (7), and is designed according to the impulse response of equation (14). The parameter setting of the channel filter comprises three parts, namely, the setting of the fractional delay factor in the channel filter, and the corresponding fractional delay factor d can be solved by referring to a formula (13)m(ii) a Second, sub-filter group Gk(z) order setting Ns(ii) a Third is a sub-filter group Gk(z) coefficient setting. And the fractional delay module and the weighting module perform fractional delay weighting on the M groups of L +1 paths of signals, and the signals are summed and combined to generate L +1 paths of signals.
Step two, configuring a receiving channel structure, a low noise amplifier module LNA, a data acquisition module ADC and an integer Delay module (Unit Delay D)0) Sequentially connected in series, and then passes through a quadrature local oscillator frequency mixing unit to reach a multiphase decomposition module.
Thirdly, the signals passing through the multiphase decomposition module and the fractional delay module are weighted by amplitude and phase (weighting W)n) And then generating an L +1 path signal, wherein N is 0,1, and N-1.
And step four, after the setting of one receiving channel is finished, setting the rest N-1 receiving channel structures, wherein each receiving channel structure is set according to the step one to the step three. And finally, summing and combining the N (L +1) paths of signals of the N paths of receiving channels through a first-stage adder to generate L +1 paths of signals, dividing the L +1 paths of signals into I, Q paths of signals, and enabling the signals to enter the L +1 sub-filter groups respectively corresponding to the signals, so that the N paths of channels share one sub-filter group.
Through the steps, two paths of orthogonal output signals y meeting the requirements can be obtainedI，yq。

Claims (1)

1. The high-efficiency receiving channel based on time delay beam forming in the broadband digital array radar is characterized by comprising N paths of receiving channels, 2 primary adders and 2 groups of FIR sub-filter groups, wherein N paths of I signal outputs in the N paths of receiving channels are connected with the input ends of the 1 primary adders, N paths of Q signals in the N paths of receiving channels are connected with the input ends of the other 1 primary adders, and the output ends of the primary adders are respectively connected with the input ends of the corresponding 1 group of FIR sub-filter groups; the I signal and the Q signal represent mutually orthogonal signals; each receiving channel comprises an analog-to-digital converter, an integer time delay module, an orthogonal local oscillator frequency mixing unit, a multiphase decomposition module, a fraction time delay module, 2 secondary adders and a weighting module; the output end of the analog-to-digital converter is connected with the input end of the integer delay module, the output end of the integer delay module is connected with the input end of the orthogonal local oscillator frequency mixing unit, the I signal and the Q signal of the orthogonal local oscillator frequency mixing unit are connected with the input end of the I signal and the Q signal of the fractional delay module through the multiphase decomposition module, the I signal output end of the fractional delay module is connected with 1 second-stage adder, the Q signal output end of the fractional delay module is connected with the other 1 second-stage adder, the output ends of 2 second-stage adders are connected with the input end of the weighting module, the I signal output in the weighting module is the I signal output of the receiving channel of the path, and the Q signal output in the weighting module is the Q signal output of;
the fractional delay factor of the fractional delay module is:
wherein d ismThe fractional delay factor of the mth path of the multi-phase decomposition is adopted, d is the fractional delay of the whole channel, M is the extraction factor of the whole channel filter, M is the branch variable of the multi-phase decomposition of the extraction module, and M is 0,1, M-1; the channel filter consists of a fractional time delay module, a secondary adder and an FIR sub-filter group;
after the channel filter is subjected to polyphase decomposition, the impulse response h (Mn + m) of the polyphase branch filter obtained is expressed by a Farrow structure as follows:
Figure FDA0002243595700000012
wherein N issThe order n of the Farrow structure FIR sub-filter is 0,1, Ns, M is 0,1, M-1, gk(n) is the FIR sub-filter time-domain impulse response function,
Figure FDA0002243595700000013
and (3) a fraction delay factor corresponding to the kth parallel branch of the mth path is decomposed in a multi-phase mode, wherein M is 0 and 1, M-1, k is 0 and 1 and 2, and L is the number of parallel branches of the Farrow structure in the channel filter.
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