CN107046542B - Method for realizing consensus verification by adopting hardware at network level - Google Patents
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L63/00—Network architectures or network communication protocols for network security
- H04L63/20—Network architectures or network communication protocols for network security for managing network security; network security policies in general
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
- H04L41/30—Decision processes by autonomous network management units using voting and bidding
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- H—ELECTRICITY
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- H04L67/00—Network arrangements or protocols for supporting network services or applications
- H04L67/01—Protocols
- H04L67/10—Protocols in which an application is distributed across nodes in the network
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- H—ELECTRICITY
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Abstract
The invention discloses a method for realizing consensus verification by adopting hardware at a network level, which utilizes a hardware device FPGA as a node, wherein the FPGA nodes are connected point to point by realizing a TCP/IP protocol, and ARP, ICMP and DHCP are adopted to assist the interaction of the TCP/IP protocol and other FPGA nodes, thereby shortening TCP/IP stack and effectively reducing time delay. The FPGA node adopts a block chain consensus protocol such as PBFT/SBFT/RBFT and other propagation messages to perform consensus, selects a leader node, and sends feedback of the received information and votes after other nodes receive the consensus messages. The consensus protocols are encrypted and attached with digital signatures in the transmission process, so that the safety of data is guaranteed. The invention realizes the consensus protocol on the hardware platform without adding a data center, effectively shortens the time delay and achieves the purpose of accelerating the consensus of the hardware.
Description
Technical Field
The invention belongs to the technical field of block chains, and particularly relates to a method for realizing consensus verification by adopting hardware at a network level.
Background
Under current stringent efficiency requirements, data centers face the need for greater and greater data volumes and workload complexities. To meet the goals of high performance, scalability, and scalability, services typically run on hundreds to thousands of machines. This requires some cooperative consensus to maintain machine consistency. The inevitable performance overhead and the additional resources required tend to reduce the consistency, resulting in fewer users having to build more complex applications to handle the potential inconsistencies. The high cost of consistency comes from the multiple rounds of communication required to reach the agreement, and the traditional network stack does not optimize for time delays or specific communication modes, making acceleration of consensus protocols a bottleneck.
Today, various types of hardware are currently an increasingly feasible option to improve system performance at low energy costs. In addition to considering performance and efficiency, for an intelligent network, a node may be added to the network, and a middleware is used to customize its application, so to use a consensus as an attribute of the network, rather than just make it implemented on an application layer, it is a good choice to find a balance point in the complexity of implementation and the throughput achievable by the middleware, and adding a blockchain consensus protocol to the network to improve the system efficiency, such as a consensus protocol such as PBFT (Practical Byzantine Fault Tolerance algorithm)/SBFT (Simple Byzantine Fault Tolerance algorithm, simplified Byzantine Fault Tolerance algorithm)/RBFT (Redundant Byzantine Fault Tolerance algorithm), while FPGA (Field Programmable Gate Array) has a low power consumption characteristic, and is not limited by a conventional CPU in terms of data processing, and can reduce the delay time in the above, by expanding the function of the middleware or adding cheap consensus to the network processing nodes, the value of the consensus protocol is more popularized to the network.
Disclosure of Invention
In view of the above, the invention provides a method for implementing consensus verification by adopting hardware at a network level, which implements block chain consensus protocols such as PBFT/SBFT/RBFT on an FPGA without increasing the capacity of a data center, and reduces time delay.
A method for realizing consensus verification by adopting hardware at a network level comprises the following steps:
(1) constructing a system operation framework for realizing consensus verification by adopting an FPGA at a network level;
(2) the FPGA nodes are connected point to point by executing a TCP/IP (Transmission Control Protocol/Internet Protocol) Protocol;
(3) the FPGA node adopts ARP (Address Resolution Protocol), ICMP (Internet Control Message Protocol) and DHCP (Dynamic host configuration Protocol) to assist the interaction of the TCP/IP Protocol and other FPGA nodes, shorten the TCP/IP stack and enable the FPGA to be in a real network;
(4) the FPGA node converts the data message into a message format meeting the requirement of a consensus protocol;
(5) and the FPGA nodes adopt a PBFT, SBFT or RBFT block chain consensus protocol to transmit and broadcast the data messages, and other FPGA nodes send feedback and vote after receiving the feedback.
The specific implementation method of the step (1) comprises the following steps: a certain amount of FPGA is arranged in a network as a node, a channel exists between any two FPGA nodes for interaction, each FPGA node realizes data transmission between a plurality of pairs of ports at the same time by connecting a switch, and the FPGA node releases the memory space of a DRAM (dynamic random access memory) for consensus and application logic execution by utilizing the characteristic of small buffer area of an internal BRAM (embedded block RAM).
The specific implementation method of the step (2) is as follows: dynamically allocating TCP sessions by an internal buffer area of the FPGA node, so that the request data of a client side is smaller than the size of an Ethernet MTU (Maximum Transmission Unit); the FPGA node only retransmits with other nodes, and the overtime setting between the FPGA node and the client is not considered, so that the stack pressing of TCP is reduced; the network protocol is realized through hardware, two real data flow channels are allowed to be established correspondingly to realize the isolation of a sending path and a receiving path, the two channels do not influence each other, and the connection state is shared through a data structure.
The data structure comprises a session lookup table, a port state table, and an event engine supported by a timer; the session lookup table comprises an IP address, a destination address and a source port, and the FPGA is used as a content addressable memory when in implementation; the port state table is used for tracking the state of each TCP port and storing state information for each opened TCP connection; the event engine is responsible for managing the activities and sending requests incoming by the interface and instructing the corresponding output engine to work.
The specific implementation method of the step (3) is as follows: point-to-point communication is carried out among FPGA equipment, if data is lost due to insufficient buffer space or line interruption, a report is sent to the source end of the data through ICMP, and a relevant event receiver sends a retransmission request notice; when sending data packet, if the sender does not have the MAC address of the receiver but knows the IP address of the receiver, a message requesting the MAC address of the receiver is broadcasted; a DHCP server allocates an idle IP address for the FPGA node and stamps an effective timestamp; when sending and receiving data on protocols of ARP, ICMP and DHCP, the application program uses conversation to communicate with the network stack, and then directly forwards the data to the network module of the specific application program; during the direct propagation of data packets over ethernet, the sequence number is used to detect if data is lost, which increases with the increase of logical requests.
The specific implementation method of the step (4) is as follows: dividing the data message into required modules, representing transmitted Metadata by Metadata, and representing a Payload by Payload; the components in the protocol are specified, Signature is used for representing the digital Signature of the interaction between the node and the node, Timestamp is used for representing the Timestamp of the message, and Cert is used for representing the certificate required by the FPGA for adding the network registration. After the message format is standardized, the identification data such as a block chain consensus protocol PBFT/SBFT/RBFT and the like are facilitated.
The specific implementation method of the step (5) is as follows: on the premise that an FPGA node added into a network generates a registration certificate, a leader node is selected first, a data message to be broadcasted is generated into a summary by the leader node through a Hash function SHA-256, then a random number nonce is generated, ECDSA (elliptic curve digital signature algorithm) calculation is carried out by a hardware encryption module, a signature to the summary is generated, and then a PBFT, SBFT or RBFT block chain consensus protocol is adopted to transmit and broadcast the signed data message; and after receiving the data information, other FPGA nodes verify whether the signature is of a data sender, determine the validity of the data, send a feedback notice of the received information and vote the data.
The invention chooses to implement the consensus protocol on hardware rather than adding more data centers in order to improve consistency without degrading performance. The invention realizes PBFT/SBFT/RBFT and other block chain consensus protocols on a hardware FPGA system, creates a reusable scheme capable of adding middleware or intelligent network hardware, and can process TCP/IP network protocols and specific network protocol work by using hardware or hardware platforms which gradually start to appear. The FPGA can access logs in a DRAM chip under most conditions, read a cache memory head and is suitable for being implemented on FPGA hardware by block chain consensus protocols such as PBFT/SBFT/RBFT and the like.
In the conventional algorithm, the payload from the TCP flow must fill the entire MTU packet size, so waiting for more data to fill up must be done for a while, and each request that is smaller than the MTU size is delayed for a while by a timeout. In the solution of the present invention, the client request is always smaller than the size 1500B of the ethernet MTU, which can better shorten the time delay.
Drawings
FIG. 1 is a schematic diagram of interaction between nodes.
Fig. 2 is a schematic diagram of the overall structure of FPGA hardware.
FIG. 3 is a diagram of a TCP stack.
Detailed Description
In order to more specifically describe the present invention, the following detailed description is provided for the technical solution of the present invention with reference to the accompanying drawings and the specific embodiments.
In the embodiment, three pieces of FPGA hardware equipment are arranged as nodes, and the nodes use FPGA evaluation boards which are provided with a plurality of Ethernet interfaces. The system is divided into three modules, namely a network protocol module, a message format modification module and a block chain consensus protocol module, and the whole hardware structure is shown in figure 1.
The channels exist between every two nodes for interaction, a switch can be used for data transmission between a plurality of port pairs at the same time, each FPGA is provided with a corresponding BRAM module, the BRAM buffer area is small, delay can be reduced without affecting performance, DRAM memory space is released for consensus and application logic execution, and therefore a large-capacity DRAM buffer area is reserved, and the whole hardware structure is shown in figure 2. The nodes are connected point to point by executing a TCP/IP protocol, a buffer area inside the FPGA dynamically allocates TCP sessions, the request of the client is smaller than the MTU size of the Ethernet, the FPGA only retransmits with other FPGAs without considering the overtime setting between the FPGA and the client, and the stack pressing of the TCP is reduced.
In the network protocol module, a TCP protocol and a plurality of application protocols are adopted, in order to reduce time delay and reduce occupied storage space in the TCP protocol, a hardware-implemented network protocol allows a real data stream channel to be established and separates a sending path and a receiving path, so that the two channels do not affect each other, and the two channels share a connection state through a data structure. The data structures comprise a session lookup table, a port table, a state table and an event engine supported by a timer, wherein the session lookup table comprises a quadruple mapping session ID which is used as a content addressable memory for the FPGA; the port table tracks the state of each TCP port and stores information for each open TCP connection state table; the event engine is responsible for managing the activities and sending requests incoming by the interface and instructing the corresponding TX engine to work.
The BRAM internal buffer is divided into several FIFOs (First Input First Output), the TCP session is dynamically allocated, and when the BRAM buffer can determine that a complete request is available in a FIFO queue, it is forwarded to the application logic. If all FIFO queues are full, the retransmission mechanism of TCP is relied upon to retransmit the data in order not to lose any data. The client requests are always smaller than the MTU size of the Ethernet, and after the timeout setting is removed, the requests are transmitted in different layers without being divided due to different MTU sizes except mutual retransmission between the FPGA and other FPGAs. In the application protocol, data packets are directly transmitted on the Ethernet, and whether data is lost or not is detected by using the sequence number, wherein the sequence number is increased along with the increase of the logic request. The FPGA equipment carries out point-to-point communication, if data is lost due to insufficient buffer space or line interruption, a receiver sends a notice of a retransmission request, and when the data is sent and received on the protocol, the application program uses a session when communicating with a network stack so that the data are directly forwarded to a network module specific to the application program; the TCP stack structure is shown in figure 3.
In the message format conversion module, data is divided into required modules, Metadata represents transmitted Metadata, and Payload represents Payload. The components in the common recognition protocol are normalized, a Signature represents a digital Signature interacted between the node and the node, a Timestamp represents a Timestamp finished by the message, and a Cert represents a certificate required by the network registration added by the FPGA.
In the block chain consensus protocol module, the FPGA node transmits messages such as PBFT/SBFT/RBFT by adopting a block chain consensus protocol, and other nodes send feedback of the received information and vote after receiving the consensus messages. On the premise that the FPGA node added into the network generates the registration certificate, namely, the FPGA node enters the network as a legal node. Numbering the three FPGA nodes with numbers 0, 1 and 2, firstly, performing modulus operation on 3 (three FPGA nodes) according to the block height, and selecting a leader node according to the obtained remainder, namely the number corresponding to the FPGA. The leader node generates a summary of the data message needing to be broadcast after the message format is normalized by using a hash function SHA-256, then generates a random number nonce, performs ECDSA calculation by using a hardware encryption module, generates a signature for the summary, and submits a certificate to other nodes. After receiving the data information, other nodes verify whether the signature is the data sender through the random number nonce, determine the validity of the data, and then perform feedback notification of the received information and perform voting work on the data.
The embodiments described above are presented to enable a person having ordinary skill in the art to make and use the invention. It will be readily apparent to those skilled in the art that various modifications to the above-described embodiments may be made, and the generic principles defined herein may be applied to other embodiments without the use of inventive faculty. Therefore, the present invention is not limited to the above embodiments, and those skilled in the art should make improvements and modifications to the present invention based on the disclosure of the present invention within the protection scope of the present invention.
Claims (2)
1. A method for realizing consensus verification by adopting hardware at a network level comprises the following steps:
(1) a system operation framework for realizing consensus verification by adopting an FPGA (field programmable gate array) at a network level is constructed, and the specific realization method comprises the following steps: arranging a certain amount of FPGA in a network as nodes, wherein channels exist between any two FPGA nodes for interaction, each FPGA node realizes data transmission between multiple pairs of ports at the same time by connecting a switch, and the FPGA nodes release DRAM memory space for execution of consensus and application logic by utilizing the characteristic that an internal BRAM buffer area of the FPGA node is small;
(2) the FPGA nodes are connected point to point by executing a TCP/IP protocol, and the specific implementation method is as follows: dynamically distributing TCP sessions by an internal buffer area of the FPGA node to enable client request data to be smaller than the size of an Ethernet MTU; the FPGA node only retransmits with other nodes, and the overtime setting between the FPGA node and the client is not considered, so that the stack pressing of TCP is reduced; the network protocol is realized through hardware, two real data flow channels are allowed to be established to correspondingly realize the isolated sending and receiving paths, the two channels do not influence each other, and the connection state is shared through a data structure;
(3) the FPGA node adopts ARP, ICMP and DHCP to assist TCP/IP protocol to interact with other FPGA nodes, shortens TCP/IP stack, and makes FPGA in real network, the concrete realization method is: point-to-point communication is carried out among FPGA equipment, if data is lost due to insufficient buffer space or line interruption, a report is sent to the source end of the data through ICMP, and a relevant event receiver sends a retransmission request notice; when sending data packet, if the sender does not have the MAC address of the receiver but knows the IP address of the receiver, a message requesting the MAC address of the receiver is broadcasted; a DHCP server allocates an idle IP address for the FPGA node and stamps an effective timestamp; when sending and receiving data on protocols of ARP, ICMP and DHCP, the application program uses conversation to communicate with the network stack, and then directly forwards the data to the network module of the specific application program; in the process of directly transmitting the data packet on the Ethernet, detecting whether the data is lost or not by using the sequence number, wherein the sequence number is increased along with the increase of the logic request;
(4) the FPGA node converts the data message into a message format meeting the requirement of a consensus protocol, and the specific implementation method comprises the following steps: dividing the data message into required modules, representing transmitted Metadata by Metadata, and representing a Payload by Payload; the method comprises the steps of standardizing components in a consensus protocol, representing a digital Signature of interaction between a node and the node by using Signature, representing a Timestamp of a message by using Timestamp, and representing a certificate required by adding network registration to an FPGA by using Cert;
(5) on the premise that an FPGA node added into a network generates a registration certificate, a leader node is selected firstly, a data message to be broadcasted is generated into a summary by the leader node through a Hash function SHA-256, then a random number nonce is generated, ECDSA calculation is carried out by a hardware encryption module, a signature of the summary is generated, and then a PBFT, SBFT or RBFT block chain consensus protocol is adopted to transmit and broadcast the signed data message; and after receiving the data information, other FPGA nodes verify whether the signature is of a data sender, determine the validity of the data, send a feedback notice of the received information and vote the data.
2. The method of claim 1, wherein: the data structure comprises a session lookup table, a port state table, and an event engine supported by a timer; the session lookup table comprises an IP address, a destination address and a source port, and the FPGA is used as a content addressable memory when in implementation; the port state table is used for tracking the state of each TCP port and storing state information for each opened TCP connection; the event engine is responsible for managing the activities and sending requests incoming by the interface and instructing the corresponding output engine to work.
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