CN106484367A - Common recognition computing chip, equipment, system and mainboard - Google Patents
Common recognition computing chip, equipment, system and mainboard Download PDFInfo
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- CN106484367A CN106484367A CN201610810949.7A CN201610810949A CN106484367A CN 106484367 A CN106484367 A CN 106484367A CN 201610810949 A CN201610810949 A CN 201610810949A CN 106484367 A CN106484367 A CN 106484367A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
Abstract
The present invention relates to technical field of information processing, disclose a kind of common recognition computing chip, equipment, system and mainboard.In the present invention, common recognition computing chip is on-site programmable gate array FPGA chip, and common recognition computing chip includes：Memory module and computing module；Memory module is connected with computing module；The machine code of common recognition computational algorithm passes through sintering curing in a storage module, and computing module is used for carrying out knowing together according to the machine code of the common recognition computational algorithm in memory module calculating.Present invention also offers a kind of common recognition computing device, a kind of common recognition computing system and a kind of mainboard.In embodiment of the present invention, improve calculatings performance and the ratio of power consumption that common recognition calculates, can improve and calculate performance it is possible to energy efficient.
Description
Technical field
The present invention relates to technical field of information processing, particularly to a kind of common recognition computing chip, equipment, system and mainboard.
Background technology
Block chain (BlockChain) technology is a kind of emerging skill occurring in financial technology (FinTech) field in recent years
Art, the attribute such as its unique decentration, information can not be distorted, multinode collective maintainability, publicity, secret protection, in base
In incredible the Internet, the believable trading information data of offer can be recorded.
Proof of work algorithm in block chain knows together calculating it is ensured that the anti-tamper characteristic of block chain, and its essence exists
In being realized using multi-layer H ash algorithm.Block chain proof of work computing is generally calculated using standard CPU, also adopts
Calculated with standard GPU.
However, during realizing the present invention, inventor finds that in prior art, at least there are the following problems：Due to mark
Quasi- CPU not only carries steerable system, also carries various application programs, and this makes the internal memory ratio for proof of work computing
Less, and the energy consumption ratio of CPU is larger, leads to the ratio calculating performance with consuming energy not high.
Content of the invention
The purpose of embodiment of the present invention is to provide a kind of common recognition computing chip, equipment, system and mainboard, improves altogether
Know the ratio of the calculatings performance calculating and power consumption, can improve and calculate performance it is possible to energy efficient.
For solving above-mentioned technical problem, embodiments of the present invention provide a kind of common recognition computing chip, described common recognition meter
Calculation chip is on-site programmable gate array FPGA chip, and described common recognition computing chip includes：Memory module and computing module；Described
Memory module is connected with described computing module；The machine code of common recognition computational algorithm passes through sintering curing in described memory module,
Described computing module is used for carrying out common recognition calculating according to the machine code of the common recognition computational algorithm in described memory module.
Embodiments of the present invention additionally provide a kind of mainboard, including：Interface chip and above-mentioned common recognition computing chip；Institute
State interface chip to be connected with described common recognition computing chip；Described interface chip is used for receiving the calculating ginseng of described common recognition computational algorithm
Number, and it is transferred to the computing module in described common recognition computing chip；Described computing module is common with described according to described calculating parameter
Know computational algorithm and carry out common recognition calculating.
Embodiments of the present invention additionally provide a kind of common recognition computing device, including：Above-mentioned mainboard.
Embodiments of the present invention additionally provide a kind of common recognition computing system, including：Terminal is calculated with above-mentioned common recognition and sets
Standby；Described common recognition computing device is connected with described terminal；Described terminal includes：Interface, drive module, acquisition module and transmission mould
Block；Described interface chip is docked with described interface；Described drive module is used for driving described common recognition computing device；Described acquisition mould
Block, for obtaining calculating parameter；Described sending module, the calculating parameter for obtaining described acquisition module passes through described interface
Chip sends to described computing module.
In terms of existing technologies, common recognition computing chip adopts fpga chip to realize to embodiment of the present invention, specifically,
In fpga chip, sintering has the machine code of common recognition computational algorithm, and can execute common recognition according to the machine code of common recognition computational algorithm
Calculate.So, it is used alone fpga chip execution common recognition to calculate, not only can improve calculating performance, can be carried with reducing energy consumption
The ratio of the calculatings performance that high common recognition calculates and power consumption, and, above-mentioned common recognition computing chip, computing device of knowing together and mainboard body
Long-pending little it is easy to integrated.
In addition, in one embodiment, the Hash Hash complicated dynamic behaviour formula of described machine code can be：
SHA256M(Start N)<Target；
Wherein, SHA256 is SHA, and operation result is 256, and Start is initial value, and N is integer, described
Start is spliced with described N phase；Described Target is desired value；M is Hash operation number of times, from the beginning of second Hash operation, often
The input of Hash operation is the output of last Hash operation.Embodiment of the present invention can be obtained little by successive ignition
Hash complexity in desired value.
In addition, in one embodiment, also sinter stride in described memory module and control machine code；Described stride controls
Machine code is used for controlling the amplification of described N.In present embodiment, the stride in memory module controls machine code can control N's
Amplification, so, by controlling the amplification of N, can adjust the calculating speed of Hash complexity.
In addition, in one embodiment, the amplitude such as described stride controls machine code to include from control machine code with non-
Constant amplitude is from control machine code；Described computing module according to first choice parameter call etc. amplitude from control machine code
When, the stride that described computing module carries out common recognition calculating is the integer more than 1；In described computing module according to the second selection parameter
Call non-constant amplitude from control machine code when, described computing module carry out know together calculate stride according to default non-constant amplitude step
Width ordered series of numbers carries out common recognition and calculates；Wherein, described first choice parameter, described second selection parameter respectively with etc. amplitude from control
Machine code, non-constant amplitude correspond from control machine code.In embodiment of the present invention, computing module can be according to first choice
Parameter transfers constant amplitude from control machine code, or transfers non-constant amplitude from control machine code according to the second selection parameter.So,
During common recognition calculates, constant amplitude can be transferred from control machine code or non-constant amplitude from increasing according to specific selection parameter
Control machine code, and then improve computing module and carry out the efficiency calculating of knowing together.
Brief description
Fig. 1 is the structure chart of common recognition computing chip according to a first embodiment of the present invention；
Fig. 2 is the structure chart of common recognition computing chip according to a second embodiment of the present invention；
Fig. 3 is the flow chart of common recognition computational algorithm according to a second embodiment of the present invention；
Fig. 4 is the structured flowchart of mainboard according to a third embodiment of the present invention；
Fig. 5 is the structure chart of common recognition computing device according to a fourth embodiment of the present invention；
Fig. 6 is the structure chart of common recognition computing system according to a fifth embodiment of the present invention.
Specific embodiment
For making the object, technical solutions and advantages of the present invention clearer, below in conjunction with each reality to the present invention for the accompanying drawing
The mode of applying is explained in detail.However, it will be understood by those skilled in the art that in each embodiment of the present invention,
In order that reader more fully understands that the application proposes many ins and outs.But, even if there is no these ins and outs and base
In following embodiment many variations and modification it is also possible to realize the application technical scheme required for protection.
The first embodiment of the present invention is related to a kind of common recognition computing chip, as shown in figure 1, this common recognition computing chip 100
It can be FPGA (field programmable gate array) chip.The calculation that fpga chip executes calculating task is parallel computation, meter
Calculate speed fast.
Common recognition computing chip 100 can include memory module 101 and computing module 102.Wherein, memory module 101 and meter
Calculate module 102 to connect.
The machine code of common recognition computational algorithm can be by sintering curing in memory module 101, and computing module 102 is according to depositing
The machine code of the common recognition computational algorithm in storage module 101 carries out common recognition and calculates.Specifically, common recognition computational algorithm is with the shape of program
Formula forms machine code through forms such as a series of encryptions, and this machine code can be by the storage of sintering curing to common recognition computing chip
In module 101, and then, the computing module 102 in common recognition computing chip, can be calculated according to the common recognition in memory module 101 and calculate
The machine code of method carries out common recognition and calculates.
Compared with prior art, common recognition computing chip adopts fpga chip to realize, and specifically, sintering in fpga chip has
The machine code of common recognition computational algorithm, and can be calculated according to the machine code execution common recognition of common recognition computational algorithm.So, it is used alone
Fpga chip execution common recognition calculates, and not only can improve calculating performance, can be with reducing energy consumption, and it is computational that raising common recognition calculates
Can with the ratio of power consumption, and, above-mentioned common recognition computing chip small volume is it is easy to integrated.
Second embodiment of the present invention is related to a kind of common recognition computing chip, as shown in Fig. 2 common recognition computing chip 100 can
Think fpga chip, this common recognition computing chip includes：Memory module 101 and computing module 102.And memory module 101 with
Computing module 102 is connected.The machine code 201 of common recognition computational algorithm passes through sintering curing in memory module 101, computing module
102 are used for carrying out common recognition calculating according to the machine code 201 of the common recognition computational algorithm in memory module 101.So, it is used alone
Fpga chip execution common recognition calculates, and not only can improve calculating performance, can be with reducing energy consumption, and it is computational that raising common recognition calculates
Can with the ratio of power consumption, and, above-mentioned common recognition computing chip small volume is it is easy to integrated.
Specifically, Hash (Hash) the complicated dynamic behaviour formula of common recognition computational algorithm machine code is：
SHA256M(Start N)<Target；
Wherein, SHA256 is SHA, and operation result is 256, and Start is initial value, and N is integer, initially
Value Start is spliced with N phase；Target is desired value；M is Hash operation number of times, from the beginning of second Hash operation, breathes out each time
The input of uncommon computing is the output of last Hash operation.
As M=1, Hash complicated dynamic behaviour formula is：
SHA256(Start N)<Target；
As M=2, Hash complicated dynamic behaviour formula is：
SHA256(SHA256(Start N))<Target；
As M=3, Hash complicated dynamic behaviour formula is：
SHA256(SHA256(SHA256(Start N)))<Target；
Specifically, the parameter pre-entering has initial value Start and desired value Target, and wherein, initial value Start can
Think the character string of indefinite length, desired value Target can be fixing 256bit signless integer.Hash complicated dynamic behaviour
In formula, initial value Start and N can be with using string-concatenation mode, it would however also be possible to employ the mode such as numeral addition.
Memory module 101 in common recognition computing chip 100 can also sinter stride and control machine code, and this stride controls machine
Code can be used for controlling the amplification of N.Specifically, can be according to the actual need of default objectives value Target and user
Ask, control N to adopt the amplitude of which kind of mode to increase.
Stride controls machine code can include constant amplitude from control machine code 202 and non-constant amplitude from control machine code 203,
Common recognition computing chip 100 in computing module 102 according to first choice parameter call constant amplitude from control machine code 202 when, meter
The stride that calculation module 102 carries out common recognition calculating is the integer more than 1.Called non-according to the second selection parameter in computing module 102
Constant amplitude from control machine code 203 when, computing module 102 carry out know together calculate stride enter according to the stride of default non-constant amplitude
Row common recognition calculate, wherein, first choice parameter, the second selection parameter respectively with etc. amplitude from control machine code, non-constant amplitude from
Control machine code corresponds.Specifically, can prestore in memory module 101 first choice parameter, the second selection parameter
With constant amplitude from control machine code 202, non-constant amplitude from control machine code 203 one-to-one relationship, this corresponding relation can be
One data list.When the selection parameter from user is the first parameter, computing module 102 is looked into according to described data list
Table, the amplitude such as selects from control machine code, and according to select etc. amplitude control from control machine code calculate when N stride
Amplification.
When computing module 102 according to first choice parameter call constant amplitude from control machine code 202 when, constant amplitude is from control
Machine code is N=N+x；Wherein x is the integer more than 1.When computing module 102 calls non-constant amplitude from increasing according to the second selection parameter
When controlling machine code 203, non-constant amplitude is N=N+x from control machine coden, wherein { xnIt is integer ordered series of numbers, xnIt is whole more than 1
Number.
In the present embodiment, computing module 102 carries out knowing together the detailed process calculating as shown in figure 3, including：
Step 301：Input initial value Start and desired value Target.For example, the initial value of input is 5, the mesh of input
Scale value is 1005.
Step 302：Hash complicated dynamic behaviour.Specifically, a Hash operation is carried out according to initial value and desired value.
Step 303：Judge whether operation result is less than desired value Target.If so, then execution step 305, otherwise, execution
Step 304.
Step 304：N is from increasing.Specifically, when above-mentioned operation result is not less than desired value, N is from increasing, for example, default N
For 5, selection parameter is first choice parameter, and computing module calls constant amplitude from control machine code, and x is equal to 5, then initial value is permissible
Increase by 5 on the basis of original input value 5, be changed into 10, afterwards return to step 302, continue Hash complicated dynamic behaviour, until obtaining
Till meeting the result of condition.
Step 305：Return the value of N.
Amplification mode due to N can be selected according to selection parameter, and, the amplification of N is more than 1, so, Yong Huke
To control the amplification mode of the stride of common recognition calculating by selection parameter, and then, select the higher stride controlling party of computational efficiency
Formula, improves operation efficiency.
Additionally, common recognition can control calculation procedure during calculating, any one step in above-mentioned steps can basis
User needs to interrupt at any time and exit.
Compared with prior art, it is used alone fpga chip execution common recognition to calculate, not only can improve calculating performance, also may be used
With reducing energy consumption, improve common recognition the calculatings performance calculating and the ratio consuming energy, and, above-mentioned common recognition computing chip small volume,
It is easily integrated；The stride that computing module carries out common recognition calculating can be according to the difference of default objectives value Target and user
Demand and regulate and control, so, can also improve common recognition calculate speed.
Third embodiment of the present invention is related to a kind of mainboard, as shown in figure 4, this mainboard 401 can include：Interface chip
With common recognition computing chip 100.Wherein interface chip is connected with common recognition computing chip 100, and interface chip can receive common recognition and calculate
In chip 100, the calculating parameter of common recognition computational algorithm is it is possible to be transferred to, by this calculating parameter, the meter in computing chip 100 of knowing together
Calculate module, and then, computing module can carry out common recognition according to the calculating parameter of common recognition computational algorithm with common recognition computational algorithm and calculate.
Interface chip includes first interface chip 402, and wherein, first interface chip 402 can be PCI Express interface
Chip.Specifically, PCI Express is EBI, sends data and receiving data can synchronously be carried out, using 8b/10b
The embedded clock technology of coding, clock information is written directly in data flow, can be effectively saved transmission channel, improves transmission effect
Rate, using point to point operation pattern (Peer to Peer, also referred to as P2P), each equipment has the dedicated transmission of oneself
Road, can avoid multiple equipment to fight for the problem of bandwidth；Data transmission rate can be brought up to a very high frequency.
Interface chip can also include second interface chip 403, and wherein, second interface chip 403 can connect for USB2.0
Mouth chip, transmission speed faster, is supported hot plug and is connected multiple equipment, and can be with backward compatible USB1.1.
Compared with prior art, interface chip can receive the calculating parameter of common recognition computational algorithm, and is transferred to know together
Computing module in computing chip is used for carrying out common recognition calculating.So, it is used alone fpga chip execution common recognition to calculate, not only may be used
Calculate performance to improve, the calculating performance of common recognition calculating and the ratio of power consumption with reducing energy consumption, can be improved, and, above-mentioned
Mainboard small volume is it is easy to integrated.
Four embodiment of the invention is related to a kind of common recognition computing device, as shown in figure 5, including mainboard 401, this mainboard can
To include interface chip and common recognition computing chip 100.Wherein, interface chip is connected with common recognition computing chip 100, interface chip
The parameter of common recognition computational algorithm can be received, and parameter can be transferred to the computing module in computing chip of knowing together, and then,
Computing module can carry out common recognition according to calculating parameter with common recognition computational algorithm and calculate.
Interface chip includes first interface chip 402, and wherein, first interface chip 402 can be PCI Express interface
Chip.Interface chip can also include second interface chip 403, and wherein, second interface chip 403 can be USB2.0 interface core
Piece.
Compared with prior art, not only can improve calculating performance, the calculating that common recognition calculates can be improved with reducing energy consumption
Performance and the ratio consuming energy；And, it is easy to integrated, specifically, this common recognition computing device can realize miniaturization to small volume, enters
And, can be integrated with hardware devices such as existing television set, mobile phone, automobiles.
Fifth embodiment of the invention is related to a kind of common recognition computing system, as shown in fig. 6, terminal 600 can be included together
Know computing device 501.Wherein, common recognition computing device 501 is connected with terminal 600.
Terminal 600 can include first interface 601, second interface 602, drive module 603, acquisition module 604 and send
Module 605.Wherein, first interface chip is docked with the first interface 601 of terminal, the second interface of second interface chip and terminal
602 docking, drive module 603 is used for driving common recognition computing device, and acquisition module 604 is used for obtaining calculating parameter, sending module
605 calculating parameters being used for obtaining acquisition module are sent to computing module by interface chip.Terminal 600 can also include showing
Show the input equipments such as device and keyboard.Above-mentioned terminal can be computer, mobile phone, television set, PDA (Personal Digital
Assistant, personal digital assistant) etc..
Specifically, in embodiment of the present invention, common recognition computing device 501 can by by the interface chip on equipment with
The interface of terminal docks and links together.Calculating parameter, such as initial value and desired value required for common recognition calculating, can pass through
By user input to terminal 600, afterwards, the acquisition module 604 in terminal 600 can obtain the meter of input to the input equipments such as keyboard
Calculate parameter, and calculating parameter is transferred to sending module 605, and then, calculating parameter can be counted by sending module 605 by common recognition
Interface chip on calculation equipment sends to computing module, and computing module can calculate according to the calculating parameter receiving and common recognition
Algorithm carries out common recognition and calculates, and the end value of calculating of knowing together the most at last is transferred to terminal 600, so, Yong Huke by interface chip
The end value that detection common recognition calculates is obtained by display.
Compared with prior art, common recognition computing device is connected with terminal by interface chip, so, computing device of knowing together
Calculating parameter is obtained by terminal and carries out common recognition calculating.Calculated using common recognition computing device common recognition, not only can improve
Calculate performance, the calculating performance of common recognition calculating and the ratio of power consumption with reducing energy consumption, can be improved.
It is noted that involved each module in present embodiment is logic module, in actual applications, one
Individual logical block can be a part for a physical location or a physical location, can also be with multiple physics lists
The combination of unit is realized.Additionally, for the innovative part projecting the present invention, will not be with solution institute of the present invention in present embodiment
The unit that the technical problem relation of proposition is less close introduces, but this is not intended that in present embodiment there are not other lists
Unit.
System embodiment described above is only that schematically the wherein said unit illustrating as separating component can
To be or to may not be physically separate, as the part that unit shows can be or may not be physics list
Unit, you can with positioned at a place, or can also be distributed on multiple NEs.Can be selected it according to the actual needs
In the purpose to realize this embodiment scheme for some or all of module.Those of ordinary skill in the art are not paying creativeness
Work in the case of, you can to understand and to implement.
Finally it should be noted that：Above example only in order to technical scheme to be described, is not intended to limit；Although
With reference to the foregoing embodiments the present invention is described in detail, it will be understood by those within the art that：It still may be used
To modify to the technical scheme described in foregoing embodiments, or equivalent is carried out to wherein some technical characteristics；
And these modification or replace, do not make appropriate technical solution essence depart from various embodiments of the present invention technical scheme spirit and
Scope.
Claims (9)
1. one kind knows together computing chip it is characterised in that described common recognition computing chip is on-site programmable gate array FPGA chip,
Described common recognition computing chip includes：Memory module and computing module；
Described memory module is connected with described computing module；
The machine code of common recognition computational algorithm passes through sintering curing in described memory module, and described computing module is used for according to described
The machine code of the common recognition computational algorithm in memory module carries out common recognition and calculates.
2. common recognition computing chip according to claim 1 is it is characterised in that the Hash Hash complexity meter of described machine code
Formula is
SHA256M(Start N)<Target；
Wherein, SHA256 is SHA, and operation result is 256, and Start is initial value, and N is integer, described Start
With the splicing of described N phase；Described Target is desired value；M is Hash operation number of times, from the beginning of second Hash operation, each time
The input of Hash operation is the output of last Hash operation.
3. common recognition computing chip according to claim 2 is it is characterised in that also sinter stride control in described memory module
Machine code；
Described stride controls machine code to be used for controlling the amplification of described N.
4. common recognition computing chip according to claim 3 is it is characterised in that described stride controls machine code the amplitude such as to include
From control machine code with non-constant amplitude from control machine code；
When amplitude is from control machine code according to first choice parameter call etc. for described computing module, described computing module
The stride calculating that carries out knowing together is integer more than 1；
When described computing module calls non-constant amplitude from control method according to the second selection parameter, described computing module is carried out altogether
Know the stride calculating and carry out common recognition calculating according to the stride ordered series of numbers of default non-constant amplitude；
Wherein, described first choice parameter, described second selection parameter respectively with etc. amplitude from control machine code, non-constant amplitude from
Control machine code corresponds.
5. a kind of mainboard is it is characterised in that include：Interface chip calculates core with the common recognition any one of Claims 1-4
Piece；
Described interface chip is connected with described common recognition computing chip；Described interface chip is used for receiving described common recognition computational algorithm
Calculating parameter, and it is transferred to the computing module in described common recognition computing chip；
Described computing module carries out common recognition according to described calculating parameter with described common recognition computational algorithm and calculates.
6. mainboard according to claim 5 is it is characterised in that described interface chip includes first interface chip；
Described first interface chip is PCI Express interface chip.
7. mainboard according to claim 6 is it is characterised in that described interface chip also includes second interface chip；
Described second interface chip is USB2.0 interface chip.
8. a kind of common recognition computing device is it is characterised in that include：Mainboard described in any one of claim 5 to 7.
9. a kind of common recognition computing system is it is characterised in that include：Terminal and the common recognition computing device described in claim 8；
Described common recognition computing device is connected with described terminal；
Described terminal includes：Interface, drive module, acquisition module and sending module；
Described interface chip is docked with described interface；
Described drive module is used for driving described common recognition computing device；
Described acquisition module, for obtaining calculating parameter；
Described sending module, is sent by described interface chip to based on described by the calculating parameter obtaining described acquisition module
Calculate module.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107046542A (en) * | 2017-04-24 | 2017-08-15 | 杭州云象网络技术有限公司 | A kind of method that common recognition checking is realized using hardware in network level |
| CN107103472A (en) * | 2017-04-26 | 2017-08-29 | 北京计算机技术及应用研究所 | A kind of algorithm processing module for block chain |
| CN108322304A (en) * | 2018-02-28 | 2018-07-24 | 北京比特大陆科技有限公司 | The computational methods and device of proof of work, electronic equipment, program and medium |
| CN111367848A (en) * | 2018-12-25 | 2020-07-03 | 北京天能博信息科技有限公司 | Data processing device, related equipment and method for block chain |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7613902B1 (en) * | 2005-09-22 | 2009-11-03 | Lockheed Martin Corporation | Device and method for enabling efficient and flexible reconfigurable computing |
| CN103973432A (en) * | 2014-05-23 | 2014-08-06 | 浪潮电子信息产业股份有限公司 | SM4 algorithm encryption unit based on FPGA chip and USB interface chip |
-
2016
- 2016-09-08 CN CN201610810949.7A patent/CN106484367A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7613902B1 (en) * | 2005-09-22 | 2009-11-03 | Lockheed Martin Corporation | Device and method for enabling efficient and flexible reconfigurable computing |
| CN103973432A (en) * | 2014-05-23 | 2014-08-06 | 浪潮电子信息产业股份有限公司 | SM4 algorithm encryption unit based on FPGA chip and USB interface chip |
Non-Patent Citations (1)
| Title |
|---|
| 须磊: "HMAC-SHA256算法的优化设计", 《价值工程》 * |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107046542A (en) * | 2017-04-24 | 2017-08-15 | 杭州云象网络技术有限公司 | A kind of method that common recognition checking is realized using hardware in network level |
| CN107046542B (en) * | 2017-04-24 | 2020-04-14 | 杭州云象网络技术有限公司 | Method for realizing consensus verification by adopting hardware at network level |
| CN107103472A (en) * | 2017-04-26 | 2017-08-29 | 北京计算机技术及应用研究所 | A kind of algorithm processing module for block chain |
| CN108322304A (en) * | 2018-02-28 | 2018-07-24 | 北京比特大陆科技有限公司 | The computational methods and device of proof of work, electronic equipment, program and medium |
| CN108322304B (en) * | 2018-02-28 | 2021-12-07 | 海峡小鹿有限公司 | Calculation method and apparatus for workload certification, electronic device, program, and medium |
| CN111367848A (en) * | 2018-12-25 | 2020-07-03 | 北京天能博信息科技有限公司 | Data processing device, related equipment and method for block chain |
| CN111367848B (en) * | 2018-12-25 | 2021-08-20 | 北京天能博信息科技有限公司 | Data processing device, related equipment and method for block chain |
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