CN106847852B - Back structure of electron multiplication charge coupled device and manufacturing method thereof - Google Patents
Back structure of electron multiplication charge coupled device and manufacturing method thereof Download PDFInfo
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Abstract
The invention relates to a back structure of electron multiplication charge coupled device and its preparation method, the back structure includes EMCCD chip, electrode lead-out area, photosensitive area, storage gain area, ion implantation area, antireflection film and metal shielding layer, the electrode lead-out area is set up in the back both sides of EMCCD chip, the electrode lead-out area is equipped with the pressure welding figure at intervals, photosensitive area and storage gain area of the back of EMCCD chip position are between electrode lead-out areas, there are ion implantation areas formed by low-energy ion implantation in photosensitive area and storage gain area, antireflection film on the surface of photosensitive area, can reduce standing wave effect, reduce the reflected light; the metal shielding layer on the surface of the storage gain region can prevent incident light from transmitting through the surface of the storage gain region. The invention can be used for improving the photoelectric conversion efficiency of the electron multiplication charge coupled device, and simultaneously can also reduce the manufacturing cost of the device and improve the yield of products.
Description
Technical Field
The invention relates to a back structure of an electron multiplication charge coupled device and a manufacturing method thereof, belonging to the technical field of charge coupled devices.
Background
Electron Multiplying Charge Coupled Devices (EMCCDs) have been developed for many years and have been widely used in many fields such as image scanning, industrial non-contact measurement, aerospace, astronomical remote sensing, military, medicine, etc. The electron multiplication charge-coupled device is a large-scale integrated photoelectric device, has the functions of photoelectric conversion, charge storage, charge transfer, charge measurement and the like, has the technical characteristics of high sensitivity, high signal-to-noise ratio, high modulation transfer function, full solid state and the like, and plays an irreplaceable key role in the aspects of technical upgrading and reconstruction of the traditional day digital image industry, such as an X-ray digital imaging system, various high-frame-rate cameras and the like, in the aspects of development of low-light night vision, such as low-light television, industrial monitoring, deep space detection and the like, and in the aspects of emerging industries, such as smart cities, internet+ and the like, and is used as a core device of a light-weight and reliable low-light imaging system.
In recent years, due to rapid expansion of industrial automation and market scale of digital images, market demands of micro-light detectors are also rapidly increased, and due to continuous upgrading of manufacturing processes of electronic devices, design and manufacturing of back structures of electron multiplication charge coupled devices are gradually mature, so that back irradiation electron multiplication charge coupled devices are increasingly widely applied to production, living and working, digital image acquisition and processing systems using back irradiation electron multiplication charge coupled devices as core devices are widely used in fields of consumer electronics, medical treatment, industrial monitoring, aerospace, military and the like, such as monitoring cameras, video conferences, cameras and the like in subway traffic. However, the research on the back structure of the domestic electron multiplying charge coupled device is still in the research and development stage, and the proper balance between the cost and the process is not achieved. The existing mainstream back structure manufacturing method needs multiple steps to adjust process parameters during polishing, so that not only is the process efficiency low, but also chip breakage is easy to cause, and a special fixing clamp is required to be customized, so that the cost is high, the existing back structure manufacturing technology generally has the problems of single photoetching pattern, rough pattern control precision, less applicable device schemes and the like, and is not suitable for manufacturing the back structure of the electron multiplying charge coupled device.
Disclosure of Invention
The invention provides a back structure of an electron multiplication charge coupled device and a manufacturing method thereof, which overcome the defects in the prior art, well realize ultrathin and uniform back thickness reduction of the electron multiplication charge coupled device by using a technology combining a proper polishing process and a plurality of selective etching methods, have high reduction speed and fewer defects, realize the construction of the back structure morphology of the electron multiplication charge coupled device by adopting a multi-step standard semiconductor photoetching process, reduce the production cost of the device, ensure the good performance of the device and have better economic benefit.
The technical scheme of the back structure of the electron multiplication charge coupled device and the manufacturing method thereof is that the back structure of the electron multiplication charge coupled device is realized through the process steps of back grinding and polishing corrosion, low-energy P-type ion implantation, laser annealing, multi-layer film sputtering etching, photoetching corrosion of an electrode lead-out area and the like, after the front structure is finished, the back of the electron multiplication charge coupled device is thinned through grinding and polishing combined with various corrosion processes, then the flattened back surface is subjected to low-energy P-type ion implantation, after the implantation is finished, the laser annealing is adopted to carry out rapid annealing to form an ion implantation area, an anti-reflection film and a metal shielding layer are deposited, the surface morphology of a photosensitive area and a storage gain area is finished through pattern photoetching, and finally the electrode lead-out area is manufactured through photoetching corrosion of various materials, so that the complete back structure of the electron multiplication charge coupled device is manufactured.
A backside structure of an electron-multiplying charge-coupled device, characterized by: the back of the EMCCD chip (1) is provided with an electrode lead-out area (2), a photosensitive area (3), a storage gain area (4), an ion implantation area (5), an antireflection film (6) and a metal shielding layer (7), wherein the electrode lead-out area (2), the photosensitive area (3) and the storage gain area (4) are adjacently formed inside a back silicon body of the EMCCD chip (1), the ion implantation area (5) is formed inside the photosensitive area (3) and the storage gain area (4) through low-energy ion implantation, the antireflection film (6) is coated on the surface of the photosensitive area (3), and the antireflection film (6) and the metal shielding layer (7) are arranged on the surface of the storage gain area (4).
The electron multiplication charge coupled device chip comprises a back electrode lead-out area, a photosensitive area, an antireflection film on the photosensitive area, a storage gain area, an antireflection film on the storage gain area and a metal shielding layer, wherein the antireflection film and the metal shielding layer are sequentially adjacent to form a three-stage step appearance.
And the storage gain area on the back of the electron multiplication charge coupled device chip, the antireflection film on the storage gain area, the metal shielding layer and the electrode lead-out area are sequentially adjacent to form a secondary step morphology.
The included angle alpha between the side wall between the second-stage step formed by the photosensitive area (3) and the antireflection film (6) and the first-stage step formed by the electrode lead-out area (2) and the surface of the first-stage step is 90-150 degrees, and the included angle beta between the side wall between the third-stage step formed by the metal shielding layer (7) on the storage gain area (4) and the second-stage step formed by the photosensitive area (3) and the antireflection film (6) and the surface of the second-stage step is 90-150 degrees.
The included angle gamma between the side wall between the second-stage step formed by the storage gain region (4) and the anti-reflection film (6) above and the metal shielding layer (7) and the first-stage step formed by the electrode lead-out region (2) and the surface of the second-stage step is 90-150 degrees.
The thickness h0 of the electrode lead-out area (2) is 0.5-10 mu m.
The height h1 of the side wall between the first-stage step formed by the electrode lead-out area (2) and the second-stage step formed by the photosensitive area (3) and the antireflection film (6) is 10-30 mu m.
The height h2 of the side wall between the second-stage step formed by the photosensitive region (3) and the antireflection film (6) and the third-stage step formed by the metal shielding layer (7) above the storage gain region (4) is 0.5-5 mu m.
The depth d0 of the ion implantation region in the back surface structure is 0.1-2 μm.
The thickness d1 of the antireflection film in the back surface structure is 0.01-1 μm
The thickness d2 of the metal shielding layer in the back structure is 0.5-5 mu m.
The manufacturing method of the back structure of the EMCCD chip is carried out after the front process of the EMCCD chip is finished, and comprises the following steps:
1) The back of the EMCCD chip (1) is thinned to 10-50 mu m by combining mechanical grinding, wet etching and chemical mechanical polishing processes;
2) The back of the thinned EMCCD chip (1) is subjected to low-energy ion implantation, P-type ions are implanted, and an ion implantation area (5) is formed in the silicon body at the back of the EMCCD chip;
3) Carrying out laser annealing treatment on the ion implantation region (5), and repairing lattice damage through rapid annealing;
4) An antireflection film (6) is deposited and evaporated on the back of the EMCCD chip (1);
5) A metal shielding layer (7) is deposited on the anti-reflection film (6) by sputtering;
6) Photoetching a metal shielding layer (7) to realize mask pattern transfer, wherein the etching stop layer is an antireflection film (6) layer, and the metal shielding layer (7) on the surface of the storage gain area (4) is formed;
7) Etching the antireflection film (6) by adopting photoetching, establishing a pattern on the surface of the photosensitive region (3), and forming an antireflection film (6) layer on the surface of the photosensitive region (3) by etching the cutoff layer to form an ion implantation region (5);
8) And manufacturing an electrode lead-out area (2) on the back of the EMCCD chip (1) by adopting inductively coupled plasma etching and combining wet etching and/or dry etching.
According to the invention, the step morphology structure is formed on the back of the EMCCD chip by adopting multi-step processes such as polishing thinning, wet etching, dry etching, chemical mechanical polishing and the like, the side wall of the step is not vertical, and a certain included angle is formed between the side wall and the horizontal plane. The invention forms a built-in electric field in the photosensitive area and the storage gain area through the ion implantation area, and the potential difference of the built-in electric field drives photo-generated electrons generated by the incident silicon body on the back surface of the incident light, so that the photo-generated electrons are effectively transferred to the integral potential well of the EMCCD device, thereby being beneficial to improving the photo-response time of the EMCCD device and ensuring better compromise between the photo-response time of the device and the photo-generated carrier absorptivity of the device.
The invention provides a back structure of an EMCCD chip and a manufacturing method thereof, after the front structure of the EMCCD chip is manufactured, the EMCCD chip is thinned to a target thickness by selecting proper polishing materials, polishing pads and polishing speed in the polishing process, the target thickness is set to be 20 mu m, the mechanical polishing is thinned to the target thickness, the fragmentation probability of the EMCCD chip can be reduced, then a slow low-heating corrosive liquid is used, and the corrosion speed and the corrosion precision can be controlled by a wet method matched with a high-precision temperature control instrument in the prior art, so that the corrosion method not only has selectivity, but also can increase the back corrosion precision of the EMCCD chip, and the corrosion method can also reduce the pollution of the back surface of the corrosive liquid EMCCD chip as much as possible. Then, the back of the EMCCD chip is etched by continuously using an inductively coupled plasma ICP dry etching technology, and the ICP etching has the characteristics of good controllability, high uniformity and the like, so that the better controllable etching profile and clean etching of the EMCCD chip can be realized, then Chemical Mechanical Polishing (CMP) is applied, and the excellent flatness of the back of the EMCCD chip is obtained by selecting the conditions of the particle size of the polishing liquid, the flow rate of the polishing liquid, the pH value of the polishing liquid, the polishing pad material, the polishing pad pressure and the like, so that the smooth surface of the back of the EMCCD chip with high flatness is obtained, and the damage of the surface of the back of the EMCCD chip is reduced. According to the invention, ion implantation is adopted on the back of the EMCCD chip, so that the recombination effect of the capture state defects on the surface on the photo-generated carriers can be effectively reduced, and the signal collection efficiency of the EMCCD chip can be improved by generating built-in potential difference in silicon on the back of the EMCCD chip due to the ion implantation effect. According to the invention, the antireflection film is evaporated on the photosensitive area on the back of the EMCCD chip, so that the light energy loss caused by reflection on the back surface of the EMCCD chip is reduced, and the photoelectric efficiency of the device is improved. The invention realizes the back structure of the EMCCD chip and the manufacture thereof by adopting a multi-step semiconductor manufacturing process method such as grinding, polishing and thinning, semiconductor etching, chemical mechanical polishing, ion implantation, photoetching process and the like. The invention has the characteristics of controllable process, simple process steps, capability of effectively improving the problem of low process efficiency of realizing the back morphology of the EMCCD chip, capability of greatly improving the photoelectric conversion performance of the EMCCD chip, high back processing precision and support of the optimization of various back patterns of devices, capability of greatly reducing the manufacturing cost of the back structure of the EMCCD chip, realization of optimal balance between the manufacturing cost and the product performance, and important practical significance for promoting the autonomous development of the micro-light detector in China.
Drawings
Fig. 1 is a schematic structural view of the present invention.
Fig. 2 is a schematic illustration of ion implantation region formation.
Fig. 3 is a view showing the formation of an antireflection film and a metal shielding layer.
Fig. 4 is a schematic diagram of the formation of the photosensitive region and the storage gain region.
Fig. 5 is a schematic view of forming an electrode lead-out area.
Detailed Description
Embodiments of the present invention are described in further detail below with reference to the accompanying drawings.
As shown in the schematic structure of the invention in fig. 1: the back structure of the EMCCD chip comprises an EMCCD chip 1, an electrode lead-out area 2 of the EMCCD chip 1, a photosensitive area 3, a storage gain area 4, an ion implantation area 5, an antireflection film 6 and a metal shielding layer 7. The electrode lead-out area 2, the photosensitive area 3 and the storage gain area 4 are adjacently formed in the back silicon body of the EMCCD chip 1, an ion implantation area 5 is formed in the photosensitive area 3 and the storage gain area 4 through low-energy ion implantation, an antireflection film 6 is coated on the surface of the photosensitive area 3, and the antireflection film 6 and a metal shielding layer 7 are arranged on the surface of the storage gain area 4.
The electrode lead-out areas 2 are arranged on two sides of the back surface of the EMCCD chip 1, pressure welding patterns are arranged on the electrode lead-out areas 2 at intervals and can be used for bonding and interconnection with a packaging structure of the EMCCD chip 1, the photosensitive areas 3 and the storage gain areas 4 on the back surface of the EMCCD chip 1 are arranged between the electrode lead-out areas 2, ion implantation areas 5 formed by low-energy ion implantation are arranged in the photosensitive areas 3 and the storage gain areas 4, an antireflection film 6 formed by semiconductor processing methods such as cleaning, baking and sputtering evaporation is arranged on the surface of the photosensitive areas 3, the antireflection film 6 on the surface of the photosensitive areas 3 can reduce standing wave effect and reduce light reflected by the surface of the photosensitive areas 3, the surface of the storage gain areas 4 is provided with a metal shielding layer 7 manufactured by semiconductor processing methods such as cleaning, drying and sputtering, and the metal shielding layer 7 on the surface of the storage gain areas 4 can effectively prevent the incident light from being transmitted on the surface of the storage gain areas 4.
In the structural schematic diagram of the invention shown in fig. 1, an electrode lead-out area 2, a photosensitive area 3, an antireflection film 6, a storage gain area 4 and a metal shielding layer 7 on the back surface of an EMCCD chip 1 form a three-stage step morphology, wherein the electrode lead-out area 2 forms a first-stage step on the back surface of the EMCCD chip 1, the photosensitive area 3 and the antireflection film 6 form a second-stage step on the back surface of the EMCCD chip 1, and the metal shielding layer 7 forms a third-stage step on the back surface of the EMCCD chip 1.
In the structural schematic diagram of the invention shown in fig. 1, an electrode lead-out area 2, a storage gain area 4, an antireflection film 6 and a metal shielding layer 7 on the back surface of an EMCCD chip 1 form a two-stage step morphology, wherein the electrode lead-out area 2 forms a first stage step on the back surface of the EMCCD chip 1, and the storage gain area 4, the antireflection film 6 and the metal shielding layer 7 form a second stage step on the back surface of the EMCCD chip 1.
In the structural schematic diagram of the invention shown in fig. 1, the included angle between the side wall between the first-stage step and the second-stage step in the three-stage step morphology and the surface of the first-stage step is alpha, and the included angle between the side wall between the first-stage step and the second-stage step and the surface of the second-stage step is beta. The included angle alpha is 90-150 degrees, and the included angle beta is 90-150 degrees.
In the structural schematic diagram of the invention shown in fig. 1, the included angle between the side wall between the first-stage step and the second-stage step in the second-stage step morphology and the surface of the second-stage step is gamma. The included angle gamma is 90-150 degrees.
The thickness of the electrode lead-out area 2 in the structural schematic diagram of the present invention in fig. 1 is h0. The thickness h0 is 0.5-10 mu m.
In the structural schematic diagram of the invention shown in fig. 1, the height of a side wall between a first step and a second step of the three-step morphology is h1. The height h1 of the side wall is 10-30 mu m.
In the structural schematic diagram of the invention shown in fig. 1, the height of the side wall between the second-stage step and the third-stage step in the three-stage step morphology is h2. The height h2 of the side wall is 0.5-5 mu m.
The depth of the ion implantation region 5 in the schematic structure of the present invention in fig. 1 is d0. The depth d0 is 0.1-2 μm.
The thickness of the antireflection film 6 in the structural diagram of the present invention in fig. 1 is d1. The thickness d1 is 0.01-1 μm.
The thickness of the metal shielding layer 7 in the structural schematic of the present invention in fig. 1 is d2. The thickness d2 is 0.5-5 μm.
Fig. 2 is a diagram illustrating formation of an ion implantation region, in which low-energy P-type ion implantation is performed on the back surface of the thinned EMCCD chip 1, and an ion implantation region 5 is formed in a silicon body on the back surface of the EMCCD chip 1, wherein the ion implantation region 5 can reduce lattice damage and defects on the back surface, and the ion implantation region 5 can also form a built-in electric field to drive photo-generated electrons to be effectively transferred.
Fig. 3 is a diagram showing the formation of an antireflection film and a metal shielding layer, in which the antireflection film 6 and the metal shielding layer 7 are formed on the back surface of the thinned EMCCD chip 7 by a semiconductor processing method such as sputtering or vapor deposition, the antireflection film 6 can reduce the reflection phenomenon of incident light on the back surface of the EMCCD chip 7, and the metal shielding layer 7 can effectively prevent the incident light from being transmitted into the ion implantation region 5.
Fig. 4 is a schematic diagram of formation of a photosensitive region and a storage gain region, wherein an anti-reflection film 6 and a metal shielding layer 7 deposited on the back surface of an EMCCD chip 1 are subjected to a semiconductor photolithography process, a mask pattern is firstly transferred to a photoresist layer on the anti-reflection film 6 and the metal shielding layer 7 for exposure and development, then the photoresist layer is transferred to the anti-reflection film 6 and the metal shielding layer 7 from the photoresist layer through etching, and the photosensitive region 3 and the storage gain region 4 are formed in an ion implantation region 5 through a characteristic pattern.
Fig. 5 is a schematic diagram of forming an electrode lead-out area, and the back of the EMCCD chip 1 is etched by inductively coupled plasma etching in combination with other dry etching and wet etching processes, so that a multi-layer material on the back of the EMCCD chip 1 is manufactured into an electrode lead-out area 2 on the back of the EMCCD chip according to a characteristic pattern.
The manufacturing method of the back structure of the EMCCD chip is carried out according to the following specific and detailed steps after the front process of the EMCCD chip is finished:
1) The back of the EMCCD chip 1 is thinned to 10-50 mu m by combining the processes of mechanical grinding, wet etching, chemical mechanical polishing and the like;
2) The back of the thinned EMCCD chip 1 is subjected to low-energy ion implantation, P-type ions are implanted, the implantation dosage is 1E 14-5E 15, the implantation energy is 0.1 KeV-10 KeV, and an ion implantation region 5 with the depth d0 of 0.1-2 mu m is formed;
3) Carrying out laser annealing treatment on an ion implantation area 5 on the back surface of the EMCCD chip 1, wherein the laser annealing treatment adopts a laser beam with the working wavelength of 100-500 nm, the energy density of 0.1-20J/cm < 2 >, and the pulse width of 50-500 ns;
4) Evaporating an antireflection film 6 on the surface of an ion implantation region 5 at the back of the thinned EMCCD chip 1 by deposition, wherein the thickness of the antireflection film 6 is 0.01-1 mu m;
5) Photoetching a metal shielding layer 7 at the back of the EMCCD chip 1, transferring a mask pattern to the back of the EMCCD chip 1, and forming a metal shielding layer 7 on the surface of the storage gain region 4 by using an anti-reflection film layer 6 as an etching stop layer, wherein the thickness of the metal shielding layer 7 is 0.5-5 mu m;
6) Etching the anti-reflection film 6 evaporated on the back of the EMCCD chip 1 by adopting photoetching, establishing a pattern on the surface of the photosensitive region 3, and forming an anti-reflection film 6 layer on the surface of the photosensitive region 3 by using an ion implantation region 5 on the back of the EMCCD chip as an etching stop layer, wherein the thickness of the anti-reflection film 6 layer is 0.01-1 mu m;
7) An electrode lead-out area 2 is manufactured on the back of the EMCCD chip 1 by inductively coupled plasma etching in combination with wet etching and dry etching.
The invention has good control capability on the back thickness of the EMCCD chip (1) through the processing methods of mechanical polishing, semiconductor etching, chemical mechanical polishing and the like, has high back processing precision, has no special limit on the photoetching patterns on the back, can realize various back pattern schemes, is simple and reliable, reduces the production cost and shortens the research and development period of products.
While the invention has been described in terms of what are presently considered to be the most practical and preferred embodiments, it is to be understood that the invention is not limited to the particular examples disclosed, but on the contrary, is intended to cover various modifications and alternative arrangements included within the spirit and scope of the appended claims. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that while the present invention has been described in terms of embodiments, not every embodiment is provided with a separate embodiment, and this description is for clarity only, and those skilled in the art will recognize that the foregoing description is provided as a whole, and that the embodiments may be suitably combined to form other embodiments as will be understood by those skilled in the art.
Claims (10)
1. A backside structure of an electron-multiplying charge-coupled device, characterized by: the back of the EMCCD chip (1) is provided with an electrode lead-out area (2), a photosensitive area (3), a storage gain area (4), an ion implantation area (5), an antireflection film (6) and a metal shielding layer (7), wherein the electrode lead-out area (2), the photosensitive area (3) and the storage gain area (4) are adjacently formed inside a back silicon body of the EMCCD chip (1), the ion implantation area (5) is formed inside the photosensitive area (3) and the storage gain area (4) through low-energy ion implantation, the antireflection film (6) is coated on the surface of the photosensitive area (3), and the antireflection film (6) and the metal shielding layer (7) are arranged on the surface of the storage gain area (4).
2. The back surface structure of the electron multiplying charge coupled device according to claim 1, wherein the electrode lead-out area (2), the photosensitive area (3), the antireflection film (6) and the metal shielding layer (7) on the back surface of the EMCCD chip (1) are sequentially adjacent to form a three-stage step morphology, wherein the electrode lead-out area (2) forms a first-stage step on the back surface of the EMCCD chip (1), the photosensitive area (3) and the antireflection film (6) form a second-stage step on the back surface of the EMCCD chip (1), and the metal shielding layer (7) forms a third-stage step on the back surface of the EMCCD chip (1).
3. The back surface structure of the electron multiplying charge coupled device according to claim 1, wherein the electrode lead-out area (2), the storage gain area (4), the antireflection film (6) and the metal shielding layer (7) on the back surface of the EMCCD chip (1) are sequentially adjacent to form a two-stage step morphology, wherein the electrode lead-out area (2) forms a first-stage step on the back surface of the EMCCD chip (1), and the storage gain area (4), the antireflection film (6) and the metal shielding layer (7) form a second-stage step on the back surface of the EMCCD chip (1).
4. The back surface structure of an electron multiplying charge coupled device according to claim 1 or 2, wherein an included angle α between a sidewall between a second step formed by the photosensitive region (3) and the antireflection film (6) and a first step formed by the electrode lead-out region (2) and a surface of the first step is 90 ° to 150 °, and an included angle β between a sidewall between a third step formed by the metal shielding layer (7) on the storage gain region (4) and a second step formed by the photosensitive region (3) and the antireflection film (6) and a surface of the second step is 90 ° to 150 °.
5. The back structure of an electron multiplying charge coupled device according to claim 1 or 3, wherein a sidewall between a second step formed by the storage gain region (4) and the upper antireflection film (6) and the metal shielding layer (7) and a first step formed by the electrode lead-out region (2) forms an angle γ between 90 ° and 150 ° with the surface of the second step.
6. The back structure of an electron multiplying charge coupled device according to claim 1 or 2, wherein the thickness h0 of the electrode lead-out area (2) is 0.5-10 μm, the height h1 of the side wall between the first step formed by the electrode lead-out area (2) and the second step formed by the photosensitive area (3) and the antireflection film (6) is 10-30 μm, and the height h2 of the side wall between the second step formed by the photosensitive area (3) and the antireflection film (6) and the third step formed by the metal shielding layer (7) above the storage gain area (4) is 0.5-5 μm.
7. The back surface structure of an electron multiplying charge coupled device according to claim 1 or 2, wherein the depth d0 of the ion implantation region (5) is 0.1 to 2 μm.
8. The back structure of an electron multiplying charge coupled device according to claim 1 or 2, wherein the thickness d1 of the antireflection film (6) is 0.01 to 1 μm.
9. The back structure of an electron multiplying charge coupled device according to claim 1 or 2, wherein the thickness d2 of the metal shielding layer (7) is 0.5-5 μm.
10. A method for manufacturing a back structure of an electron multiplication charge coupled device is characterized by comprising the following steps: after finishing the front-side process of the EMCCD chip, manufacturing a back-side structure according to the following steps:
1) The back of the EMCCD chip (1) is thinned to 10-50 mu m by combining mechanical grinding, wet etching and chemical mechanical polishing processes;
2) The back of the thinned EMCCD chip (1) is subjected to low-energy ion implantation, P-type ions are implanted, and an ion implantation area (5) is formed in the silicon body at the back of the EMCCD chip;
3) Carrying out laser annealing treatment on the ion implantation region (5);
4) An antireflection film (6) is deposited and evaporated on the back of the EMCCD chip (1);
5) A metal shielding layer (7) is deposited on the anti-reflection film (6) by sputtering;
6) Photoetching a metal shielding layer (7) to realize mask pattern transfer, wherein the etching stop layer is an antireflection film (6) layer, and the metal shielding layer (7) on the surface of the storage gain area (4) is formed;
7) Etching the antireflection film (6) by adopting photoetching, establishing a pattern on the surface of the photosensitive region (3), and forming an antireflection film (6) layer on the surface of the photosensitive region (3) by etching the cutoff layer to form an ion implantation region (5);
8) And manufacturing an electrode lead-out area (2) on the back of the EMCCD chip (1) by adopting inductively coupled plasma etching and combining wet etching and/or dry etching.
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