CN106647700A - FPGA configuration control system test method, control platform and verification platform - Google Patents
FPGA configuration control system test method, control platform and verification platform Download PDFInfo
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- CN106647700A CN106647700A CN201611132486.XA CN201611132486A CN106647700A CN 106647700 A CN106647700 A CN 106647700A CN 201611132486 A CN201611132486 A CN 201611132486A CN 106647700 A CN106647700 A CN 106647700A
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- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
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- G05B23/02—Electric testing or monitoring
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Abstract
The invention provides an FPGA configuration control system test method, a control platform and a verification platform. Through acquiring a test case for testing a to-be-tested design of the configuration control system, test bit stream data generated according to a test execution process in the test case and a generation constraint condition are inputted to a test execution platform, the test bit stream data comprise specified test data generated according to the constraint condition and random test data generated by configuration data with no generation constraint condition for the test process, corresponding writing or reading time sequence signals are generated according to configuration interface information, the test bit stream data are written to the to-be-tested design of the configuration control system for test according to the time sequence signals, and as the generated test bit stream data have randomness, performance of the configuration control system in each condition can be verified, and the function verification accuracy and the reliability for the configuration control system are further enhanced.
Description
Technical field
The present invention relates to programmable integrated circuit design field, more particularly to a kind of FPGA (Field Programmable
Gate Array, field programmable gate array) configuration control system method of testing, control platform and verification platform.
Background technology
With the growth requirement of information and date science and technology, programmable chip, particularly field programmable gate array rely on it
The advantages of flexible in programming, system stability, aboundresources, high integrated level, its application extends from the original communications field
To extensive fields such as space flight, consumer electronics, Industry Control, test measurements, and there is the trend for constantly expanding.However as
Process node it is constantly soaring, people propose for the level of integrated system of programmable circuit, programmable resource and device scale
Higher requirement.For FPGA system, the configuration information bit stream for producing software is needed by FPGA configuration controls system
System is loaded in the configuration memory cell SRAM of related circuit module in circuit system to complete the configuration of corresponding function, therefore
FPGA configuration control system design rationality and practicality play the role of for Consumer's Experience it is very important, for
The test of FPGA configuration control systems is also a very important ring in design cycle.
At present for FPGA configures the test of control system, carried out on FPGA configuration control system test and verification platforms
, mainly the test bit stream data for needing is produced by the software kit instrument customization of FPGA, then configuration data stream reads
Device reads corresponding test bit stream data, is then input in driver by form conversion and is processed, while by default
Configuration interface message generate it is corresponding write or read clock signal be input into into driver, bit stream will be tested by driver
Data are tested according to the design to be measured that clock signal writes configuration control system.In this flow process, software kit instrument
Placement-and-routing's effect be fixed, interface is also fixed, therefore the test bit stream data that software kit instrument is produced is also
Fixed, not with randomness, the situation that FPGA configurations control system is showed under random case also cannot be just authenticated to, therefore
The accuracy of test checking is not high.
The content of the invention
A kind of FPGA configuration control system method of testings, control platform and verification platform that the present invention is provided, mainly solve
Technical problem be：When testing FPGA configurations control system in prior art, the test bit stream data of generation does not have
Randomness, it is impossible to verify that FPGA configurations control system shows the problem of situation under random case.
To solve above-mentioned technical problem, the present invention provides a kind of FPGA and configures control system testing and control platform, including：
Case-based system device, the test case that the design to be measured for obtaining to configuring control system is tested, the survey
Examination example includes the generation constraints of at least part of configuration data being related in testing process, testing process and configuration interface
Information；
Configuration data maker, for generating test position according to the test execution flow process and the generation constraints
Flow data is input into test execution platform；Comprising the nominative testing generated according to the constraints in the test bit stream data
Data and the random test data for being related to for the testing process but being generated without the configuration data for generating constraints；
Configuration interface sequence generator, for generating corresponding write according to the configuration interface message or reading sequential letter
Number it is input into the test execution platform, so that the bit stream data is write the configuration control system by the test execution platform
Design to be measured tested.
Further, the present invention also provides a kind of FPGA configurations control system test and verification platform, it is characterised in that include
Test execution platform and above-mentioned FPGA configuration control system testing and control platforms；
The test execution platform is used for the clock signal according to the configuration interface sequence generator output, matches somebody with somebody described
The design to be measured for putting the test bit stream data write configuration control system of Data Generator output is tested.
Further, the present invention also provides a kind of FPGA configurations control system method of testing, it is characterised in that include：
The test case that the design to be measured to configuring control system is tested is obtained, the test case includes test stream
The generation constraints and configuration interface message of at least part of configuration data being related in journey, testing process；
It is input into test and holds according to the test execution flow process and generation constraints generation test bit stream data
Row platform；Comprising the nominative testing data generated according to the constraints and for the survey in the test bit stream data
The random test data that examination flow process is related to but is generated without the configuration data for generating constraints；
Corresponding write is generated according to the configuration interface message or reading clock signal is input into the test execution and puts down
Platform, so that the test execution platform is tested the design to be measured of the bit stream data write configuration control system；
According to the clock signal, the test bit stream data write that the configuration data maker the is exported configuration control
The design to be measured of system processed is tested.
The invention has the beneficial effects as follows：
According to FPGA configuration control system method of testings, control platform and verification platform that the present invention is provided, by example
Getter obtains the test case that the design to be measured to configuring control system is tested, and configuration data maker is real according to test
Test execution flow process and generation constraints in example generates test bit stream data and is input into test execution platform, wherein, survey
It is related to comprising the nominative testing data generated according to constraints and for testing process but without generating about in examination bit stream data
The random test data that the configuration data of beam condition is generated, configure configuration of the interface sequence generator in test case and connect
Message breath generates corresponding write or reads clock signal and is input into test execution platform, so that the test execution platform will be tested
The design to be measured of bit stream data write configuration control system is tested, due to the test bit stream number that configuration data maker is generated
According to randomness, therefore performance situation of the configuration control system under each situation can be verified, and then improve configuration control
The accuracy and reliability of system functional verification processed.
Description of the drawings
Fig. 1 configures control system method of testing first pass schematic diagram for the FPGA of the embodiment of the present invention one；
Fig. 2 configures control system method of testing second procedure schematic diagram for the FPGA of the embodiment of the present invention one；
Fig. 3 configures the structural representation of control system testing and control platform for the FPGA of the embodiment of the present invention two；
Fig. 4 is the structural representation of the configuration data maker of the embodiment of the present invention two；
Fig. 5 configures the first structure schematic diagram of control system test and verification platform for the FPGA of the embodiment of the present invention three；
Fig. 6 configures the second structural representation of control system test and verification platform for the FPGA of the embodiment of the present invention three；
Fig. 7 configures the 3rd structural representation of control system test and verification platform for the FPGA of the embodiment of the present invention three.
Specific embodiment
Accompanying drawing is combined below by specific embodiment to be described in further detail the embodiment of the present invention.
Embodiment one：
In order that being no longer dependent on software kit instrument to the test that FPGA configures control system, improve and FPGA configurations are controlled
The accuracy that system processed is tested, the present embodiment provides a kind of FPGA and configures control system method of testing, specifically can join
As shown in Figure 1, including：
S101：Obtain the test case that the design to be measured to configuring control system is tested.
Test case in the present embodiment includes the life of at least part of configuration data being related in testing process, testing process
Into constraints and configuration interface message.And it should be noted that the design to be measured in the present embodiment can be to realize certain
The circuit design of function.Wherein, test case can be obtained by case-based system device in step S101.
S102：Test bit stream data is generated according to testing process and constraints to be input into test execution platform.
It should be appreciated that the configuration data maker that can pass through in the present embodiment is producing test bit stream data, this
Testing process and life in the test case that configuration data maker in embodiment can be got according to case-based system device
Into constraints, generate test bit stream data and be input into test execution platform.Wherein, the configuration data life in the present embodiment
The test bit stream data of generation of growing up to be a useful person includes the nominative testing data generated according to constraints, and is related to for testing process
But the random test data generated without the configuration data for generating constraints.
It should be noted that the configuration data maker in the present embodiment can include at least in following generator
Kind：Configuration register automatically generates device, configuration data storage and automatically generates in the identification of device, clear data generator and configuration data
Hold generator.
That is to say, the configuration data maker in the present embodiment can only include any one in above-mentioned generator, or
Person can include any two kinds, three kinds in above-mentioned generator, or can also simultaneously include four kinds of above-mentioned generators.Example
Such as, the configuration data maker in the present embodiment can automatically generate device and configuration data storage from movable property including configuration register
Raw device.
Therefore the configuration data maker in the present embodiment generates test bit stream data and just includes in situations below at least
It is a kind of：
Configuration register automatically generates device according to generation constraints generation specified configuration register data, and/or at random
Produce random arrangement register data；
Configuration data storage automatically generates device and the specified number for being configured to FPGA memory cell is produced according to generation constraints
According to, and/or randomly generate the random data for being configured to FPGA memory cell；
Clear data generator produces the clear data waited for clock handover configurations or for the time.
Configuration data identification Content Generator produces the mark data that bit stream data is tested described in unique mark.
It should be appreciated that the configuration register in the present embodiment automatically generates device can be specified according to constraints generation
Configuration register data and randomly generate random arrangement register data, it is also possible to only produce specified configuration register data or only
Produce random arrangement register data.Likewise, the configuration data storage in the present embodiment automatically generate device can be according to constraint
Condition produces and is configured to the director data of FPGA memory cell and randomly generates the random data for being configured to FPGA memory cell, or
Person can also only produce and specify data or only produce random data.Clear data generator in the present embodiment can be produced when supplying
Clock handover configurations or the clear data waited for the time, during such that it is able to providing enough waits for pattern switching data processing
Between, it should be appreciated that the size of the clear data in the present embodiment can be pre-set by developer, it is also possible to supports
User Defined.The mark data that configuration data identification Content Generator in the present embodiment is generated can be a fixed number
According to, mark action is acted primarily as, its identification data may be located at the head of test bit stream data, it is also possible to positioned at test bit stream number
According to afterbody, naturally it is also possible to while positioned at test bit stream data head and afterbody.
S103：Corresponding write is generated according to configuration interface message or clock signal is read and is input into test execution platform.
It should be noted that in the present embodiment clock signal can be generated by configuring interface sequence generator, and configure
Interface sequence generator can generate write or read clock signal according to the configuration interface message that case-based system device gets.
S104：According to clock signal, the test bit stream data that configuration data maker is exported is written to into configuration control system
The design to be measured of system is tested.
It should be appreciated that the present embodiment S104 steps can be performed by test execution platform.
It is described further to carrying out test to the design to be measured of configuration control system in the present embodiment below.
It is shown in Figure 2, the testing process that the design to be measured for configuring control system is performed is included in the present embodiment：
S201：According to the clock signal for receiving will test bit stream data be respectively written into configuration the to be measured of control system set
In meter and simulator.
For S201, can realize that the configuration interface sequence in said process, and the present embodiment is sent out by driver
The clock signal that raw device is generated can be input in driver, meanwhile, the test that the configuration data maker in the present embodiment is generated
Bit stream data can also be input into into driver.
S202：The reference model of the design to be measured comprising configuration control system in simulator, and according to the test position of input
Flow data produces simulation result and exports into checker.
S203：The operation result of the design to be measured according to test bit stream data output of configuration control system is obtained, and should
As a result export into checker.
It should be appreciated that in the present embodiment the design to be measured of configuration control system can be obtained according to survey by monitor
The operation result of examination bit stream data output, dividing for the no priorities of the S202 in the present embodiment and S203 can first carry out S203 again
Perform S202.
S204：Checker carries out checking treatment and obtains test result to the simulation result that receives and operation result.
In addition also, it should be noted that can also be directly defeated to the design to be measured of configuration control system by asserting controller
Enter additional test and excitation, now assert controller can with configuration control system design to be measured in excitation input interface connect
Connect, it is to be understood that when by asserting that controller is input into additional test and excitation to the design to be measured of configuration control system,
Same additional test and excitation can be input into in simulator.It is understood that the configuration data maker in the present embodiment
Random test data can be only generated, nominative testing data now just can be by asserting controller to configuration control system
Design input to be measured, while the specified data also will be input into into simulator.
Further, it is also possible to will assert that controller is connected with the monitoring position in the design to be measured of configuration control system, assert
Controller can extract the signal of the monitoring position and be monitored.
In addition also, it should be noted that memory cell in the design to be measured of the configuration control system in the present embodiment is retouched
It can be the array descriptor format that whole description is carried out from array functional layer to state form, it is, for example possible to use register type
Verilog (hardware description language) describing mode carries out the description of array memory cell, can so shorten emulation and compile
Time, processing speed in simulator is made faster, so as to improve simulation efficiency.
FPGA provided in an embodiment of the present invention configures control system method of testing, is generated by configuration data maker and is tested
Bit stream data is input into test execution platform, wherein test bit stream data includes nominative testing data and random test data,
Such that it is able to verify performance situation of the configuration control system under each situation, the standard of test checking configuration control system is improve
Really property, also can save the regular hour relative to test bit stream data is generated by software kit instrument in prior art.
Embodiment two：
The present embodiment provides a kind of FPGA configuration control system testing and controls platform 30, specifically may refer to shown in Fig. 3,
Including case-based system device 31, configuration data maker 32 and configuration interface sequence generator 33.
Wherein, case-based system device 31 is used to obtain the test case that the design to be measured to configuring control system is tested.
Test case in the present embodiment includes the generation constraint bar of at least part of configuration data being related in testing process, testing process
Part and configuration interface message.And it should be noted that the design to be measured in the present embodiment can be the electricity for realizing certain function
Design on road.
Configuration data maker 32 in the present embodiment is used in the test case got according to case-based system device 31
Testing process and generation constraints generate test bit stream data and are input into test execution platform；Test position in the present embodiment
It is related to but without generation constraint bar comprising the nominative testing data generated according to constraints and for testing process in flow data
The random test data that the configuration data of part is generated.
It should be noted that the configuration data maker 32 in the present embodiment includes at least one in following generator：
Configuration register automatically generates device, for producing specified configuration register data according to generation constraints, and/or
Randomly generate random arrangement register data；
Configuration data storage automatically generates device, for producing the finger for being configured to FPGA memory cell according to generation constraints
Fixed number evidence, and/or randomly generate the random data for being configured to FPGA memory cell；
Clear data generator；For producing the clear data waited for clock handover configurations or for the time.
Configuration data recognizes Content Generator, for producing the mark data that unique mark tests bit stream data.
That is to say, the configuration data maker 32 in the present embodiment can only include any one in above-mentioned generator,
Or including any two kinds, three kinds in above-mentioned generator, or can also can simultaneously include four kinds of above-mentioned generators.Example
Such as, the configuration data maker 32 in the present embodiment can including configuration register automatically generate device, configuration data storage it is automatic
Generator and configuration data identification Content Generator.Shown in Figure 4, Fig. 4 is when the configuration data in the present embodiment is generated
Device 32 automatically generates device 321, configuration data storage and automatically generates device 322, clear data generator including configuration register simultaneously
323 and configuration data identification Content Generator 324 when, the structural representation of its four kinds of generators.
It should be appreciated that the configuration register in the present embodiment automatically generates device can be specified according to constraints generation
Configuration register data and randomly generate random arrangement register data, it is also possible to only produce specified configuration register data or only
Produce random arrangement register data.Specifically, the configuration register in the present embodiment automatically generate device can produce it is various
The content of configuration register, including control register, command register, bit wide identification register, user register and other
Register and self-defining register for identification etc., is mainly used in arranging bit wide identification, the controlling party of configuration data storage
Formula, interfaces mode, verification calculation, Read-write Catrol mode, encryption and decryption control mode etc., control bit in control register
The randomization of conditional combination mode can be carried out according to the principle not conflicted with command bit in command register and produce controlling value.
Likewise, the configuration data storage in the present embodiment automatically generates device can be configured to according to constraints generation
The director data of FPGA memory cell and randomly generate the random data for being configured to FPGA memory cell, or can also only produce
Specified data only produce random data.
Clear data generator in the present embodiment can produce the blank number waited for clock handover configurations or for the time
It is filling content according to, clear data, without function, and when can be that the processes such as clock switching, pattern switching reserve enough
Between come complete operation.It should be appreciated that the size and location of the clear data in the present embodiment can be advance by developer
Set, it is also possible to support User Defined.
The mark data that configuration data identification Content Generator in the present embodiment is generated can be a fixed data,
Mark action is acted primarily as, its identification data may be located at the head of test bit stream data, it is also possible to positioned at test bit stream data
Afterbody, naturally it is also possible to while positioned at test bit stream data head and afterbody.It should be appreciated that when to single configuration control
When the design to be measured of system processed is tested, it is also possible to do not need configuration data identification Content Generator to produce mark data.When
So, can be according to the corresponding product of the setting of design to be measured in the FPGA configuration control system testing and controls platform 30 in the present embodiment
Raw device, the combination of concrete generator can be arranged flexibly.
Configuration interface sequence generator 33 in the present embodiment is used to generate corresponding writing according to the configuration interface message
Enter or read clock signal to be input into the test execution platform, so that the test execution platform writes the test bit stream data
The design to be measured for entering the configuration control system is tested.
The FPGA configuration control system testing and controls platform 30 that the present embodiment is provided can also include asserting controller.This reality
Apply and controller is asserted in example for being connected with the excitation input interface in the design to be measured of configuration control system, for directly to matching somebody with somebody
The design to be measured for putting control system is input into additional test and excitation；
And/or,
Controller is asserted for being connected with the monitoring position in the design to be measured of configuration control system, for extracting monitoring position
The signal put is monitored.
That is to say, controller can be used for directly to the design to be measured input of configuration control system asserting in the present embodiment
While additional test and excitation, it is also possible to be monitored for a certain monitoring position in design to be measured, it is also possible to while tool
There are above-mentioned functions.As such, it is possible to it is more directly perceived, more easily add additional test and excitation or increase monitoring position carry out it is more detailed
Thin signal detection so that the quality of test checking is preferably ensured.
Certainly, assert that controller is input into additional survey to the design to be measured of configuration control system when what is provided by the present embodiment
During examination excitation, it is also possible to same additional test and excitation is input into in simulator.It is understood that the configuration in the present embodiment
Data Generator 32 can only generate random test data, and nominative testing data now just can be by asserting controller to matching somebody with somebody
The design to be measured input of control system is put, while the specified data also will be input into into simulator.
The FPGA provided by the present embodiment configures control system testing and control platform 30, can directly pass through configuration data
Maker 32 generates the test bit stream data for test, can lift testing efficiency, and due to the test bit stream number for generating
According to randomness, therefore the accuracy that configuration control system tests the result can be improved.
Embodiment three：
Shown in Figure 5, the present embodiment provides a kind of FPGA configuration control systems test and verification platform 50, including test
Perform platform 34 and any one above-mentioned FPGA configuration control system testing and controls platform 30.
Here, it should be noted that the FPGA configuration control system testing and controls platform 30 in the present embodiment can be with integrated
In FPGA configuration control systems test and verification platform 50, the overall time of validation test can be so saved, this enforcement certainly
FPGA configuration control system testing and controls platform 30 in example can also configure control system test and verification platform independently of FPGA
It is extra beyond 50 to arrange.
Test execution platform 34 in the present embodiment is used for the clock signal according to the output of configuration interface sequence generator 33,
The test bit stream data that configuration data maker 32 is exported is written to the design to be measured of configuration control system and is tested.
Shown in Figure 6, the test execution platform 34 that the present embodiment is provided can include driver 341, simulator
342nd, monitor 344 and checker 345.
Driver 341 in the present embodiment is used to be configured according to the clock signal of the output of configuration interface sequence generator 33
The bit stream data of the output of Data Generator 32 is respectively written into the design 343 to be measured of configuration control system and simulator 342.
The reference model of the design to be measured comprising configuration control system in simulator 342, for according to the bit stream number of input
Export to checker 345 according to simulation result is produced；
Monitor 344 is used to obtain the operation knot of the design to be measured according to test bit stream data output of configuration control system
Really, and by operation result export to checker 345；
Checker 345 is used for the simulation result to receiving and operation result to carry out checking treatment and obtains test result.
When the FPGA configuration control systems test and verification platform 50 that the present embodiment is provided includes asserting controller 35, this
FPGA configuration control systems test and verification platform 50 in embodiment may refer to shown in Fig. 7.
In addition also, it should be noted that memory cell in the design to be measured of the configuration control system in the present embodiment is retouched
It can be the array descriptor format that whole description is carried out from array functional layer to state form, it is, for example possible to use register type
Verilog (hardware description language) describing mode carries out the description of array memory cell, thus, verification platform 50 is in compiling
More preferable process of compilation and integrated treatment can be obtained, the netlist comprehensively drawn during simulation run can be made more simplified, be greatly reduced
The system consumption of simulation software, so as to shorten the compilation time and simulation time of emulation, so as to the test for shortening overall is tested
The card time, and then improve simulation efficiency.
The FPGA provided by the present embodiment configures control system test and verification platform, produces the mode of test bit stream data
It is no longer dependent on software kit instrument, it is possible to reduce software kit instrument produces test bit stream data and read test bit stream number
According to the flow process for wasting time and energy, such that it is able to reduce the time of test checking, produced due to device can be automatically generated by configuration data
The random test bit stream data of life, compared to software kit instrument fixed test bit stream data can only be produced, and enable to test
Card platform validation verifies the standard for configuring control system design to be measured to the leak at many dead angles of design to be measured so as to improve test
True property.
Obviously, those skilled in the art should be understood that each module or each step of the embodiments of the present invention can be used
Realizing, they can be concentrated on single computing device general computing device, or be distributed in multiple computing device institutes
On the network of composition, alternatively, they can be realized with the executable program code of computing device, it is thus possible to by they
It is stored in computer-readable storage medium (ROM/RAM, magnetic disc, CD) and is performed by computing device, and in some cases, can
To perform shown or described step with the order being different from herein, or they are fabricated to respectively each integrated circuit die
Block, or the multiple modules or step in them are fabricated to single integrated circuit module to realize.So, the present invention is not limited
Combine in any specific hardware and software.
Above content is to combine the further description that specific embodiment is made to the embodiment of the present invention, it is impossible to recognized
Being embodied as of the fixed present invention is confined to these explanations.For general technical staff of the technical field of the invention,
Without departing from the inventive concept of the premise, some simple deduction or replace can also be made, the present invention should be all considered as belonging to
Protection domain.
Claims (10)
1. a kind of FPGA configures control system testing and control platform, it is characterised in that include：
Case-based system device, the test case that the design to be measured for obtaining to configuring control system is tested, the test reality
Example includes the generation constraints of at least part of configuration data being related in testing process, testing process and configuration interface letter
Breath；
Configuration data maker, it is defeated for generating test bit stream data according to the testing process and the generation constraints
Enter to test execution platform；In the test bit stream data comprising according to the constraints generate nominative testing data and
The random test data for being related to for the testing process but being generated without the configuration data for generating constraints；
Configuration interface sequence generator, for defeated according to the corresponding write of the configuration interface message generation or reading clock signal
Enter to the test execution platform, so that the test bit stream data is write the configuration control system by the test execution platform
Design to be measured tested.
2. FPGA as claimed in claim 1 configures control system testing and control platform, it is characterised in that the configuration data life
Grow up to be a useful person including at least one in following generator：
Configuration register automatically generates device, for producing specified configuration register data according to the generation constraints, and/or
Randomly generate random arrangement register data；
Configuration data storage automatically generates device, for producing the finger for being configured to FPGA memory cell according to the generation constraints
Fixed number evidence, and/or randomly generate the random data for being configured to FPGA memory cell；
Clear data generator；For producing the clear data waited for clock handover configurations or for the time.
Configuration data recognizes Content Generator, for producing the mark data that bit stream data is tested described in unique mark.
3. FPGA as claimed in claim 1 configures control system testing and control platform, it is characterised in that also including asserting control
Device；
It is described to assert controller for being connected with the excitation input interface in the design to be measured of the configuration control system, for straight
Connect to the design to be measured of the configuration control system and be input into additional test and excitation；
And/or,
It is described to assert controller for being connected with the monitoring position in the design to be measured of the configuration control system, for extracting
The signal for stating monitoring position is monitored.
4. a kind of FPGA configures control system test and verification platform, it is characterised in that including test execution platform and such as right
Require the FPGA configuration control system testing and control platforms described in any one of 1-3；
The test execution platform is used for the clock signal according to the configuration interface sequence generator output, by the configuration number
The design to be measured of the test bit stream data write configuration control system exported according to maker is tested.
5. FPGA as claimed in claim 4 configures control system test and verification platform, it is characterised in that the test execution is put down
Platform includes driver, simulator, monitor and checker；
The driver is used to be generated the configuration data according to the clock signal of the configuration interface sequence generator output
The bit stream data of device output is respectively written into the design to be measured of the configuration control system and simulator；
The reference model of the design to be measured comprising the configuration control system in the simulator, for according to the bit stream number of input
Export to the checker according to simulation result is produced；
The monitor is used to obtain the fortune of the design to be measured according to the test bit stream data output of the configuration control system
Row result, and the operation result is exported to the checker；
The checker is used for the simulation result to receiving and operation result to carry out checking treatment and obtains test result.
6. the FPGA as described in claim 4 or 5 configures control system test and verification platform, it is characterised in that the configuration control
The descriptor format of the memory cell in the design to be measured of system processed is the array description that whole description is carried out from array functional layer
Form.
7. a kind of FPGA configures control system method of testing, it is characterised in that include：
Obtain the test case tested of design to be measured to configuring control system, the test case include testing process,
The generation constraints and configuration interface message of at least part of configuration data being related in testing process；
Test bit stream data is generated according to the testing process and the generation constraints to be input into test execution platform；Institute
State and related to comprising the nominative testing data generated according to the constraints and for the testing process in test bit stream data
And but without the random test data that generated of configuration data for generating constraints；
Corresponding write is generated according to the configuration interface message or clock signal is read；
According to the clock signal, the test bit stream data write that the configuration data maker the is exported configuration control system
The design to be measured of system is tested.
8. FPGA as claimed in claim 7 configures control system method of testing, it is characterised in that the configuration data maker
Test bit stream data is generated including at least one in situations below according to the testing process and the generation constraints：
Configuration register automatically generates device according to the generation constraints generation specified configuration register data, and/or at random
Produce random arrangement register data；
Configuration data storage automatically generates device and the specified number for being configured to FPGA memory cell is produced according to the generation constraints
According to, and/or randomly generate the random data for being configured to FPGA memory cell；
Clear data generator produces the clear data waited for clock handover configurations or for the time.
Configuration data identification Content Generator produces the mark data that bit stream data is tested described in unique mark.
9. FPGA as claimed in claim 7 configures control system method of testing, it is characterised in that also include：
Treating for control system is directly configured to described by the excitation input interface in the design to be measured of the configuration control system
Survey the additional test and excitation of design input；
And/or,
The signal for extracting the monitoring position in the design to be measured of the configuration control system is monitored.
10. the FPGA as described in any one of claim 7-9 configures control system method of testing, it is characterised in that according to described
Clock signal, the design to be measured of the test bit stream data write configuration control system that the configuration data maker is exported
Carrying out test includes：
According to the clock signal by it is described test bit stream data be respectively written into it is described configuration control system design to be measured and
Simulator, the reference model of the design to be measured comprising the configuration control system in the simulator；
The simulator produces simulation result and exports to checker according to the test bit stream data of input；
The operation result of the design to be measured according to the test bit stream data output of the configuration control system is obtained, and will be described
Operation result is exported to the checker；
Checker carries out checking treatment and obtains test result to the simulation result that receives and operation result.
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101996265A (en) * | 2009-08-25 | 2011-03-30 | 安凯(广州)微电子技术有限公司 | Verification system and method for memory controller |
| CN102109572A (en) * | 2009-12-23 | 2011-06-29 | 中兴通讯股份有限公司 | Method for testing and method for testing and controlling transmission chip |
| CN103558543A (en) * | 2013-11-20 | 2014-02-05 | 太仓思比科微电子技术有限公司 | Mass production testing method of CIS chip |
| CN103713281A (en) * | 2013-12-12 | 2014-04-09 | 中国人民解放军海军工程大学 | Radar signal unit performance test and fault diagnosis system based on general test platform |
| CN105425201A (en) * | 2015-12-11 | 2016-03-23 | 中国电力科学研究院 | Metering chip simulation test method used for intelligent electric energy meter software reliability detection |
| CN105654993A (en) * | 2016-02-22 | 2016-06-08 | 深圳市同创国芯电子有限公司 | Function verification method and platform for DDR3 SDRAM (double data rate 3 synchronous dynamic random access memory) controller |
| CN105760296A (en) * | 2016-01-21 | 2016-07-13 | 深圳市同创国芯电子有限公司 | Automation testing control method, device and terminal |
-
2016
- 2016-12-09 CN CN201611132486.XA patent/CN106647700B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101996265A (en) * | 2009-08-25 | 2011-03-30 | 安凯(广州)微电子技术有限公司 | Verification system and method for memory controller |
| CN102109572A (en) * | 2009-12-23 | 2011-06-29 | 中兴通讯股份有限公司 | Method for testing and method for testing and controlling transmission chip |
| CN103558543A (en) * | 2013-11-20 | 2014-02-05 | 太仓思比科微电子技术有限公司 | Mass production testing method of CIS chip |
| CN103713281A (en) * | 2013-12-12 | 2014-04-09 | 中国人民解放军海军工程大学 | Radar signal unit performance test and fault diagnosis system based on general test platform |
| CN105425201A (en) * | 2015-12-11 | 2016-03-23 | 中国电力科学研究院 | Metering chip simulation test method used for intelligent electric energy meter software reliability detection |
| CN105760296A (en) * | 2016-01-21 | 2016-07-13 | 深圳市同创国芯电子有限公司 | Automation testing control method, device and terminal |
| CN105654993A (en) * | 2016-02-22 | 2016-06-08 | 深圳市同创国芯电子有限公司 | Function verification method and platform for DDR3 SDRAM (double data rate 3 synchronous dynamic random access memory) controller |
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