CN106525231A - Multi-photon coincidence counter based on programmable logic device - Google Patents
Multi-photon coincidence counter based on programmable logic device Download PDFInfo
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Abstract
The invention discloses a multi-photon coincidence counter based on a programmable logic device. Based on the large capacity of a DDR, the simultaneous counting of multiple coincidence types can be supported, a diversion mechanism is used to solve the problem of insufficient DDR reading and writing speeds, and the event rate of a coincidence system is improved. Moreover, through introducing pulse shaping and a synchronous clock, the generation of accidental coincidence can be inhibited dually. At the same time, pulse time delay can be dynamically adjusted, since the IO resource of an FPGA is employed, the adjustment precision reaches tens of picoseconds, and the linearity is good. The problem that the consistency may not be guaranteed in each time due to the time delay of an input signal is solved by dynamic adjustment. Moreover, a scanning mechanism is introduced, and thus in the condition of knowing single channel counting distribution, the correctness of a coincidence result can be extrapolated. In addition, a PC can know a system working state according to a state word and adjust a system parameter through the control word, thus the working flow is automated, and the robustness of the system is improved.
Description
Technical field
The present invention relates to photon counting field, more particularly to a kind of multi-photon coincidence counting based on PLD
Device.
Background technology
It is a kind of peculiar quantum appearance that multi-photon is tangled, and which is in research quantum simulator, quantum error correction and quantum mould
All it is indispensable resource in the research of plan.Number of photons is more, and the degree of freedom of single photon is bigger, multi-photon system process letter
The ability of breath is stronger.In newest experiment progress, tangling for eight photons is achieved.
Tangle in experiment in multi-photon, this Quantum Properties will be tangled and be converted into the amount needs that our world of experiences can be observed
Counting statisticses are carried out to number of photons, is a kind of process of many bodies due to tangling, so it is coincidence counting to count.Coincidence counter
Function is that meeting between two or more signals is judged and counted.
2005, Gaertner et al. proposed the scheme of address of cache.As shown in figure 1, system is by probe unit is met, first
Enter buffer (FIFO), random access memory (RAM) compositions on microcontroller and piece.Meet probe unit
Operation principle be using input signal take logic or after signal as sample trigger, sample the pattern that obtains as the ground of enumerator
Location is cached to FIFO.
2015, BYUNG KWON PARK et al. also achieved the enumerator that eight bodies meet with door on FPGA.As schemed
Shown in 2, the system integration wherein comprising time delay module, pulse shaping module, meets signal generator on FPGA, enumerator and
Processor, FPGA are turned USB by serial ports and are communicated with PC.The principle for meeting signal generator be by Port Multiplier gate multi input with
Determining to meet configuration, each multi input one kind corresponding with door meets species to door.
In optical quantum communication and light quantum are calculated, usually require that measurement multi-photon meets event, the experiment of eight photons is led to
Road number has reached 16, meets species up to 216- 1, reject some it is insignificant meet, meet species be at least also geometry increase
Long, meanwhile, light-source brightness also reaches single channel counting rate megahertz, the level that ten megahertzs of system event rate.With experiment
The fast development of technology, port number and light-source brightness can all be continuously increased.
But, the scheme of Gaertner realizes arbitrarily meeting for eight passages, simply can not expand to dozens of
Passage because it is that, with port number exponential increase, incident rate can also be increased to meet species, now the capacity of memorizer and
Speed can become bottleneck.The integrated level of discrete device and motility also cannot be matched in excellence or beauty with FPGA.The more importantly event of system
Rate is 0.8MHz, and the dead time is 14ns, it is impossible to read them in real time, therefore can not meet current experiment demand.
Meanwhile, although the scheme minimum of PARK meets window for 0.47ns, maximum incoming frequency is 163MHz, due to
Arrive and door, simultaneously the prior several situations that meet for selecting can only have been counted.After port number increases to dozens of, with door
Line will become very complicated.
The content of the invention
It is an object of the invention to provide a kind of multi-photon coincidence counter based on PLD, by FPGA
On realize several tens of channels, tens of megahertzs of example rates meet that species is more, and below random signals 1ppm reads in real time and counts, from
Dynamicization and prolongable multi-photon coincidence counter scheme, the coincidence counter are also applicable in particle physicses experiment.
The purpose of the present invention is achieved through the following technical solutions：
A kind of multi-photon coincidence counter based on PLD, including：Fpga chip, DDR and PC；Wherein：
The fpga chip, the N roads electric pulse for receiving carry out delay adjustment, integer operation, sampling, symbol successively
It is stored in after logical judgement in corresponding FIFO, then coincidence counting is carried out by the enumerator being connected with corresponding FIFO and operates；On
The trigger condition for stating sampling is the clock signal of fpga chip internal clocking management module output；
The DDR is controlled by the MCB in fpga chip, for storing the coincidence counting of corresponding counter；
The PC, for the coincidence counting that reads inside DDR and fpga chip in Block RAM and carries out post processing.
Further, the fpga chip includes：Delay unit, pulse shaping unit, sample register, meet logic and sentence
Disconnected module, Clock management module, Block RAM FIFO and the first enumerator, DDR FIFO and the second enumerator, Block
RAM, WISHBONE bus and MCB；Wherein：
The delay unit, carries out delay adjustment for the N roads electric pulse to receiving so that N roads electric pulse is completely right
Together；
The pulse shaping unit, for being burst pulse by the N roads electric pulses integer after alignment；
The Clock management module, for exporting corresponding clock signal after the synchronised clock for receiving laser instrument offer
As the trigger condition of sampling；
The sample register, for storing sampled result；
The logic judgment module that meets has diverter function, for according to predetermined judgment mode to sampled result successively
Carry out meeting logical judgment, and according to judged result met accordingly address of cache send to Block RAM FIFO or
DDR FIFO；
First enumerator is connected with Block RAM FIFO, and second enumerator is connected with DDR FIFO, two
Enumerator is used to coincidence counting；The count results of first enumerator are stored in Block RAM, the meter of the second enumerator
Number result is stored in DDR by MCB；
The WISHBONE buses are connected with PC by USB interface, for reading and writing the data in Block RAM and DDR, with
And to delay unit and write control word in Clock management module and reading state word.
Further, delay adjustment adopts scan mechanism with sampling, and its step is as follows：
The first step, the phase place of Clock management module is adjusted to into minimum；
Second step, Clock management module often increase by a unit of phase, and all passages are carried out with the single channel meter of certain hour
Number, when phase place reaches maximum, as the distribution for counting reflects the waveform of pulse, you can learn all pulses whether all in scanning
In the range of；If not, then it represents that time delay exceeds dynamic regulation scope, start until institute from the first step Jing after manually adding and subtracting line length again
There is pulse all in sweep limitss；
, by all pulse centers to the maximum pulse center alignment of time delay, the center defines for 3rd step, regulation delay unit
For pulse center；
4th step, adjust Clock management module by clock sampling edge align pulse center.
Further, meet logic judgment module to send out the counting rate high species address that meets according to predetermined judgment mode
Block RAM FIFO are delivered to, remaining is met into species address and is sent to DDR FIFO.
Further, Block RAM and MCB include dual-port, and one of port is used for enumerator, another end
Confession PC passes through WISHBONE bus access；Two ports of Block RAM can not carry out write operation to same address simultaneously,
Two ports share bandwidth of MCB, i.e., two port data rates add up the bandwidth less than DDR.
Further, delay unit, Clock management module, and Block RAM FIFO and DDR FIFO be equipped with state
Word, PC obtain current system working condition by status word；Which includes：Clock is abnormal when in sync, Block RAM FIFO or
DDR FIFO write full, and PC can point out error message；Afterwards, PC attempts restarting automatically adopting number, adopts several processes and terminates, and data are automatic
Preserve into PC；
PC controls delay unit and Clock management mould also by writing control word to delay unit and Clock management module
The working method of block；Which includes：Write control word to control the delay adjustment process of electric pulse to delay unit；To Clock management
Module writes control word to adjust dynamic dephasing processes.
Further, the method also includes：Meet address using meet logic judgment module described in predetermined way change
Mapping scheme.
As seen from the above technical solution provided by the invention, 1) Large Copacity of DDR is caused to more meeting species
Can be counted simultaneously.2) shunting mechanism solves the problems, such as that DDR read or write speeds are slow, improves the incident rate for meeting system.
3) generation of double inhibition random signals is capable of in the introducing of pulse shaping and synchronised clock.4) pulse delay can with dynamic regulation,
As a result of the I/O resource of FPGA, degree of regulation is up to tens psecs, and the linearity is good.Dynamic regulation solves input signal
Time delay may not ensure every time consistent problem.5) synchronised clock can introduce scan mechanism with dynamic phase shift so that
In the case of Single-pass count distribution, extrapolated can meet the correctness of result, must be known by test better than prior art
Whether consistent with expection meet signal meets result scheme.6) when counting statisticses are carried out, coincidence counting can read, only
Speed to be read and write would not cause counting loss in DDR bandwidth.7) PC can learn working state of system according to status word, then
By control word de-regulation systematic parameter, workflow automation is made, while increased system robustness.8) meet logic can be again
Configuration, therefore in system speed, capacity permissible range, can be applicable to difference and meet experiment.9) structure is portable high.
Description of the drawings
In order to be illustrated more clearly that the technical scheme of the embodiment of the present invention, below will be to using needed for embodiment description
Accompanying drawing be briefly described, it should be apparent that, drawings in the following description are only some embodiments of the present invention, for this
For the those of ordinary skill in field, on the premise of not paying creative work, can be obtaining other according to these accompanying drawings
Accompanying drawing.
The address-mapping schemes schematic diagram that Fig. 1 is provided for background of invention；Wherein, (a) it is structured flowchart；B () is
Meet probe unit detailed structure view；
Fig. 2 for background of invention provide on FPGA with the schematic diagram that eight body coincidence counters are realized with door；Its
In, it is (a) overall plan structured flowchart；B () is to meet signal generator structure chart；
Fig. 3 is a kind of multi-photon coincidence counter based on PLD provided in an embodiment of the present invention；Wherein,
The schematic diagram of (a) for overall plan；B () is fpga logic structure chart；
Fig. 4 be pulse delay provided in an embodiment of the present invention, integer, the sequential chart of sampling process；Wherein, (a)～(d) according to
It is secondary to be：Sequential chart, the sequential chart after integer after the sequential chart of initial signal, time delay, according to the sequential chart of clock sampling
Fig. 5 is scan method flow chart provided in an embodiment of the present invention.
Specific embodiment
With reference to the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Ground description, it is clear that described embodiment is only a part of embodiment of the invention, rather than the embodiment of whole.Based on this
Inventive embodiment, the every other enforcement obtained under the premise of creative work is not made by those of ordinary skill in the art
Example, belongs to protection scope of the present invention.
The embodiment of the present invention provides a kind of multi-photon coincidence counter based on PLD；The multi-photon meets
Enumerator mainly contains judgement and meets species the fpga chip for being counted, the synchronised clock that laser instrument is provided, for depositing
Substantial amounts of Double Data Rate Synchronous Dynamic RAM (DDR) for meeting data of storage and dynamic adjustment symbol
Close parameter and read the PC (PC) of coincidence counting.
Fpga chip contains substantial amounts of programmable logic resource, but only when user will be these logical resources organically mutual
Connection company is integral, can just complete specific task.The fpga logic of the present invention includes delay unit, pulse shaping unit, adopts
Sample depositor, meet logic judgment module, Clock management module, Block RAM FIFO and the first enumerator, DDR FIFO and
Second enumerator, Block RAM, WISHBONE buses (WISHBONE Bus) and MCB (Memory Controller
Block)。
DDR has capacity big, and fireballing advantage is suitable as meeting the memorizer of data.When port number is n, symbol
Close species and have 2n- 1, exponentially increase.If port number is 20, data width is 32bit, and required memory capacity is
32Mbit, therefore the limited SRAM of capacity do not apply to.
In the embodiment of the present invention, solve the problems, such as that using shunting mechanism DDR read or write speeds are inadequate, improve to meet and be
The incident rate of system.That is, sampled result is carried out meeting logic successively according to predetermined judgment mode by meeting logic judgment module
Judge, and according to judged result by corresponding data is activation to Block RAM FIFO or DDR FIFO；Again by counting accordingly
Number device reads the address of FIFO cachings, and the data of RAM (Block RAM FIFO or DDR FIFO) appropriate address are counted
Number.
Additionally, can also avoid counting loss using above-mentioned shunting mechanism.Assume data bit wide be 64bit, counting operation
It is required that reading data add one and write back, example rate is 30MHz, then data volume is 3840Mbps, depends DDR alone and is possible to process completely
Cause to lose number.And above-mentioned shunting mechanism is based on, DDR readings data add to write back in the lump and meet only for a part, another part symbol
Close Block RAM that (can be counting rate big meet data) be branched in fpga chip to process, as its speed is compared with DDR
Faster, it is ensured that the integrity of data.But the limited storage space of Block RAM, therefore the scheme of shunting should be appropriate according to experiment
Choose.
There is dark noise and environment noise in detector signal, by meeting referred to as random signals caused by noise.Accidentally
Meeting to cause the result of mistake, be that we are undesirable.To reduce the probability that random signals occur, this invention takes
Dual measure, is that compression meets window, next to that the use of synchronised clock first.Only could accord with meeting the pulse in window
Close, affect the parameter for meeting window to be pulse width in the present invention, therefore narrow arteries and veins is compressed into prepulse Jing integer unit is met
Punching, this compression do not affect the time that rising edge occurs.Make sampling triggering with synchronised clock, rather than with the pulse for occurring at first
Trigger, eliminate the possibility of false triggering.
In multi-photon experimentation, laboratory technician need to obtain some countings for meeting in real time and carry out regulation experiment parameter, also exist
Carry out when long-time adopts several if it find that stopping experiment immediately by counting of abnormal, has saved the time.In order to realize count into
The function of data can also be read during row, the design of Block RAM and MCB using dual-port, a port are used for enumerator, separately
A port is accessed for USB.Two ports of Block RAM can not carry out write operation, two ends of MCB simultaneously to same address
Mouthful shared bandwidth, as long as USB reads, data transfer rate is not too big, i.e., two port data rates add up the bandwidth less than DDR, just
Do not result in and lose several problems.
If adopting several processes needs the artificial mechanically actuated step by step of laboratory technician, the waste of human resourcess can be caused.The present invention
Number is adopted by energy automatization, aside earnestly waits without the need for laboratory technician.PC obtains current system working condition by status word, then passes through
Control word regulating system parameter.Delay unit, Clock management module, two FIFO are designed with status word.Clock exception when in sync,
Block RAM FIFO or DDR FIFO write full, and PC can point out error message, and attempt restarting automatically adopting number.Adopt several processes
Terminate, data are automatically saved in PC.Additionally, PC is controlled also by writing control word with Clock management module to delay unit
The working method of delay unit and Clock management module；Which includes：Write control word to control prolonging for electric pulse to delay unit
When adjust process；Dynamic dephasing processes are adjusted to Clock management module write state word.
Different experiments has different demands that meet, such as port number, meets species, or even same experiment can also occur to become
Change.If the same set of system that meets can apply to these different scenes, objective time and fund will be saved.As FPGA has
Reconfigurable characteristic, for different demands, as long as port number, restriction of the data volume without departing from system, change meet logic
, realize the recycling of same set of hardware.
In order to make it easy to understand, being described in detail to such scheme of the present invention below in conjunction with the accompanying drawings.
Fig. 3 is a kind of multi-photon coincidence counter based on PLD provided in an embodiment of the present invention；Wherein,
The schematic diagram of (a) for overall plan；(b) fpga logic structure chart.
In the schematic diagram of the overall plan as shown in Fig. 3 (a), dotted arrow is optical signal, and other arrows are the signal of telecommunication.Swash
Light (laser) is incident in optical system (Optical System), is spatially separated into n light path respectively by n single-photon detecting
Survey device to receive, be converted into n roads electric pulse.Electric pulse first passes through discriminator and is converted into 3.3V TTL signals, then is managed by common IO
Foot is input into fpga chip (FPGA Chip), and laser instrument is input into one with laser pulse synchronization by clock dedicated pin
76MHz clocks are to fpga chip.Fpga chip is connected with DDR and USB chips by PCB layout, PC again by USB cable with
USB chips are connected.
The major function of above-mentioned fpga chip, DDR and PC is as follows：Fpga chip, for the N roads electric pulse that will receive according to
It is secondary carry out delay adjustment, integer operate, sample, meet logical judgment after be encoded to the address of RAM (Block RAM or DDR)
It is stored in corresponding FIFO, then coincidence counting is carried out by the enumerator being connected with corresponding FIFO and operates；DDR is controlled by FPGA cores
MCB in piece, for storing the coincidence counting of corresponding counter；PC, for reading Block RAM inside DDR and fpga chip
In coincidence counting and carry out post processing and control coincidence counter the course of work.
In the embodiment of the present invention, involved concrete numerical value is citing and is not construed as limiting；Exemplary, above-mentioned enforcement
In example, can apply in the experiment of eight photon entanglements, the degree of freedom of each photon is 2, then one has 22× 8=32 logical
Road, i.e., above-mentioned n=32.
Exemplary, fpga chip can select XILINX companies SPARTAN-6XC6SLX16-2CSG324C, and DDR can be with
From Micron Technology MT46H64M16LFCK-5, CY7C68013As of the USB from CYPRESS companies.Can basis
Experimental program is adjusted flexibly each device parameters, for example, selects DDR of the capacity more than 1Gbit, serial of the bandwidth in more than 10MBps
Communication such as kilomega network.
In the embodiment of the present invention, shown in fpga chip internal structure such as Fig. 3 (b), wherein solid arrow is 1bit signals, single
It is many bit signals to hollow arrow, two-way filled arrows are control signal and status signal, and bidirectional hollow arrow is that data are believed
Number.
The fpga chip mainly includes：Delay unit (IODELAY2), pulse shaping unit (Pulse Shaping),
Sample register (Register), meet logic judgment module (Coincidence Logic), Clock management module (DCM),
Block RAM FIFO and the first enumerator, DDR FIFO and the second enumerator, Block RAM, WISHBONE bus and
MCB；Wherein：
The delay unit, carries out delay adjustment for the N roads electric pulse to receiving so that N roads electric pulse is completely right
Together；
The pulse shaping unit, for the N roads electric pulse after alignment is carried out integer for burst pulse；
The Clock management module, for exporting corresponding clock signal after the synchronised clock for receiving laser instrument offer
As the trigger condition of sampling；
The sample register, for storing sampled result；
It is described to meet logic judgment module, for carrying out successively meeting logic to sampled result according to predetermined judgment mode
Judge, and met mapping address accordingly according to judged result to send to Block RAM FIFO or DDR FIFO；
First enumerator is connected with Block RAM FIFO, and second enumerator is connected with DDR FIFO, two
Enumerator is used to coincidence counting；The count results of first enumerator are stored in Block RAM, the meter of the second enumerator
Number result is stored in DDR by MCB；
The WISHBONE buses are connected with PC by USB interface, for reading and writing the data in Block RAM and DDR, with
And to delay unit and write control word in Clock management module and reading state word.
Exemplary, as mentioned before, it is assumed that n=32, then 32 road electric pulses are first by the IODELAY2 in I/O resource
Carry out delay adjustment, the pulse after alignment after integer module is changed into burst pulse by DCM export clock sampling, pulse when
Sequence figure is as shown in figure 4, the input clock of DCM is the synchronised clock that laser instrument is provided.Pattern Jing after sampling meets logical judgment
Module is cached to Block according to two parts, the FIFO of part of cache to DDR, another part is divided into after default judgment mode
RAM FIFO.After the enumerator of Block RAM obtains the data in Block RAM FIFO, read from Block RAM appropriate address
Go out data and to add write back in the lump Block RAM.It is after the enumerator of DDR obtains the data in DDR FIFO, corresponding from DDR by MCB
Address read-outing data adds.WISHBONE buses can be to IODELAY2 and DCM write control words and reading shape
State word, additionally it is possible to the arbitrary data and the arbitrary data read and write in DDR by MCB in direct read/write Block RAM.
USB main equipment in WISHBONE is connected with USB chips by common I/O pin.
For example, the status word of IODELAY2 is busy, indicates whether delay unit is currently in displaced condition, if
To put height, IODELAY2 can not receive new shift instruction to busy.The status word of Clock management module be lock, psdone,
Limit, indicates respectively whether clock locks, and whether phase shift completes, and whether phase place goes beyond the scope.The status word of two FIFO is
Full, indicates whether FIFO is full.WISHBONE buses pass through status word and control word is connected with two FIFO, in Fig. 3 (b) not
Illustrate.
As shown in figure 4, (a) therein～(d) is followed successively by：After sequential chart, integer after the sequential chart of initial signal, time delay
Sequential chart, according to the sequential chart of clock sampling.CH1～CH3,3 tunnel pulses are illustrated in Fig. 4 only.
In the embodiment of the present invention, the alignment and sampling for completing pulse needs the mechanism of scanning, as shown in figure 5, its step
It is as follows：
The first step, the phase place of Clock management module is adjusted to into minimum；
Second step, Clock management module often increase by a unit of phase, and all passages are carried out with the single channel meter of certain hour
Number, when phase place reaches maximum, as the distribution for counting reflects the waveform of pulse, you can learn all pulses whether all in scanning
In the range of；If not, then it represents that time delay exceeds dynamic regulation scope, start until institute from the first step Jing after manually adding and subtracting line length again
There is pulse all in sweep limitss；
, by all pulse centers to the maximum pulse center alignment of time delay, the center defines for 3rd step, regulation delay unit
For pulse center；
4th step, adjust Clock management module by clock sampling edge align pulse center.
It will be understood by those skilled in the art that judgment mode predetermined in meeting logic judgment module can be according to actual feelings
Condition for example, is sent the counting rate high species address that meets to Block RAM FIFO according to predetermined judgment mode adjusting,
Remaining is met species address to send to DDR FIFO.
Exemplary, in the experiment of eight photon entanglements, account for always meeting example as single photon and two photons meet
More than 90%, 20MHz is reached, therefore, meeting logic judgment module can be according to predetermined judgment mode by single photon and two light
Subdata is sent to the fast Block RAM of processing speed, and DDR be enough to deal with more than two photons meeting.
It is just open to discussion after determining shunting scheme to meet address-mapping schemes.Meet counting rate in species it is maximum up to megahertz
Hereby, and once test and be possible to carry out dozens of hour, the bit wide of enumerator is can guarantee that enough to great talent will not overflow, therefore select
Use 64bit bit wides.The species that meets of 32 passages has 232- 1, but wherein have it is many it is invalid meet, a photon corresponding
Can only at most there is one in passage while have meeting for pulse to be defined as effectively meeting, therefore a photon there are 6 kinds of possibility, need
3bit is encoded, the common 24bit of 8 photons.24bit address widths, 64bit data widths, common 1Gbit spaces, so big storage
Space requirement, DDR are preferably to select.
Block RAM do not have the memory space of 1Gbit, therefore the address-mapping schemes of single photon and two photons require ground
Location width is as far as possible little, and address is divided into two parts, and two photons of correspondence, a photon only need to know be which photon, which
Two information of individual passage, photon information account for 3bit, and channel information accounts for 2bit, a photon 5bit, the common 10bit of two photons, such as
Fruit is that single photon meets, then two photon informations are the same.
In the embodiment of the present invention, as fpga chip employs the logical structure as shown in Fig. 3 (b), it is therefore possible to use
The predetermined way change Block RAM's meets address-mapping schemes.It will be understood by those skilled in the art that described predetermined
Mode can be this area usual manner.
The such scheme of the embodiment of the present invention, mainly obtains following beneficial effect：
1) Large Copacity of DDR is allowd to more meeting species while counting.
2) shunting mechanism solves the problems, such as that DDR read or write speeds are inadequate, improves the incident rate for meeting system.
3) generation of double inhibition random signals is capable of in the introducing of pulse shaping and synchronised clock.
4) pulse delay can be with dynamic regulation, and as a result of the I/O resource of FPGA, degree of regulation is up to tens psecs, line
Property degree is good.Dynamic regulation solves the problems, such as that the time delay of input signal may not ensure every time consistent.
5) synchronised clock can introduce scan mechanism with dynamic phase shift so that in the case where Single-pass count distribution is obtained,
Extrapolated can meet the correctness of result, better than prior art must pass through to meet known to test signal meet result whether with advance
Phase consistent scheme.
6) when counting statisticses are carried out, coincidence counting can read, as long as read-write speed would not cause in DDR bandwidth
Counting loss.
7) PC can learn working state of system according to status word, then by control word de-regulation systematic parameter, make work
Process automation, while increased system robustness.
8) meet logic reconfigurable, therefore in system speed, capacity permissible range, can be applicable to difference and meet reality
Test.
9) structure is portable high, the SPARTAN of XILINX companies, and the Series FPGA such as VIRTEX, KINTEX supports this
The structure of invention.
The above, the only present invention preferably specific embodiment, but protection scope of the present invention is not limited thereto,
Any those familiar with the art in the technical scope of present disclosure, the change or replacement that can be readily occurred in,
Should all be included within the scope of the present invention.Therefore, protection scope of the present invention should be with the protection model of claims
Enclose and be defined.
Claims (7)
1. a kind of multi-photon coincidence counter based on PLD, it is characterised in that include：Fpga chip, DDR with
PC；Wherein：
The fpga chip, operates, samples, meeting and patrol for the N for receiving roads electric pulse is carried out delay adjustment, integer successively
Collect and be stored in corresponding FIFO after judging, then coincidence counting is carried out by the enumerator being connected with corresponding FIFO and operate；It is above-mentioned to adopt
The trigger condition of sample is the clock signal of fpga chip internal clocking management module output；
The DDR is controlled by the MCB in fpga chip, for storing the coincidence counting of corresponding counter；
The PC, for the coincidence counting that reads inside DDR and fpga chip in Block RAM and carries out post processing.
2. a kind of multi-photon coincidence counter based on PLD according to claim 1, it is characterised in that
The fpga chip includes：Delay unit, pulse shaping unit, sample register, meet logic judgment module, Clock management mould
Block, Block RAM FIFO and the first enumerator, DDR FIFO and the second enumerator, Block RAM, WISHBONE bus and
MCB；Wherein：
The delay unit, carries out delay adjustment for the N roads electric pulse to receiving so that N roads electric pulse is perfectly aligned；
The pulse shaping unit, for the N roads electric pulse after alignment is carried out integer for burst pulse；
The Clock management module, for exporting corresponding clock signal conduct after the synchronised clock for receiving laser instrument offer
The trigger condition of sampling；
The sample register, for storing sampled result；
The logic judgment module that meets has diverter function, for being carried out to sampled result successively according to predetermined judgment mode
Meet logical judgment, and address of cache is met accordingly according to judged result and send to Block RAM FIFO or DDR
FIFO；
First enumerator is connected with Block RAM FIFO, and second enumerator is connected with DDR FIFO, two countings
Device is used to coincidence counting；The count results of first enumerator are stored in Block RAM, the counting knot of the second enumerator
Fruit is stored in DDR by MCB；
The WISHBONE buses are connected with PC by USB interface, for reading and writing the data in Block RAM and DDR, Yi Jixiang
Control word and reading state word are write in delay unit and Clock management module.
3. a kind of multi-photon coincidence counter based on PLD according to claim 2, it is characterised in that
Delay adjustment adopts scan mechanism with sampling, and its step is as follows：
The first step, the phase place of Clock management module is adjusted to into minimum；
Second step, Clock management module often increase by a unit of phase, and the single channel that all passages are carried out with certain hour is counted, when
Whether phase place reaches maximum, as the distribution for counting reflects the waveform of pulse, you can learn all pulses all in sweep limitss
It is interior；If not, then it represents that time delay exceeds dynamic regulation scope, start until all arteries and veins from the first step Jing after manually adding and subtracting line length again
Punching is all in sweep limitss；
, by all pulse centers to the maximum pulse center alignment of time delay, the center is defined as arteries and veins for 3rd step, regulation delay unit
Rush center；
4th step, adjust Clock management module by clock sampling edge align pulse center.
4. a kind of multi-photon coincidence counter based on PLD according to claim 2, it is characterised in that
Meet logic judgment module the counting rate high species address that meets to be sent to Block according to predetermined judgment mode
Remaining is met species address and is sent to DDR FIFO by RAMFIFO.
5. a kind of multi-photon coincidence counter based on PLD according to claim 2, it is characterised in that
Block RAM and MCB include dual-port, and one of port is used for enumerator, and another port passes through for PC
WISHBONE bus access；Two ports of Block RAM can not carry out write operation, two ends of MCB simultaneously to same address
The shared bandwidth of mouth, i.e., two port data rates add up the bandwidth less than DDR.
6. a kind of multi-photon coincidence counter based on PLD according to claim 2, it is characterised in that
Delay unit, Clock management module, and Block RAM FIFO and DDR FIFO be equipped with status word, PC passes through state
Word obtains current system working condition；Which includes：Clock exception, Block RAM FIFO or DDR FIFO write full when in sync,
PC can point out error message；Afterwards, PC attempts restarting automatically adopting number, adopts several processes and terminates, and data are automatically saved in PC；
PC controls delay unit with Clock management module also by writing control word to delay unit and Clock management module
Working method；Which includes：Write control word to control the delay adjustment process of electric pulse to delay unit；To Clock management module
Write control word to adjust dynamic dephasing processes.
7. a kind of multi-photon coincidence counter based on PLD according to claim 2, it is characterised in that
Also include：Meet address-mapping schemes using meet logic judgment module described in predetermined way change.
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107656881A (en) * | 2017-09-13 | 2018-02-02 | 中国科学院半导体研究所 | Data storage transit system based on FPGA |
| CN108280437A (en) * | 2018-01-30 | 2018-07-13 | 四川新先达测控技术有限公司 | pulse signal processing method, device and user terminal |
| CN109238480A (en) * | 2018-10-19 | 2019-01-18 | 中国科学技术大学 | A kind of multi-photon coincidence counting method and device |
| CN109253808A (en) * | 2018-10-26 | 2019-01-22 | 上海星秒光电科技有限公司 | time coincidence counting system, method and device |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| RU2248534C1 (en) * | 2002-08-09 | 2005-03-20 | Открытое Акционерное Общество "Пеленг" | Device for testing parameters of information channel control laser field |
| US8237475B1 (en) * | 2008-10-08 | 2012-08-07 | Altera Corporation | Techniques for generating PVT compensated phase offset to improve accuracy of a locked loop |
| US20130019053A1 (en) * | 2011-07-14 | 2013-01-17 | Vinay Ashok Somanache | Flash controller hardware architecture for flash devices |
| CN203385484U (en) * | 2013-08-09 | 2014-01-08 | 西安工程大学 | Single-photon counting device |
| CN104848880A (en) * | 2015-05-26 | 2015-08-19 | 电子科技大学 | Quasi-distributed optical sensing device based on light quantum technology |
-
2016
- 2016-10-28 CN CN201610961414.XA patent/CN106525231B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| RU2248534C1 (en) * | 2002-08-09 | 2005-03-20 | Открытое Акционерное Общество "Пеленг" | Device for testing parameters of information channel control laser field |
| US8237475B1 (en) * | 2008-10-08 | 2012-08-07 | Altera Corporation | Techniques for generating PVT compensated phase offset to improve accuracy of a locked loop |
| US20130019053A1 (en) * | 2011-07-14 | 2013-01-17 | Vinay Ashok Somanache | Flash controller hardware architecture for flash devices |
| CN203385484U (en) * | 2013-08-09 | 2014-01-08 | 西安工程大学 | Single-photon counting device |
| CN104848880A (en) * | 2015-05-26 | 2015-08-19 | 电子科技大学 | Quasi-distributed optical sensing device based on light quantum technology |
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107656881A (en) * | 2017-09-13 | 2018-02-02 | 中国科学院半导体研究所 | Data storage transit system based on FPGA |
| CN108280437A (en) * | 2018-01-30 | 2018-07-13 | 四川新先达测控技术有限公司 | pulse signal processing method, device and user terminal |
| CN109324542A (en) * | 2018-09-12 | 2019-02-12 | 中国原子能科学研究院 | A kind of neutron multiplicity measurement Special pulse signal processor |
| CN109272099A (en) * | 2018-09-19 | 2019-01-25 | 上海星秒光电科技有限公司 | Coincidence counting manages method and device |
| CN109238480B (en) * | 2018-10-19 | 2024-02-23 | 中国科学技术大学 | Multiphoton coincidence counting method and device |
| CN109238480A (en) * | 2018-10-19 | 2019-01-18 | 中国科学技术大学 | A kind of multi-photon coincidence counting method and device |
| CN109253808A (en) * | 2018-10-26 | 2019-01-22 | 上海星秒光电科技有限公司 | time coincidence counting system, method and device |
| CN110175095A (en) * | 2019-04-28 | 2019-08-27 | 南京大学 | A kind of multi-functional FPGA coincidence measurement system of man-machine interactive and its measurement method |
| CN110175095B (en) * | 2019-04-28 | 2023-09-22 | 南京大学 | Man-machine interaction type multifunctional FPGA coincidence measurement system and measurement method thereof |
| CN111143273A (en) * | 2019-11-12 | 2020-05-12 | 广东高云半导体科技股份有限公司 | System on chip |
| CN112069095A (en) * | 2020-09-09 | 2020-12-11 | 北京锐马视讯科技有限公司 | DDR3 read-write transmission method and device |
| CN112069095B (en) * | 2020-09-09 | 2022-01-28 | 北京锐马视讯科技有限公司 | DDR3 read-write transmission method and device |
| CN112486247A (en) * | 2020-11-13 | 2021-03-12 | 深圳市贝斯达医疗股份有限公司 | Coincidence controller, realization method thereof and positron emission tomography system |
| CN112486247B (en) * | 2020-11-13 | 2022-07-05 | 深圳市贝斯达医疗股份有限公司 | Coincidence controller, realization method thereof and positron emission tomography system |
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