CN106951587A - FPGA debugging systems and method - Google Patents
FPGA debugging systems and method Download PDFInfo
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- CN106951587A CN106951587A CN201710081184.2A CN201710081184A CN106951587A CN 106951587 A CN106951587 A CN 106951587A CN 201710081184 A CN201710081184 A CN 201710081184A CN 106951587 A CN106951587 A CN 106951587A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
- G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
- G06F30/3312—Timing analysis
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Abstract
FPGA debugging systems and method provided by the present invention, by by the FPGA debugging signal messages write read to capacity is larger and interface bandwidth also memory cell is stored outside enough piece, on the premise of keeping debugging number of signals enough, being substantially improved for signal observation time will be debugged, thus can just avoid existing debud mode inevitably repeatedly select debugging signal and make repeated attempts trigger timing the problem of, also avoid to realize flow to debug to need very time-consuming FPGA is repeated, greatly improve FPGA debugging efficiency.And it can solve the problem that existing debugging technique can not diagnose the abnormal problem of big time span.
Description
Technical field
The present invention relates to chip and FPGA electronic system designs field, more particularly to FPGA debugging systems and method.
Background technology
Field programmable gate array (FPGA) device is widely used in various as a kind of flexible and efficient programming device
In electronic system and the verification system of IC chip exploitation.But FPGA exploitation threshold is higher, especially
It is that its debugging method is deficienter, because FPGA is real time execution and limited with the interface channel of host server, so nothing
Method records and stored in real time the value of all internal signals using the verification method of emulation, causes the function that FPGA design is realized to go out
It is difficult now the reason for positioning causes abnormal after exception.
The main of current FPGA debugging plans is problem precisely due to RAM resources are very limited on FPGA piece, generally
RAM resources on FPGA are less than 10MB, and these limited RAM resources will also distribute to objective function and use, debugging system
The RAM resources that can be taken are just less.
Assuming that current debugging system can be assigned to RAM on 5MB FPGA pieces to store the value of debugging signal, generally
The clock frequency run on FPGA is 100MHz or so, it is assumed that the quantity of debugging signal is the 200 (internal bus of 64 bit wides
Number of signals), then the time span for the signal that can be observed=5MB/200b x 10ns=2ms.
It can be seen that, under current debugging technique, the quantity and debugging signal record time span for debugging signal are into anti-
Than.Tuner need to estimate with the quantity of balanced signal and record time span, and can only capture and have in finite time point
Limit the signal of quantity.Choose which signal be observed at which at time point it is just very crucial.But when FPGA target work(
When energy scale is slightly larger or slightly complicated, it is very difficult to the root of problem is diagnosed by the situation of the limit signal in finite time
Source.
Especially when abnormal time span is larger, the setting of trigger timing is very difficult, because current debugging
Technology, time span is generally in the rank of at most several milliseconds of microsecond rank；If the time span of the anomaly run into (is led
The generation of abnormal root-cause event is caused to show the abnormal time to function) and beyond the time span that can be recorded, debugging is just
Can be increasingly difficult.
Another significant shortcoming of current debugging technique is exactly when needing to select and change repeatedly debugging signal and triggering
Machine, and change every time be required for reruning whole FPGA realize flow (compiling, comprehensive, placement-and-routing, generate bit files,
Download in fpga chip), this flow very takes, it usually needs could complete within several hours, this results in debugging
Efficiency is very low.In addition for the more nervous large-scale or complicated FPGA functions of timing Design, change debugging signal
After when rerun FPGA and realize flow, be frequently encountered the unstable situation of timing closure, this is the intractable difficulty of comparison again
With processing.
The content of the invention
The shortcoming of prior art in view of the above, it is an object of the invention to provide FPGA debugging systems and method, greatly
Big increase debugging signal observation interval, solve in the prior art due to debugging signal observation interval it is inadequate caused by
Problems.
In order to achieve the above objects and other related objects, the present invention provides a kind of FPGA debugging systems, and fpga chip is being adjusted
Write-in debugging signal message during examination；The FPGA debugging systems include：The outer memory cell of piece, for receiving and storing from described
The debugging signal message that fpga chip is read；Wherein, the memory capacity of described outer memory cell is more than the FPGA cores
Piece, and its interface bandwidth is not less than the total bandwidth that signal is debugged in the fpga chip.
In one embodiment of the invention, the FPGA includes：HPI and connection institute for connecting a main frame
State the memory interface of the outer memory cell of piece；The memory interface is connected to the HPI so that the main frame reads institute
State the debugging signal message in the outer memory cell of piece.
In one embodiment of the invention, the FPGA includes：HPI for connecting a main frame；Described external memory
Storage unit is located at a main frame, and the main frame receives the debugging signal message by HPI and is stored in storage outside described
Unit.
In one embodiment of the invention, the HPI type includes：Interface bandwidth is not less than the fpga chip
It is middle debugging signal total bandwidth PCI-E interface, USB interface and Ethernet interface in any one..
In one embodiment of the invention, the type of described outer memory cell includes：DDR RAM, solid state hard disc and/or
Hard disk array.
In one embodiment of the invention, including：Main frame, the debugging signal letter is read from described outer memory cell
Breath, and it is organized into the VCD formatted files of IEEE1364 standards.
In order to achieve the above objects and other related objects, the present invention provides a kind of FPGA adjustment methods, and fpga chip is being adjusted
Write-in debugging signal message during examination；Methods described includes：The debugging signal message is read from the fpga chip；It will be read
Debugging signal message be stored in the outer memory cell of piece；Wherein, the memory capacity of described outer memory cell is more than the FPGA
Chip, and its interface bandwidth is not less than the total bandwidth that signal is debugged in the fpga chip.
As described above, FPGA debugging systems provided by the present invention and method, are believed by the debugging signal for writing FPGA
Breath read to capacity is larger and interface bandwidth also memory cell is stored outside enough piece, keeping, debugging number of signals is enough
On the premise of, being substantially improved for signal observation time will be debugged, thus can just avoid existing debud mode inevitably anti-
Select again debugging signal and make repeated attempts trigger timing the problem of, also avoid in order to debug needs be repeated very take
FPGA realize flow, greatly improve FPGA debugging efficiency.And it can solve the problem that existing debugging technique can not diagnose the big time
The abnormal problem of span.
Brief description of the drawings
Fig. 1 is shown as the principle schematic of FPGA debugging system of the present invention in an embodiment.
Fig. 2 is shown as the configuration diagram of FPGA debugging system institute applied environment of the present invention in an embodiment.
Fig. 3 is shown as the configuration diagram of FPGA debugging system institute applied environment of the present invention in another embodiment.
Component label instructions
100 fpga chips
101 outer memory cell
200 fpga chips
210 debugging signal sampling modules
220 memory interfaces
230 HPIs
240 FPGA objective function modules
201 outer memory cell
202 main frames
300 fpga chips
310 debugging signal sampling modules
320 HPIs
330 FPGA objective function modules
301 outer memory cell
302 main frames
Embodiment
Illustrate embodiments of the present invention below by way of specific instantiation, those skilled in the art can be by this specification
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also pass through specific realities different in addition
The mode of applying is embodied or practiced, the various details in this specification can also based on different viewpoints with application, without departing from
Various modifications or alterations are carried out under the spirit of the present invention.It should be noted that, in the case where not conflicting, following examples and implementation
Feature in example can be mutually combined.
It should be noted that the diagram provided in following examples only illustrates the basic structure of the present invention in a schematic way
Think, then in schema only display with relevant component in the present invention rather than according to component count, shape and the size during actual implement
Draw, it is actual when implementing, and kenel, quantity and the ratio of each component can be a kind of random change, and its assembly layout kenel
It is likely more complexity.
Technical scheme, the debugging for fpga chip；So-called FPGA (Field-Programmable Gate
Array), i.e. field programmable gate array, is gone out as a kind of semi-custom circuit in application specific integrated circuit (ASIC) field
Existing, there is inadequate resource based on debugging plan in existing use FPGA pieces and cause to debug signal observation interval in the present invention
Not enough the problem of, has carried out the improvement of technical scheme, well solves problem of the prior art.
Specifically, as shown in figure 1, the present invention provides a kind of FPGA debugging systems, it includes：The outer memory cell 101 of piece, is used
In receiving and storing the debugging signal message from fpga chip reading, the debugging signal message is write in FPGA Debugging chip
Enter, specifically, debugging signal just refers to the signal to be observed when debugging, each debugging signal is in each clock cycle
Debugging signal message can be produced, fpga chip is write and stores.
The improvement principle of the present invention is that the write-in debugging signal message in debugging of fpga chip 100 then assumes FPGA cores
The memory space that piece 100 is used to debug is 5MB, and working frequency is 100Mhz, then it exists in debugging per 10ns clock cycle
Fpga chip 100 writes the debugging signal message of predetermined quantity, if each debugging signal each clock cycle produces 1bit letter
Breath needs are stored, such as 200 debugging signals, and the clock cycle is 10ns, then each clock cycle just produces 200bit
Debugging signal message (number of signals of the internal bus of i.e. one 64 bit wides), then the time span T that can observe is calculated
Mode is：T=A/C × t, A are the capacity of storage debugging signal message, and existing is the 5MB debugging purposes in fpga chip 100
Memory space；C is the i.e. for example described 200bit of quantity of observation signal；T is the cycle, i.e. the inverse of working frequency, i.e. such as institute
State 10ns；And the present invention has changed a kind of thinking, then a piece of outer memory cell 101 is provided, it can be logical with the fpga chip 100
Letter, for storing the debugging signal message, is realized outside debugging signal record storage to FPGA pieces, then just can be from root
The various shortcomings and difficulty caused by RAM deficiencies on FPGA pieces are solved in sheet；Briefly, exactly realizing will store outside piece
The capacity of unit 101 can be regarded as the value for A, and for using memory cell 101 outside such as piece of 16GB capacity, A values can increase from 5MB
16GB is added as, then T is greatly promoted.
Certainly, in order to be able to realize this purpose, the capacity of described outer memory cell 101 needs to be more than the FPGA cores first
Piece 100 is more big then better；Also, the interface bandwidth of described outer memory cell 101 is also at least otherwise less than FPGA internal debuggings
The total bandwidth of signal, is preferably greater than, and more big then better, to improve the quantity of debugging signal message output.For example,
200bit debugging signal message is deposited with each clock cycle 10ns in the above-described embodiments, then all debugging signals are believed
Breath real-time storage bandwidth required if getting up is exactly 200bps/10ns=20Gbps, that is, is required these debugging letters
The bandwidth of the interface of the outer memory cell of piece of number write-in have to be larger than 20Gbps, and otherwise interface just has little time in real time all
Debug in the memory cell outside the piece of signal message transmission, also just do not reach the number for the debugging signal message that predetermined needs are obtained
Amount.
The specific embodiment of two FPGA debugging system structures using the present invention is set forth below：
As shown in Fig. 2 showing one embodiment of the FPGA debugging system structures, described outer memory cell 201 is led to
The debugging signal crossed in the connection fpga chip 200 of memory interface 220, the connection of memory interface 220 fpga chip 200 is adopted
Egf block 210, the debugging signal sampling module 210 is used to read from the FPGA objective functions module 240 in fpga chip 200
Write debugging signal message is taken, specifically, the FPGA objective functions module 240 just refers to need to realize originally on FPGA
Functional module, be also the debugging target of debugging system, all debugging signal messages are all from FPGA objective functions module 240
Middle collection；The fpga chip 200 is also connected to main frame 202 by HPI 230；Wherein, the main frame 202 is, for example,
PC etc., the HPI 230 is, for example, any one in PCI-E interface, USB interface and Ethernet interface, described
Outer memory cell 201 is, for example, DDR RAM etc..
The debugging signal sampling module 210 is to the debugging signal message real-time sampling in FPGA objective functions module 240
Afterwards, write by the IP kernel modules for memory interface 220 (being ddr interface in the present embodiment) to outside fpga chip 200
The outer memory cell 201 of piece in, then main frame 202 is read from DDR RAM by HPI 230 and debugs signal message.
With DDR3 for internal memory for example, its interface bandwidth is 80Gbps, it is assumed that its capacity be 16GB, fpga chip 200
The clock speed of operation is 100MHz, then the bandwidth of each debugging signal in fpga chip 200 is 100Mbps.
Then, the peak signal number that can be observed depends on DDR interface bandwidth：
Peak signal number=80Gbps/100Mbps=800b, that is, 800 signals are observed, much larger than what is assumed before
200 signals；
The time span that can be observed depends on DDR RAM capacity：
Observation maximum time length=16GB/100B × 10ns=1.6s, the signal observation time compared with 2ms before,
1.6s has been promoted to, s rank is risen to from ms.
As shown in figure 3, showing second embodiment of the FPGA debugging system structures, the Main Differences with Fig. 2 embodiments
It is that embodiment is directly to be exported using high speed host computer host interface by signal message is debugged from fpga chip to main frame, to utilize main frame
On the main storage system of high-capacity and high-speed stored；Described outer memory cell 301 is located at a main frame 302, and it can be such as
For the main storage system (such as internal memory, hard disk) of the main frame 302, the debugging signal sampling module 310 of fpga chip 300 is straight
Connect HPI 320 and be connected to the main frame 302；In the present embodiment, the main frame 302 is, for example, PC, the master
Machine interface 320 is, for example, PCI-E interface, and described outer memory cell 301 is, for example, DDR RAM, solid state hard disc (SSD) or hard
Disk array etc..
The debugging signal sampling module 310 by HPI 320 with the direct communication of main frame 302, so that realize will be from
The debugging signal message that FPGA objective functions module 330 is gathered is stored to outside piece in memory cell 301.
To directly it be write by HPI 320 (being PCI-E interface in the present embodiment) after debugging signal message real-time sampling
Enter the main storage system to main frame 302；It is assumed that PCIE interfaces using the third generation × 8 specifications, its interface bandwidth is 8Gbps × 8
=64Gbps.And if the outer SSD or SSD arrays of memory cell 301 of the piece in main frame 302 are realized, its capacity is for debugging
It is unlimited almost to can be considered, it is assumed that be 1TB (8Tb), the clock frequency of FPGA operations is still 100MHz.
Then, the peak signal number that can be observed depends on PCIE interface bandwidth：
Peak signal number=64Gbps/100Mbps=640b, i.e., 640 are observed, also much larger than 200；
The time span that can be observed depends on the capacity of the outer memory cell 301 of piece：
Observe maximum time length=8Tb/640b × 10ns=125s；Hundred s rank has been promoted to from ms.
In one embodiment, if using the interface specification of PCI-E × 16, observation peak signal number can also obtain double
Lifting.
Existing debugging technique is contrasted, it will be seen that the present invention is the DDR RAM's using only current conventional main flow
In the case of, it is possible to will debug signal observation time has thousands of times of lifting, reaches the rank of second, can cover in electronic system
The abnormal time span of the overwhelming majority；It is preferred that, if can provide faster and the outer memory cell of bigger piece so that observation signal number
Amount can reach 1000 or so, and most of exception can be diagnosed by the debugging signal within 1000, so preferred,
In the case where the working frequency of fpga chip is 100MHz, the interface bandwidth of the outer memory cell of piece need to be in more than 100Gbps；Separately
Outside, according to test, it is some it is less demanding in the case of, can should at least keep 200b quantity, then piece outer memory cell
The HPI type that interface bandwidth in more than 20Gbps, need at least meet this requirement is just more；And if using current normal
If the interface of such as PCIE × 8 for advising main flow, 1TB conventional host memory capacity just can will debug the observation time of signal can be with
It is promoted to 125 seconds, it is enough for FPGA debugging.
Still further preferably, in the above-described embodiments, carry out in debugging process, storage medium of the main frame outside FPGA pieces
The middle sample information for reading debugging signal, to be organized into VCD (Value Change Dump) file of IEEE1364 standards, leads to
Conventional artificial debugging instrument reading is crossed to be debugged.
Based on above-mentioned principle, the present invention can also provide a kind of FPGA adjustment methods, and methods described includes：
1) the debugging signal message is read from the fpga chip；
2) the debugging signal message read is stored in memory cell outside piece；Wherein, described outer memory cell is deposited
Store up capacity and be more than the fpga chip, and its interface bandwidth is not less than the total bandwidth that signal is debugged in the fpga chip.
In summary, FPGA debugging systems and method provided by the present invention, are believed by the debugging signal for writing FPGA
Breath read to capacity is larger and interface bandwidth also memory cell is stored outside enough piece, keeping, debugging number of signals is enough
On the premise of, being substantially improved for signal observation time will be debugged, thus can just avoid existing debud mode inevitably anti-
Select again debugging signal and make repeated attempts trigger timing the problem of, also avoid in order to debug needs be repeated very take
FPGA realize flow, greatly improve FPGA debugging efficiency.And it can solve the problem that existing debugging technique can not diagnose the big time
The abnormal problem of span.
The present invention effectively overcomes various shortcoming of the prior art and has high industrial utilization.
The above-described embodiments merely illustrate the principles and effects of the present invention, not for the limitation present invention.It is any ripe
Know the personage of this technology all can carry out modifications and changes under the spirit and scope without prejudice to the present invention to above-described embodiment.Cause
This, those of ordinary skill in the art is complete without departing from disclosed spirit and institute under technological thought such as
Into all equivalent modifications or change, should by the present invention claim be covered.
Claims (7)
1. a kind of FPGA debugging systems, it is characterised in that fpga chip write-in debugging signal message in debugging；The FPGA is adjusted
Test system includes：
The outer memory cell of piece, for receiving and storing the debugging signal message read from the fpga chip；Wherein, it is described
The memory capacity of the outer memory cell of piece is more than the fpga chip, and its interface bandwidth is not less than debugging letter in the fpga chip
Number total bandwidth.
2. FPGA debugging systems according to claim 1, it is characterised in that the FPGA includes：For connecting a main frame
HPI and connect described outer memory cell memory interface；The memory interface is connected to the main frame
Interface reads the debugging signal message in described outer memory cell for the main frame.
3. FPGA debugging systems according to claim 1, it is characterised in that the FPGA includes：For connecting a main frame
HPI；Described outer memory cell is located at a main frame, and the main frame receives the debugging signal by HPI to be believed
Cease and be stored in described outer memory cell.
4. the FPGA debugging systems according to Claims 2 or 3, it is characterised in that the HPI type includes：Interface
Bandwidth is not less than in the fpga chip in PCI-E interface, USB interface and the Ethernet interface of the total bandwidth of debugging signal
Any one.
5. FPGA debugging systems according to claim 1, it is characterised in that the type of described outer memory cell includes：
DDR RAM, solid state hard disc and/or hard disk array.
6. FPGA debugging systems according to claim 1, it is characterised in that including：Main frame, from described outer memory cell
The debugging signal message is read, and is organized into the VCD formatted files of IEEE1364 standards.
7. a kind of FPGA adjustment methods, it is characterised in that fpga chip write-in debugging signal message in debugging；Methods described bag
Include：
The debugging signal message is read from the fpga chip；
The debugging signal message read is stored in memory cell outside piece；Wherein, the memory capacity of described outer memory cell
More than the fpga chip, and its interface bandwidth is not less than the total bandwidth that signal is debugged in the fpga chip.
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