CN106501620A - A kind of serial signal method of testing, oscillograph and system - Google Patents
A kind of serial signal method of testing, oscillograph and system Download PDFInfo
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- CN106501620A CN106501620A CN201610917726.0A CN201610917726A CN106501620A CN 106501620 A CN106501620 A CN 106501620A CN 201610917726 A CN201610917726 A CN 201610917726A CN 106501620 A CN106501620 A CN 106501620A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R29/00—Arrangements for measuring or indicating electric quantities not covered by groups G01R19/00 - G01R27/00
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R13/00—Arrangements for displaying electric variables or waveforms
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Abstract
The invention provides a kind of serial signal method of testing, oscillograph and system, by obtaining the layout of test target, according to the layout, are that the test target determines at least one test point；For test point each described, corresponding test parameter is set；According to the test parameter, the sequentially outfan in each test point is input into the test signal of at least two specifications；In the receiving terminal of each test point, the test signal of specification each described is detected, generate test result.The scheme that the present invention is provided can effectively improve serial signal testing efficiency.
Description
Technical field
The present invention relates to field of computer technology, more particularly to a kind of serial signal method of testing, oscillograph and system.
Background technology
When carrying out data transmission between mainboard and a large amount of storage devices such as hard disk and CD drive etc., often through
SATA bus transfers serial signal is completing.In order to ensure the integrity of data transfer, it is often necessary to the complete of signal transmission
Property is tested.
At present, the mode of the integrity test of signal transmission mainly once can only enter for a kind of signal of specification by test
Row test, when the signal to different size is tested, needs to test each specification successively by ceaselessly transformation parameter
Signal.Existing this test mode, causes the testing efficiency of serial signal relatively low.
Content of the invention
A kind of serial signal method of testing, oscillograph and system is embodiments provided, string can be effectively improved
Row signal testing efficiency.
A kind of serial signal method of testing, including：
The layout of test target is obtained, according to the layout, is that the test target determines at least one test point；
For test point each described, corresponding test parameter is set；
According to the test parameter, the sequentially outfan in each test point is input at least two specifications
Test signal；
In the receiving terminal of each test point, the test signal of specification each described is detected, generate and survey
Test result.
Preferably, said method is further included：For test point each described, corresponding phaselocked loop is set；
The test signal to specification each described detects, generates test result, including：
By the phaselocked loop, the clock signal in the test signal of specification each described is recovered, and is built
Corresponding relation between the clock signal and the signal intensity of test signal, exports the corresponding relation in the form of eye pattern,
By the corresponding relation, determine that eye is high, eye is wide and jitter parameter.
Preferably, described for test point each described, corresponding test parameter is set, including：
On oscillograph, it is that each described test point selectes corresponding phase locked loop type, and is the phase locked loop type
Corresponding bandwidth of phase lock loop and the dough softening are set, and corresponding signal transmission rate is set for each described test point.
Preferably, the test signal of at least two specification, including：
The serial test letter of the serial test signal of 1.5Gbit/s, the serial test signal of 3Gbit/s and 6Gbit/s
Any two or multiple in number.
Preferably, the test point includes：The coupled capacitor end of hard disk；The coupled capacitor end of host chip；Host chip
Via ends.
A kind of oscillograph, including：Test point determining unit, arranging unit and test cell, wherein,
The test point determining unit, for obtaining the layout of external testing target, according to the layout, is described
Outside test target determines at least one test point；
The arranging unit, the test point for determining for test point determining unit each described arrange corresponding survey
Examination parameter；
The test cell, for the test parameter arranged according to the arranging unit, sequentially described described in each
The outfan of the test point that test point determining unit is determined is input into the test signal of at least two specifications, in each survey
The receiving terminal of the test point that pilot determining unit is determined, detects to the test signal of specification each described, generates and surveys
Test result.
Preferably, the test cell, is further used for obtaining the clock signal that outside phaselocked loop is recovered, and builds described
Corresponding relation between clock signal and the signal intensity of test signal, in the form of eye pattern exports the corresponding relation, passes through
The corresponding relation, determines that eye is high, eye is wide and jitter parameter.
Preferably, the arranging unit, for selecting corresponding phase locked loop type for test point each described, and for institute
State phase locked loop type and corresponding bandwidth of phase lock loop and the dough softening are set, and corresponding signal is set for each described test point and pass
Defeated speed.
Preferably, the test signal of at least two specification, including：
The serial test letter of the serial test signal of 1.5Gbit/s, the serial test signal of 3Gbit/s and 6Gbit/s
Any two or multiple in number.
A kind of serial signal test system, including：At least one test target and any of the above-described described oscillograph, its
In,
In at least one test target, each described test target, for providing at least one for the oscillograph
Individual test point.
A kind of serial signal method of testing, oscillograph and system is embodiments provided, by obtaining test target
Layout, according to the layout, be that the test target determines at least one test point；Set for test point each described
Put corresponding test parameter；According to the test parameter, the sequentially outfan in each test point is input at least
The test signal of two kinds of specifications；In the receiving terminal of each test point, the test signal of specification each described is carried out
Detection, generates test result, due to testing to the test signal of different size, therefore, it is possible to effectively improve string
Row signal testing efficiency.
Description of the drawings
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
Accompanying drawing to be used needed for having technology description is briefly described, it should be apparent that, drawings in the following description are the present invention
Some embodiments, for those of ordinary skill in the art, on the premise of not paying creative work, can be with basis
These accompanying drawings obtain other accompanying drawings.
Fig. 1 is a kind of flow chart of serial signal method of testing that one embodiment of the invention is provided；
Fig. 2 is a kind of flow chart of serial signal method of testing that another embodiment of the present invention is provided；
Fig. 3 is the structural representation that the test result that one embodiment of the invention is provided shows；
Fig. 4 is a kind of oscillographic structural representation that one embodiment of the invention is provided；
Fig. 5 is a kind of structural representation of serial signal test system that one embodiment of the invention is provided.
Specific embodiment
Purpose, technical scheme and advantage for making the embodiment of the present invention is clearer, below in conjunction with the embodiment of the present invention
In accompanying drawing, to the embodiment of the present invention in technical scheme be clearly and completely described, it is clear that described embodiment is
The a part of embodiment of the present invention, rather than whole embodiments, based on the present invention in embodiment, those of ordinary skill in the art
The every other embodiment obtained on the premise of creative work is not made, belongs to the scope of protection of the invention.
As shown in figure 1, embodiments providing a kind of serial signal method of testing, the method can include following step
Suddenly：
Step 101：The layout of test target is obtained, according to the layout, is that the test target determines at least one
Individual test point；
Step 102：For test point each described, corresponding test parameter is set；
Step 103：According to the test parameter, sequentially in the outfan input at least two of each test point
Plant the test signal of specification；
Step 104：In the receiving terminal of each test point, the test signal of specification each described is examined
Survey, generate test result.
In the embodiment shown in fig. 1, by the layout of acquisition test target, according to the layout, it is the survey
Examination target determines at least one test point；For test point each described, corresponding test parameter is set；According to the test ginseng
Number, the sequentially outfan in each test point are input into the test signal of at least two specifications；Described in each
The receiving terminal of test point, detects to the test signal of specification each described, generates test result, due to can be to difference
The test signal of specification is tested, therefore, it is possible to effectively improve serial signal testing efficiency.
In an embodiment of the invention, in order that test result is more directly perceived, said method is further included：For described
Each test point arranges corresponding phaselocked loop；The test signal to specification each described detects, generates and test
As a result, including：By the phaselocked loop, the clock signal in the test signal of specification each described is recovered, and structure
The corresponding relation that builds between the clock signal and the signal intensity of test signal, exports the corresponding pass in the form of eye pattern
System, by the corresponding relation, determines that eye is high, eye is wide and jitter parameter.I.e. by recovering clock signal, in the form of eye pattern
Show test result.
In an embodiment of the invention, in order to realize testing, described for the corresponding survey of test point setting each described
Examination parameter, including：On oscillograph, it is that each described test point selectes corresponding phase locked loop type, and is the phaselocked loop
Type arranges corresponding bandwidth of phase lock loop and the dough softening, and arranges corresponding signal transmission rate for each described test point.
In an embodiment of the invention, the test signal of at least two specification, including：The serial of 1.5Gbit/s
Any two or multiple in the serial test signal of test signal, the serial test signal of 3Gbit/s and 6Gbit/s.
In an embodiment of the invention, the test point includes：The coupled capacitor end of hard disk；The coupling electricity of host chip
Rong Duan；The Via ends of host chip.
As shown in Fig. 2 another embodiment of the present invention provides a kind of serial signal method of testing, the method can include as follows
Step：
Step 201：The layout of test target is obtained, according to the layout, is that the test target determines at least one
Individual test point；
The test point includes：The coupled capacitor end of hard disk；The coupled capacitor end of host chip；The Via ends of host chip.
Step 202：For each test point, corresponding phaselocked loop is set；
As SATA serial signal transfers use embedded clock signal, possess higher error correcting capability, then, pass through
Clock signal can be converted by the phaselocked loop that the step is arranged, to provide time reference as follow-up test.
Step 203：For each test point, corresponding test parameter is set；
On oscillograph, it is that each described test point selectes corresponding phase locked loop type, and is the phase locked loop type
Corresponding bandwidth of phase lock loop and the dough softening (damping) are set, and corresponding signal transmission is set for each described test point
Speed such as 1.5Gbit/s, 3Gbit/s or 6Gbit/s.
Step 204：According to the test parameter, sequentially in the outfan input at least two of each test point
Plant the test signal of specification；
The specification of the step test signal is mainly divided according to signal transmission rate, then, the step is referred to
The test signal of at least two specifications can include：The serial test signal of 1.5Gbit/s, the serial test signal of 3Gbit/s
And any two in the serial test signal of 6Gbit/s or multiple.
Step 205：In the receiving terminal of each test point, the test signal of specification each described is examined
Survey；
The process of test is mainly, and test signal is sent to receiving terminal test signal by outfan by oscillograph, and
The test signal that receiving terminal detection receiving terminal is received.Such as：When test is written and read to hard disk, then by being connected with hard disk
Chip outfan output test signal, and the receiving terminal in hard disk reads the test signal, determines the test for reading
The intensity of signal.
Step 206：By the phaselocked loop, the clock signal in the test signal of specification each described is carried out extensive
Multiple；
Step 207：The corresponding relation between the clock signal and the signal intensity of test signal is built, with the shape of eye pattern
Formula exports the corresponding relation；
As shown in figure 3, test result can be observed from eye pattern intuitively from figure.So, in order that the displaying of eye pattern
Effect is relatively good, can obtain different eye patterns by changing bandwidth of phase lock loop, to select bandwagon effect from different eye patterns
Best eye pattern is used as test result.
Step 208：By the corresponding relation, determine that eye is high, eye is wide and jitter parameter.
As shown in figure 4, the embodiment of the present invention provides a kind of oscillograph, including：Test point determining unit 401, arranging unit
402 and test cell 403, wherein,
The test point determining unit 401, for obtaining the layout of external testing target, according to the layout, be
The test target of the outside determines at least one test point；
The arranging unit 402, it is right that the test point for determining for test point determining unit 401 each described is arranged
The test parameter that answers；
The test cell 403, for the test parameter arranged according to the arranging unit 402, sequentially described each
The outfan of the test point that the individual test point determining unit is determined is input into the test signal of at least two specifications, at each
The receiving terminal of the test point that the test point determining unit is determined, detects to the test signal of specification each described,
Generate test result.
In an alternative embodiment of the invention, the test cell 403, is further used for obtaining what outside phaselocked loop was recovered
Clock signal, builds the corresponding relation between the clock signal and the signal intensity of test signal, is exported in the form of eye pattern
The corresponding relation, by the corresponding relation, determines that eye is high, eye is wide and jitter parameter.
In still another embodiment of the process, the arranging unit 402, corresponding for selecting for test point each described
Phase locked loop type, and corresponding bandwidth of phase lock loop and the dough softening are set for the phase locked loop type, and be each described test
Point arranges corresponding signal transmission rate.
In an alternative embodiment of the invention, the test signal of at least two specification, including：
The serial test letter of the serial test signal of 1.5Gbit/s, the serial test signal of 3Gbit/s and 6Gbit/s
Any two or multiple in number.
As shown in figure 5, the embodiment of the present invention provides a kind of serial signal test system, including：At least one test target
501 and any of the above-described described oscillograph 502, wherein,
In at least one test target 501, each described test target 501, for providing for the oscillograph
At least one test point.
In an embodiment of the invention, above-mentioned serial signal test system, further includes：
Phaselocked loop, is connected with test target, is carried out for the clock signal in the test signal to specification each described
Recover.
Present invention also offers a kind of computer-readable storage medium, store for making a machine execute program as described herein
The instruction of the checking method of code.Specifically, it is provided that be furnished with system or the device of storage medium, on the storage medium
The software program code for realizing the function of any embodiment in above-described embodiment is store, and makes the calculating of the system or device
Machine (or CPU or MPU) reads and executes the program code that is stored in storage medium.
In this case, the program code itself for reading from storage medium can achieve any one reality in above-described embodiment
The function of example is applied, therefore the storage medium of program code and store program codes constitutes the part of the present invention.
For provide the storage medium embodiment of program code include floppy disk, hard disk, magneto-optic disk, CD (as CD-ROM,
CD-R, CD-RW, DVD-ROM, DVD-RAM, DVD-RW, DVD+RW), tape, Nonvolatile memory card and ROM.Selectively,
Can by communication network from server computer download program code.
Further, it should be apparent that, not only by the program code executed read-out by computer, and can pass through
Operating system of calculating hands- operation etc. is made based on the instruction of program code to complete partly or completely practical operation, so as to
Realize the function of any one embodiment in above-described embodiment.
Further, it is to be appreciated that the program code read by storage medium is write the expansion board in insertion computer
In in set memorizer or write in the memorizer arranged in the expanding element being connected with computer, be subsequently based on journey
The instruction of sequence code makes CPU in expansion board or expanding element etc. come executable portion and whole practical operations, so as to
Realize the function of any embodiment in above-described embodiment.
In an embodiment of the invention, above-mentioned test target can be hard disk or each chip on mainboard.
According to such scheme, various embodiments of the present invention, at least have the advantages that：
1., by the layout of acquisition test target, according to the layout, it is that the test target determines at least one
Test point；For test point each described, corresponding test parameter is set；According to the test parameter, sequentially described each
The outfan of the test point is input into the test signal of at least two specifications；In the receiving terminal of each test point, to every
A kind of test signal of the specification is detected that generation test result, due to carrying out to the test signal of different size
Test, therefore, it is possible to effectively improve serial signal testing efficiency.
It should be noted that herein, such as first and second etc relational terms are used merely to an entity
Or operation is made a distinction with another entity or operation, and not necessarily require or imply presence between these entities or operation
Any this actual relation or order.And, term " including ", "comprising" or its any other variant are intended to non-
Exclusiveness includes, so that a series of process, method, article or equipment including key elements not only include those key elements,
But also other key elements including being not expressly set out, or also include solid by this process, method, article or equipment
Some key elements.In the absence of more restrictions, the key element for being limited by sentence " including ", does not arrange
Remove and also there is other same factor in process, method, article or the equipment for including the key element.
One of ordinary skill in the art will appreciate that：Realize that all or part of step of said method embodiment can pass through
Completing, aforesaid program can be stored in the storage medium of embodied on computer readable the related hardware of programmed instruction, the program
Upon execution, the step of including said method embodiment is executed；And aforesaid storage medium includes：ROM, RAM, magnetic disc or light
Disk etc. is various can be with the medium of store program codes in.
Last it should be noted that：Presently preferred embodiments of the present invention is the foregoing is only, the skill of the present invention is merely to illustrate
Art scheme, is not intended to limit protection scope of the present invention.All any modifications that is made within the spirit and principles in the present invention,
Equivalent, improvement etc., are all contained in protection scope of the present invention.
Claims (10)
1. a kind of serial signal method of testing, it is characterised in that include：
The layout of test target is obtained, according to the layout, is that the test target determines at least one test point；
For test point each described, corresponding test parameter is set；
According to the test parameter, the sequentially outfan in each test point is input into the test of at least two specifications
Signal；
In the receiving terminal of each test point, the test signal of specification each described is detected, generate test knot
Really.
2. method according to claim 1, it is characterised in that further include：It is right to arrange for test point each described
The phaselocked loop that answers；
The test signal to specification each described detects, generates test result, including：
By the phaselocked loop, the clock signal in the test signal of specification each described is recovered, and build described
Corresponding relation between clock signal and the signal intensity of test signal, in the form of eye pattern exports the corresponding relation, passes through
The corresponding relation, determines that eye is high, eye is wide and jitter parameter.
3. method according to claim 1 and 2, it is characterised in that described arrange for test point each described corresponding
Test parameter, including：
On oscillograph, it is that each described test point selectes corresponding phase locked loop type, and arranges for the phase locked loop type
Corresponding bandwidth of phase lock loop and the dough softening, and corresponding signal transmission rate is set for each described test point.
4. method according to claim 1, it is characterised in that the test signal of at least two specification, including：
In the serial test signal of the serial test signal of 1.5Gbit/s, the serial test signal of 3Gbit/s and 6Gbit/s
Any two or multiple.
5. according to the arbitrary described method of Claims 1-4, it is characterised in that
The test point includes：The coupled capacitor end of hard disk；The coupled capacitor end of host chip；The Via ends of host chip.
6. a kind of oscillograph, it is characterised in that include：Test point determining unit, arranging unit and test cell, wherein,
The test point determining unit, for obtaining the layout of external testing target, according to the layout, is the outside
Test target determine at least one test point；
The arranging unit, the test point for determining for test point determining unit each described arrange corresponding test ginseng
Number；
The test cell, for the test parameter arranged according to the arranging unit, sequentially in each described test described
The outfan of the test point that point determining unit is determined is input into the test signal of at least two specifications, in each test point
The receiving terminal of the test point that determining unit is determined, detects to the test signal of specification each described, generates test knot
Really.
7. oscillograph according to claim 6, it is characterised in that
The test cell, is further used for obtaining the clock signal that outside phaselocked loop is recovered, build the clock signal with
Corresponding relation between the signal intensity of test signal, exports the corresponding relation, in the form of eye pattern by the corresponding pass
System, determines that eye is high, eye is wide and jitter parameter.
8. oscillograph according to claim 6, it is characterised in that
The arranging unit, for selecting corresponding phase locked loop type for test point each described, and is the phaselocked loop class
Type arranges corresponding bandwidth of phase lock loop and the dough softening, and arranges corresponding signal transmission rate for each described test point.
9. oscillograph according to claim 6, it is characterised in that the test signal of at least two specification, including：
In the serial test signal of the serial test signal of 1.5Gbit/s, the serial test signal of 3Gbit/s and 6Gbit/s
Any two or multiple.
10. a kind of serial signal test system, it is characterised in that include：At least one test target and claim 6 to 9 times
Oscillograph described in one, wherein,
In at least one test target, each described test target, for providing at least one survey for the oscillograph
Pilot.
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| CN111897303A (en) * | 2019-05-06 | 2020-11-06 | 深圳市优必选科技有限公司 | Eye pattern test method and eye pattern test system |
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