CN106484549B

CN106484549B - A kind of exchange method, NVMe equipment, HOST and physical machine system

Info

Publication number: CN106484549B
Application number: CN201510547074.1A
Authority: CN
Inventors: 种锋生; 张羽; 俞柏峰
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2015-08-31
Filing date: 2015-08-31
Publication date: 2019-05-10
Anticipated expiration: 2035-08-31
Also published as: CN106484549A

Abstract

The present invention provides a kind of exchange method, NVMe equipment, HOST and physical machine system, it is related to field of computer technology, for realizing the hot plug of NVMe equipment, under the premise of guaranteeing that the side HOST is normally interacted with NVMe equipment, the system as caused by SDI card (NVMe equipment) system reset can be effectively avoided to hang dead.It include: that assignment instructions are written in the first queue in the HOST memory host HOST, the assignment instructions indicate NVMe equipment by the operation of execution；NVMe equipment is the peripheral equipment interacted with HOST by PCIe bus；Triggering is identified the second queue in write-in HOST memory by HOST；Triggering mark represents HOST and has confirmed that and will interact with NVMe equipment, and interaction is the interaction that NVMe equipment executes that operation needs to carry out with HOST；HOST confirmation operation is completed, then will complete to identify write-in first queue, completion mark represents HOST and has confirmed that interaction is completed.

Description

A kind of exchange method, NVMe equipment, HOST and physical machine system

Technical field

The present invention relates to field of computer technology more particularly to a kind of exchange method and NVMe (Non Volatile Memory express, non-volatile memory express passway) equipment, HOST (host) and physical machine system.

Background technique

In general, the software operated on physical machine CPU (Central Processing Unit, processor) can divide For the business software of system software and user.As shown in Figure 1, being existing SDI (Service Driven Lnfrastructure, business drive architecture) framework, i.e., the system software being deployed on processor originally is unloaded to On independent SDI card, the business software of user is only run on CPU.In this way, system has just been divided into the side HOST, NVMe equipment side Two parts pass through therebetween PCIe (Peripheral Component Interconnect express, quick outer set Part interconnection) bus communicated.

SDI card is rendered as NVMe equipment to CPU (side HOST), is led to by PCIe bus and standard NVMe agreement Letter.During NVMe equipment (such as: SDI card) and the side HOST carry out communication interaction, it is successively right twice that the CPU of the side HOST needs The register of NVMe equipment carries out write operation (i.e. progress doorbell operation), rewrites certain field in the register of NVMe equipment, makes It obtains NVMe to know and will interact with HOST, to guarantee that interaction is normally carried out.

In general, SDI card is a separate hardware card being inserted on Servers standard PCIe slot position, there is bearing system software on card And firmware, these softwares and firmware are to be upgraded in use.Under normal circumstances, the upgrading of software and firmware It requires just come into force SDI card system reset.SDI card system reset is equal to NVMe equipment quilt suddenly for the side HOST It pulls out.If when the register of the CPU operation SDI card of the side HOST, SDI card system reset causes the read/write of CPU to be asked It acquires less than response, CPU just will mistakenly believe that unit exception, and quoting MCE, (Machine Check Exception, machine check are wrong Whole system accidentally) is allowed to be hung dead.

Summary of the invention

The embodiment of the present invention provides a kind of exchange method, NVMe equipment, HOST and physical machine system, guarantee the side HOST with Under the premise of NVMe equipment normally interacts, the system as caused by SDI card (NVMe equipment) system reset can effectively be avoided to hang Extremely, the hot plug of NVMe equipment is realized.

The embodiment of the present invention adopts the following technical scheme that

In a first aspect, disclosing a kind of exchange method, comprising:

Assignment instructions are written in the first queue in the HOST memory host HOST, and the assignment instructions instruction is non-easily Storage express passway NVMe equipment is lost by the operation of execution；The NVMe equipment is mutual by quick external module with the HOST The peripheral equipment that connection PCIe bus interacts；

The second queue in the HOST memory is written in triggering mark by the HOST；Described in the triggering mark represents HOST, which has confirmed that, to be interacted with the NVMe equipment, and the interaction executes the operation needs and institute for the NVMe equipment State the interaction of HOST progress；

The HOST confirmation operation is completed, then will complete mark and the first queue, the completion mark is written It represents the HOST and has confirmed that the interaction is completed.

With reference to first aspect, in the first possible implementation of the first aspect, the HOST confirms the operation It is completed and includes:

The HOST receives the default interruption that the NVMe equipment is sent, and accesses the third queue in the HOST memory, It detects that mark is completed in operation, then confirms that the operation is completed；

Wherein, the default interruption is used to indicate the HOST and accesses the third queue, and the operation is completed mark and referred to Show that the operation is completed.

Second aspect discloses a kind of exchange method, comprising:

Non-volatile memory express passway NVMe device polling first queue；The first queue is stored in the interior of host HOST In depositing；

The NVMe equipment detects that triggering mark, the triggering mark have represented the HOST in the first queue Confirmation will be interacted with the NVMe equipment；The interaction is that the NVMe equipment executes operation needs and the HOST is carried out Interaction；

The NVMe equipment obtains assignment instructions；The assignment instructions indicate the NVMe equipment by the behaviour of execution Make；

The NVMe equipment executes the operation；

The NVMe equipment detects completion mark in the first queue；The completion mark has indicated the HOST Confirm that the interaction is completed, the completion mark is that the HOST confirms that the operation completes that the first queue is written later 's.

In conjunction with second aspect, in the first possible implementation of the second aspect, the NVMe equipment obtains task Instruction includes:

The NVMe equipment accesses the second queue in the HOST memory, and the task is obtained in the second queue Instruction.

In conjunction with the possible implementation of the first of second aspect or second aspect, second in second aspect is possible In implementation, if the operation is writes data, the NVMe equipment executes the operation and specifically includes:

The NVMe equipment obtains data to be written in the register of the HOST, and the data to be written are stored in institute In the local memory for stating NVMe equipment；

The third queue that mark is written in the HOST is completed in operation by the NVMe equipment；The operation is completed mark and is referred to Show that the operation is completed；

The NVMe equipment sends default interruption to the HOST, indicates that the HOST accesses the third queue, really Recognize the operation to be completed.

In conjunction with the possible implementation of the first of second aspect or second aspect, the third in second aspect is possible In implementation, if the operation is reads data, the NVMe equipment executes the operation and specifically includes:

The NVMe equipment receives the read data request of the HOST, and the data that continue are sent to the HOST；

The NVMe equipment receives the HOST is sent first and interrupts, and mark is completed in operation and is written in the HOST Third queue；The operation is completed the mark instruction operation and is completed, and first interruption is used to indicate the NVMe equipment The third queue that mark is written in the HOST memory is completed into the operation；

The NVMe equipment sends default interruption to the HOST, indicates that the HOST accesses the third queue, confirmation The operation is completed.

In conjunction with second aspect, in the fourth possible implementation of the second aspect, the NVMe device polling first Queue includes:

First queue described in the NVMe equipment active poll；

Or, the NVMe equipment receives first queue described in poll after the instruction information that the HOST is sent.

The third aspect discloses a kind of host HOST, comprising:

Writing unit, for assignment instructions to be written in the first queue in the HOST memory, the assignment instructions refer to Show non-volatile memory express passway NVMe equipment by the operation of execution；The NVMe equipment is to pass through quickly outside with the HOST The peripheral equipment that component interconnection PCIe bus interacts；

Said write unit is also used to, and triggering mark is written to the second queue in the HOST memory；The triggering mark Knowledge represents the HOST and has confirmed that and will interact with non-volatile memory express passway NVMe equipment, and the interaction is the NVMe Equipment executes the interaction that the operation needs to carry out with the HOST；

Confirmation unit, for confirming that the operation is completed；

Said write unit is also used to, and when the confirmation unit confirmation operation is completed, will complete mark write-in The first queue, the completion mark represent the HOST and have confirmed that the interaction is completed.

In conjunction with the third aspect, in the first possible implementation of the third aspect, the confirmation unit is specifically used for,

Fourth aspect discloses a kind of non-volatile memory express passway NVMe equipment, comprising:

Detection unit is used for poll first queue；The first queue is stored in the memory of host HOST；

The detection unit is also used to, and detects that triggering mark, the triggering mark represent institute in the first queue It states HOST and has confirmed that and will be interacted with the NVMe equipment；The interaction be the NVMe equipment execute operation need with it is described The interaction that HOST is carried out；

Acquiring unit, for obtaining assignment instructions；The assignment instructions indicate the operation of the HOST by execution；

Execution unit, for executing the operation；

The detection unit is also used to, and completion mark is detected in the first queue；The completion mark instruction institute It states HOST and has confirmed that and be completed with the interaction, the completion mark is that the HOST confirms write-in institute after the operation is completed State first queue.

In conjunction with fourth aspect, in the first possible implementation of the fourth aspect, the acquiring unit is specifically used for: The second queue in the HOST memory is accessed, the assignment instructions are obtained in the second queue.

In conjunction with the possible implementation of the first of fourth aspect or fourth aspect, second in fourth aspect is possible In implementation, if operation is writes data, the execution unit is specifically used for:

Data to be written are obtained in the register of the HOST, and the data to be written are stored in the NVMe equipment In local memory；

The third queue that mark is written in the HOST is completed into operation；The operation has completed the mark instruction operation It completes；

Default interruption is sent to the HOST, indicates that the HOST accesses the third queue, has confirmed the operation It completes.

In conjunction with the possible implementation of the first of fourth aspect or fourth aspect, the third in fourth aspect is possible In implementation, if operation is reads data, the execution unit is specifically used for:

The read data request of the HOST is received, and the data that continue are sent to the HOST；

It receives the HOST is sent first to interrupt, the third queue that mark is written in the HOST is completed into operation；Institute It states to operate to complete to identify and indicates that the operation is completed, first interruption is used to indicate the NVMe equipment and has operated described The third queue in the HOST memory is written at mark；

Default interruption is sent to the HOST, indicates that the HOST accesses the third queue, confirms that the operation is complete At.

In conjunction with fourth aspect, in the fourth possible implementation of the fourth aspect, the detection unit is specifically used for, First queue described in equipment active poll；

Or, receiving first queue described in poll after the instruction information that the HOST is sent.

5th aspect, discloses a kind of physical machine system, including host HOST and non-volatile memory express passway NVMe are set It is standby,

Assignment instructions are written in the first queue in the HOST memory HOST, and the assignment instructions instruction is non-easily Storage express passway NVMe equipment is lost by the operation of execution；The NVMe equipment is mutual by quick external module with the HOST The peripheral equipment that connection PCIe bus interacts；

Second queue described in the NVMe device polling；

The NVMe equipment detects triggering mark in the second queue；

The NVMe equipment obtains assignment instructions in the first queue；

The NVMe equipment executes the operation；

The HOST obtains the operation and completes mark, confirms that the operation is completed, then will complete described in mark write-in Second queue；The operation is completed the mark instruction operation and is completed；The completion mark represents the HOST and has confirmed that institute Interaction is stated to be completed；

The NVMe equipment detects completion mark in the second queue.

Exchange method, NVMe equipment, HOST and physical machine system provided in an embodiment of the present invention, the NVMe equipment is in master Triggering command is polled in first queue in the memory of machine HOST；The triggering command indicate the HOST have confirmed that by with institute NVMe equipment is stated to interact.The NVMe equipment obtains assignment instructions, executes the operation of the assignment instructions instruction.NVMe is set It is standby that completion instruction is detected in the first queue in the memory of the HOST；The completion instruction indicates that the HOST has confirmed that Interaction is completed with the NVMe equipment.In this way, avoiding the CPU of HOST direct during HOST is interacted with NVMe equipment The register for operating NVMe equipment, so that the CPU of HOST be avoided to cause system to be hung without response NVMe equipment side register manipulation Dead situation occurs.The CPU operation register of HOST will not be caused without response NVMe equipment occur and being unplugged suddenly Situation, it is that primary read-write time-out is realized so that it is dead effectively to avoid system caused by NVMe device reset from hanging that system, which only will be considered that, The hot plug of NVMe equipment.

Detailed description of the invention

In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this Some embodiments of invention for those of ordinary skill in the art without creative efforts, can be with It obtains other drawings based on these drawings.

Fig. 1 is the schematic diagram of existing SDI framework；

Fig. 2 is the flow diagram for the exchange method that the embodiment of the present invention 1 provides；

Fig. 3 is the flow diagram for the exchange method that the embodiment of the present invention 2 provides；

Fig. 4 is the flow diagram for the exchange method that the embodiment of the present invention 3 provides；

Fig. 5 is the flow diagram for writing data that the embodiment of the present invention 4 provides；

Fig. 6 is the flow diagram for the reading data that the embodiment of the present invention 5 provides；

Fig. 7 is the structural block diagram for the HOST that the embodiment of the present invention 6 provides；

Fig. 8 is the structural block diagram for the NVMe equipment that the embodiment of the present invention 7 provides；

Fig. 9 is the structural block diagram for the HOST that the embodiment of the present invention 8 provides；

Figure 10 is the structural block diagram for the NVMe equipment that the embodiment of the present invention 9 provides；

Figure 11 is the architecture diagram for the physical machine system that the embodiment of the present invention 10 provides.

Specific embodiment

Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other Embodiment shall fall within the protection scope of the present invention.

Originally the system software being deployed on processor is unloaded on independent SDI card, CPU by so-called SDI framework On only run the business software of user.In this way, system has just been divided into two parts.As shown in Figure 1, part A is known as HOST (master Machine) side, part B be known as NVMe equipment side.It is often necessary to which SDI card system reset could be made have bearing system software on card Normally upgrade with firmware.When SDI card does system reset movement, NVMe equipment is equal to for CPU and is unplugged suddenly.

In existing standard, NVMe equipment is specifically included with the side HOST interaction flow:

(1) CPU (CPU of the side HOST) writes command to SQ (Submission Queue submits queue), i.e., hands over this In the order write-in SQ mutually executed；

(2) Doorbell (doorbell) register of CPU write NVMe equipment, this is CPU to the direct of NVMe device register Operation, the side HOST inform that NVMe equipment will carry out the interaction between the two；

(3) NVMe equipment reads the order in step (1) write-in from SQ queue；

(4) NVMe equipment executes the order；

(5) NVMe equipment will complete data write-in CQ (Completion Queue completes queue) instruction and step is completed (1) order being written, and discharge SQ；

(6) NVMe Contreller sends MSI-X and interrupts to CPU, indicates that CPU executes CQ；

(7) CPU executes CQ after receiving interruption；

(8) the Doorbell register of CPU write NVMe equipment, this is direct operation of the HOST to NVMe device register. Subsequent NVMe equipment discharges CQ queue.Primary complete NVMe protocol interaction is completed.

In above-mentioned process, (2) a step and (8) step are direct operation of the HOST to NVMe device register, remaining Step is all the side HOST to the read-write of our memory, the behavior of equipment side.In step (2), (8), if NVMe equipment is unexpected It is pulled out (such as: SDI card is resetted), the read/write requests that at this moment side HOST CPU is initiated cannot respond, and HOST just will be considered that Unit exception quotes MCE mistake and whole system is allowed to hang extremely.

So-called hot plug (hot-plugging or Hot Swap), that is, plug, and is exactly that user is not closing system, no It is taken out in the case where cutting off the power and replaces the components such as hard disk, power supply or the board damaged, while not influencing the normal fortune of system Row.The present invention is intended to provide a kind of hot plug implementation method of NVMe equipment, so that extracting in NVMe equipment, (such as: SDI card, which is done, is System resets) when, the normal operation of system is not influenced.

In addition, doing queue of the present invention to illustrate.Queue is one of frequently-used data structure, is a kind of special Linear list, it only allows to carry out delete operation in the front end (frent) of table, and carries out insertion behaviour at the rear end of table (rear) Make.Wherein, the end for carrying out insertion operation is known as tail of the queue, and the end for carrying out delete operation is known as team's head.

Embodiment 1:

The embodiment of the present invention provides a kind of exchange method, as shown in Fig. 2, the described method comprises the following steps:

101, assignment instructions are written in the first queue in the HOST memory HOST, and the assignment instructions indicate NVMe Equipment is by the operation of execution；The NVMe equipment is to be interacted with the HOST by quick Peripheral Component Interconnect PCIe bus Peripheral equipment.

Wherein, the operation can be the NVMe equipment and read data in the memory of the HOST, alternatively, being institute It states NVMe equipment and receives the request that HOST reads data, response data is sent to HOST.Queue is a kind of data structure, for depositing Store up data.

102, the second queue in the HOST memory is written in triggering mark by the HOST；The triggering mark represents institute State HOST and have confirmed that and will be interacted with the NVMe equipment, the interaction be the NVMe equipment execute the operation need and The interaction that the HOST is carried out.

Wherein, so-called interaction, which participates in movable object, mutually to exchange, and interact on both side.In embodiments of the present invention It refers in particular to: when HOST instruction NVMe equipment will execute certain operation, before NVMe equipment executes operation, after completing operation, NVMe What is carried out between equipment and HOST exchanges, to ensure that NVMe equipment and HOST know each step process carried out.It is exemplary, when HOST instruction NVMe equipment writes data, it is also necessary to write-in triggering mark, so that NVMe equipment knows after detecting triggering mark HOST has been acknowledged that the NVMe equipment will write data from the memory of HOST.For another example: when NVMe equipment executes data writing operation When, it is not merely to obtain data in the memory of HOST, it is also necessary to which write operation completion is identified to HOST's after completing to write data Memory, so that HOST, which knows that NVMe equipment is completed, writes data.

In addition, the triggering command can be an address bit in the first queue, being used to indicate the HOST is No have confirmed that will interact with the NVMe equipment.It is exemplary, address bit be " 0 " represent the HOST it is unconfirmed will with it is described NVMe equipment interacts, and address bit represents the HOST for " 1 " and has confirmed that and will interact with the NVMe equipment.

103, the HOST confirmation operation is completed, then will complete mark and the first queue, the completion is written Mark represents the HOST and has confirmed that the interaction is completed.

It should be noted that the same with triggering mark, the completion, which identifies, to be also possible in the first queue One address bit, is used to indicate whether the HOST has confirmed that the interaction is completed.

In the specific implementation, the HOST confirmation operation is completed and includes:

It should be noted that the default interruption can be MSI (Message Signaled Interrupt, message letter Breath interrupts)-X.In addition, in the present embodiment, the first queue can be SQ (Submit Queue submits queue), described Second queue can be DQ (Doorbell Queue, doorbell queue), and the third queue can be CQ (Complete Queue completes queue).

In existing NVMe equipment and HOST interactive process, HOST is by referring to HOST to the Doorbell operation of NVMe equipment The register of NVMe equipment is directly write, modifies certain field to inform that NVMe equipment needs to interact with HOST, in this process In, if NVMe device systems reset, the write request that will lead to HOST cannot be responded, and system quotes MCE, and then system quilt It hangs up.In the present invention, it is revised as Doorbell operation to go to the register memory repeating query first team of HOST by NVMe device drives Column, to determine whether to interact with HOST.It not only ensure that is interacted between NVMe equipment and HOST was normally carried out in this way, but also System caused by resetting due to NVMe device systems is avoided to hang extremely.

Exchange method provided in an embodiment of the present invention, the NVMe equipment is in the first queue in the memory of host HOST It is polled to triggering command；The triggering command indicates that the HOST has confirmed that and will interact with the NVMe equipment.It is described NVMe equipment obtains assignment instructions, executes the operation of the assignment instructions instruction.NVMe equipment is in the memory of the HOST Completion instruction is detected in first queue；The completion instruction indicates that the HOST has confirmed that and completes friendship with the NVMe equipment Mutually.In this way, avoid the CPU of HOST from directly operating the register of NVMe equipment during HOST is interacted with NVMe equipment, from And it avoids the CPU of HOST from causing system to hang dead situation without response NVMe equipment side register manipulation and occurs.Even if occurring NVMe equipment is unplugged suddenly will not lead to the case where CPU operation register of HOST is without response, and it is one that system, which only will be considered that, Secondary read-write time-out realizes the hot plug of NVMe equipment so that it is dead effectively to avoid system caused by NVMe device reset from hanging.

Embodiment 2:

The embodiment of the present invention provides a kind of exchange method, as shown in figure 3, the described method comprises the following steps:

201, NVMe device polling first queue；The first queue is stored in the memory of host HOST.

So-called poll refers to that NVMe equipment goes monitoring or constantly goes to read the first queue in HOST memory, until Read the triggering command (such as: the numerical value of particular address position changes: becoming " 1 "), then it is assumed that NVMe equipment will with it is described HOST is interacted.

202, the NVMe equipment detects triggering mark in the first queue, and the triggering identifies described in representative HOST, which has confirmed that, to be interacted with the NVMe equipment；The interaction be the NVMe equipment execute operation need with it is described The interaction that HOST is carried out.

Wherein, the triggering command can be an address bit in the first queue, and being used to indicate the HOST is No have confirmed that will interact with the NVMe equipment.It is exemplary, address bit be " 0 " represent the HOST it is unconfirmed will with it is described NVMe equipment interacts, and address bit represents the HOST for " 1 " and has confirmed that and will interact with the NVMe equipment.

In addition, the operation, can be the NVMe equipment and reads data in the memory of the HOST, alternatively, being institute It states NVMe equipment and receives the request that HOST reads data, response data is sent to HOST.Queue is a kind of data structure, for depositing Store up data.

So-called interaction refers to HOST instruction NVMe equipment when executing certain operation, before NVMe equipment executes operation, complete After operation, the interaction to be carried out between NVMe equipment and HOST, to ensure that NVMe equipment and HOST know a certain step carried out Process.Such as: assignment instructions are written in HOST in a step 101, and instruction NVMe equipment is write data, identify later in write-in triggering, So that NVMe equipment knows that HOST has been acknowledged that the NVMe equipment will write number from the memory of HOST after detecting triggering mark According to.

203, the NVMe equipment obtains assignment instructions；The assignment instructions indicate that the NVMe equipment will be described in execution Operation.

Specifically, the NVMe equipment accesses the second queue in the HOST memory, obtains in the second queue The assignment instructions.

204, the NVMe equipment executes the operation.

It specifically can be, the NVMe equipment reads data in the memory of the HOST, alternatively, being the NVMe equipment The request that HOST reads data is received, response data is sent to HOST.

205, the NVMe equipment detects completion mark in the first queue；Described in the completion mark instruction HOST has confirmed that the interaction is completed, and completion mark is that the HOST confirms that the operation completes to be written described the later One queue.

With triggering mark, the address bit completing mark and being also possible in the first queue is used Whether have confirmed that the interaction is completed in the instruction HOST.

In existing NVMe equipment and HOST interactive process, HOST is by referring to HOST to the Doorbell operation of NVMe equipment The register of NVMe equipment is directly write, modifies certain field to inform that NVMe equipment needs to interact with HOST, in this process In, if NVMe device systems reset, the write request that will lead to HOST cannot be responded, and system quotes MCE, and then system quilt It hangs up.In the present invention, it is revised as Doorbell operation to go to the register memory repeating query first team of HOST by NVMe device drives Column, will be interacted with determining whether HOST has confirmed that.The register of NVMe equipment is carried out writing behaviour in this way, HOST is not spent Make, so that it may avoid since NVMe equipment extracts the extension of system caused by (i.e. SDI card system reset) extremely suddenly.In addition, informing NVMe equipment will be interacted with HOST, and interaction not can be carried out NVMe equipment and extract (i.e. SDI card system reset) before completing.

The NVMe equipment executes the operation, can specifically include following two situation:

If first, the described operation is writes data, the NVMe equipment executes the operation and specifically includes:

The NVMe equipment obtains data to be written in the register of the HOST, and the data to be written are stored in institute In the local memory for stating NVMe equipment；The third queue that mark is written in the HOST is completed in operation by the NVMe equipment；Institute The operation completion mark instruction operation is stated to be completed；The NVMe equipment sends default interruption to the HOST, indicates institute It states HOST and accesses the third queue, confirm that the operation is completed.

Specifically, (1) NVMe Controller reads NVMe order from SQ.

Wherein, the NVMe Controller is the control module of NVMe equipment side, the SQ, that is, second queue, The NVMe order, that is, the assignment instructions.Here, the operation of the NVMe order instruction is described to be written to data to be written NVMe equipment.

(2) DMA () engine that NVMe Controller operates NVMe equipment side obtains data in the memory of HOST.

(3) NVMe Controller encapsulates the distributed storage software that NVMe equipment side is sent to after the data to be written.

Wherein, the distributed storage software be NVMe equipment side for storing data.So-called encapsulation is to be written Data to be written are packaged into the format that distributed storage software can identify by data.

(4) distributed storage software returns to Response to NVMe Controller.

In fact, being exactly distributed storage software after the data for having stored NVMe Controller transmission, to NVMe Controller returns to an information, for informing that the number to be written of NVMe equipment will be written in this interaction of NVMe Controller According to having passed.

(5) operation is completed mark write-in third queue by NVMe Controller.

Wherein, the third queue can be CQ, and the operation is completed mark instruction operation and is completed (i.e. by number to be written According to write-in NVMe equipment).

(6) NVMe Controller sends MSI-X to HOST, indicates that the HOST accesses the third queue, in third It is obtained in queue after mark is completed in operation and confirms that the operation is completed.

If second, the described operation is reads data, the NVMe equipment executes the operation and specifically includes: the NVMe is set The standby read data request for receiving the HOST, and the data that continue are sent to the HOST；The NVMe equipment receives institute State HOST transmission first is interrupted, and the third queue that mark is written in the HOST is completed in operation；Mark is completed in the operation Indicate that the operation is completed, first interruption is used to indicate the NVMe equipment and completes the operation described in mark write-in Third queue in HOST memory；The NVMe equipment sends default interruption to the HOST, indicates described in the HOST access Third queue confirms that the operation is completed.

Wherein, first interruption can be DMA ((Direct Memory Access, direct memory access)) interruption.

Specifically, (1) NVMe Controller reads NVMe order from SQ queue.

Wherein, the NVMe Controller is the control module of NVMe equipment side, the SQ, that is, second queue, The NVMe order, that is, the assignment instructions.Here, the operation of NVMe order instruction is the NVMe equipment from the side HOST Memory in read data.

(2) NVMe Controller is sent to distributed storage software after encapsulating the data that continue.

The so-called encapsulation data data that will continue that continue are packaged into the format that distributed storage software can identify.

(3) distributed storage software returns to Response.

In this Response for informing that reception is completed in the data that continue described in NVMe Controller.

(4) DMA engine of NVMe Controller equipment side reads the data that continue in distributed storage software, and will The data that continue are sent to HOST.

(5) HOST completion, which is continued, returns to DMA to the side NVMe after data receiver and interrupts.

Wherein, the DMA is interrupted for informing that data receiver is completed in NVMe Controlle.

(6) NVMe Controller is received and mark write-in third queue is completed in operation after DMA is interrupted.

(7) NVMe Controller sends MSI-X to HOST, indicates that the HOST accesses the third queue, in third It is obtained in queue after mark is completed in operation and confirms that the operation is completed.

In this way, avoiding the CPU of HOST from directly operating the deposit of NVMe equipment during HOST is interacted with NVMe equipment Device.HOST is become into the memory queue wheel for actively removing HOST in NVMe equipment side to the operation of direct register twice of NVMe equipment It follows, occurs so that the CPU of HOST be avoided to cause system to hang dead situation without response NVMe equipment side register manipulation. Doorbell operation directly writes NVMe device register by original HOST and is revised as going repeating query by NVMe device drives Doorbell queue (first queue i.e. of the present invention), HOST will be in the triggering command, completion instruction write-in memories Doorbell queue is considered that read-write requests have been responded.At this time it is unplugged suddenly even if there is NVMe equipment The case where CPU operation register of HOST is without response is not will lead to, it is primary read-write time-out that system, which only will be considered that, thus effectively System is avoided to hang dead situation.It, therebetween can be in this way, HOST, which is not spent, carries out write operation to the register of NVMe equipment It is normally interacted, the system caused by NVMe equipment is extracted suddenly that can also avoid is hung dead.In addition, informing NVMe equipment Completion is interacted between HOST, NVMe equipment extraction can be carried out, to realize the hot plug of NVMe equipment.

Further, in a preferred embodiment of the invention, after the NVMe equipment obtains completion instruction, the method Further include:

The NVMe equipment discharges the third queue.

In another preferred embodiment of the invention, NVMe equipment poll first team in the register of the HOST Column include:

First queue described in the NVMe equipment active poll；

In addition, it is necessary to explanation, first queue, that is, second queue described in embodiment 1 described in the present embodiment can be with It is doorbell queue DQ.The second queue described in the present embodiment, that is, first queue described in embodiment 1, can be submission queue SQ.The third queue, which can be, completes queue CQ.

Embodiment 3:

The embodiment of the present invention provides a kind of exchange method, as shown in figure 4, the described method comprises the following steps:

301, assignment instructions are written in the first queue in the HOST memory HOST.

Wherein, the assignment instructions indicate non-volatile memory express passway NVMe equipment by the operation of execution；The NVMe Equipment is the peripheral equipment interacted with the HOST by quick Peripheral Component Interconnect PCIe bus.

302, the second queue in the HOST memory is written in triggering mark by the HOST.

The triggering mark represents the HOST and has confirmed that and will interact with the NVMe equipment, and the interaction is described NVMe equipment executes the interaction that the operation needs to carry out with the HOST.

303, second queue described in the NVMe device polling.

304, the NVMe equipment detects triggering mark in the second queue.

305, the NVMe equipment obtains assignment instructions in the first queue, executes the operation of assignment instructions instruction.

Specifically, if the operation is writes data, the NVMe equipment executes the operation and specifically includes:

If the operation is reads data, the NVMe equipment executes the operation and specifically includes: the NVMe equipment connects The read data request of the HOST is received, and the data that continue are sent to the HOST；Described in the NVMe equipment receives Operation is completed the third queue that mark is written in the HOST by the first interruption that HOST is sent；The operation is completed mark and is referred to Show that the operation is completed, first interruption is used to indicate the NVMe equipment and completes the operation described in mark write-in Third queue in HOST memory.

Wherein, the default interruption can be MSI-X, and first interruption can be DMA interruption.

306, the HOST obtains the operation and completes mark, confirms that the operation is completed, then will complete mark write-in The second queue.

The operation is completed the mark instruction operation and is completed.Completion mark represent the HOST have confirmed that it is described Interaction is completed.

In the specific implementation, being the default interruption that the HOST receives that the NVMe equipment is sent, and access the third team Column obtain the operation in the third queue and complete mark.

307, the NVMe equipment detects completion mark in the second queue.

Memory is written in triggering command by exchange method provided in an embodiment of the present invention, HOST, and the NVMe equipment is in host Triggering command is polled in first queue in the memory of HOST；The triggering command indicate the HOST have confirmed that by with it is described NVMe equipment interacts.The NVMe equipment obtains assignment instructions, executes the operation of the assignment instructions instruction.NVMe equipment Completion instruction is detected in the first queue in the memory of the HOST；Completion instruction indicate the HOST have confirmed that with The NVMe equipment completes interaction.In this way, avoiding the CPU of HOST from directly grasping during HOST is interacted with NVMe equipment Make the register of NVMe equipment, so that it is dead to avoid the CPU of HOST from causing system to be hung without response NVMe equipment side register manipulation The case where occur.The CPU operation register of HOST will not be caused without the feelings of response NVMe equipment occur and being unplugged suddenly Condition, it is that primary read-write time-out is realized so that it is dead effectively to avoid system caused by NVMe device reset from hanging that system, which only will be considered that, The hot plug of NVMe equipment.

Embodiment 4:

The embodiment of the present invention provides a kind of exchange method, is mainly used for NVMe equipment and interacts with HOST, writes data into NVMe equipment.As shown in figure 5, the described method comprises the following steps:

401, HOST writes command to SQ queue.

402, DQ (Doorbell Queue, doorbell queue) is written in triggering command by HOST.

403, NVMe Controller (controller) from DQ repeating query to triggering command.

404, NVMe Controller obtains SQ queue in the memory of HOST.

405, NVMe Controller obtains assignment instructions in SQ queue.

406, the DMA engine that NVMe Controller operates NVMe equipment side reads data to be written in the memory of HOST.

407, NVMe Controller is sent to distributed storage software after encapsulating data to be written.

408, distributed storage software returns to Response (response) to NVMe Controlle.

409, operation is completed mark write-in CQ queue and discharges SQ queue by NVMe Controller.

410, NVMe Controller sends MSI-X and interrupts to HOST.

411, HOST executes CQ queue after receiving interruption.

CQ queue is accessed, operation is obtained and completes mark.

412, HOST will complete to instruct write-in Doorbell queue.

413, NVMe Controller is polled to completion instruction, NVMe Controller release from Doorbell queue CQ queue.

So far, according to NVMe agreement, once data flow is completely write between HOST and NVMe and is just completed.

The embodiment of the present invention provides a kind of exchange method and avoids the CPU of HOST direct when data are written in the NVMe equipment The register for operating NVMe equipment, so that the CPU of HOST be avoided to cause system to be hung without response NVMe equipment side register manipulation Dead situation occurs.The CPU operation register of HOST will not be caused without response NVMe equipment occur and being unplugged suddenly Situation, it is that primary read-write time-out is realized so that it is dead effectively to avoid system caused by NVMe device reset from hanging that system, which only will be considered that, The hot plug of NVMe equipment.

Embodiment 5:

The embodiment of the present invention provides a kind of exchange method, is mainly used for NVMe equipment and interacts with HOST, HOST is set in NVMe Standby middle reading data.As shown in fig. 6, the described method comprises the following steps:

501, HOST writes command to SQ queue.

502, Doorbell queue is written in triggering command by HOST.

503, NVMe Controller is polled to triggering command from Doorbell queue.

504, NVMe Controller obtains SQ queue in the memory of HOST.

505, NVMe Controller obtains assignment instructions from SQ queue.

506, NVMe Controller is sent to distributed storage software after encapsulating the data that continue.

507, distributed storage software returns to Response.

508, the DMA engine that NVMe Controller operates NVMe equipment side is read in distributed storage software continues Data, and the data that will continue are sent to HOST.

509, HOST complete continue data reception after return DMA interrupt.

510, operation is completed mark write-in CQ queue and discharges SQ queue by NVMe Controller.

511, NVMe Controller sends MSI-X and interrupts to HOST.

512, HOST executes CQ queue after receiving interruption.

CQ queue is accessed, operation is obtained and completes mark.

513, HOST will complete to instruct write-in Doorbell queue.

514, NVMe Controller is polled to completion instruction, NVMe Controller release from Doorbell queue CQ queue.

So far, according to NVMe agreement, primary complete time data stream journey is just completed between HOST and NVMe.

The embodiment of the present invention provides a kind of exchange method and avoids the CPU of HOST from directly grasping when the NVMe equipment reads data Make the register of NVMe equipment, so that it is dead to avoid the CPU of HOST from causing system to be hung without response NVMe equipment side register manipulation The case where occur.The CPU operation register of HOST will not be caused without the feelings of response NVMe equipment occur and being unplugged suddenly Condition, it is that primary read-write time-out is realized so that it is dead effectively to avoid system caused by NVMe device reset from hanging that system, which only will be considered that, The hot plug of NVMe equipment.

Embodiment 6:

The embodiment of the present invention provides a kind of HOST, as shown in fig. 7, the HOST includes: writing unit 601, confirmation unit 602。

Writing unit 601, for assignment instructions to be written in the first queue in the HOST memory, the assignment instructions Indicate NVMe equipment by the operation of execution；The NVMe equipment is to pass through quick Peripheral Component Interconnect PCIe bus with the HOST The peripheral equipment interacted.

Said write unit 601 is also used to, and triggering mark is written to the second queue in the HOST memory；The triggering Mark represents the HOST and has confirmed that and will interact with non-volatile memory express passway NVMe equipment, and the interaction is described NVMe equipment executes the interaction that the operation needs to carry out with the HOST.

Confirmation unit 602, for confirming that the operation is completed.

Said write unit 601 is also used to, and when the confirmation unit confirmation operation is completed, will be completed mark and is write Enter the first queue, the completion mark represents the HOST and has confirmed that the interaction is completed.

The confirmation unit 602 is specifically used for, and the HOST receives the default interruption that the NVMe equipment is sent, and accesses institute The third queue in HOST memory is stated, detects that mark is completed in operation, then confirms that the operation is completed.

Memory is written in triggering command by HOST provided in an embodiment of the present invention, so that the NVMe equipment is in host HOST Memory in first queue in be polled to triggering command；The triggering command indicate the HOST have confirmed that by with the NVMe Equipment interacts.The NVMe equipment obtains assignment instructions, executes the operation of the assignment instructions instruction.NVMe equipment is in institute It states and detects completion instruction in the first queue in the memory of HOST；Completion instruction indicate the HOST have confirmed that with it is described NVMe equipment completes interaction.In this way, avoiding the CPU of HOST from directly operating during HOST is interacted with NVMe equipment The register of NVMe equipment, so that the CPU of HOST be avoided to cause system to be hung extremely without response NVMe equipment side register manipulation Situation occurs.It will not lead to the case where CPU operation register of HOST is without response NVMe equipment occur and being unplugged suddenly, It is that primary read-write is overtime that system, which only will be considered that, so that it is dead effectively to avoid system caused by NVMe device reset from hanging, realizes NVMe The hot plug of equipment.

Embodiment 7:

The embodiment of the present invention provides a kind of NVMe equipment, as shown in figure 8, the HOST includes: detection unit 701, obtains Unit 702, execution unit 703.

Detection unit 701 is used for poll first queue；The first queue is stored in the memory of host HOST.

The detection unit 701 is also used to, and detects that triggering mark, the triggering mark represent in the first queue The HOST, which has confirmed that, to be interacted with the NVMe equipment；The interaction executes operation needs and institute for the NVMe equipment State the interaction of HOST progress.

Acquiring unit 702, for obtaining assignment instructions；The assignment instructions indicate the behaviour of the HOST by execution Make.

Execution unit 703, for executing the operation.

The detection unit 701 is also used to, and completion mark is detected in the first queue；The completion mark instruction The HOST has confirmed that be completed with the interaction, and the completion mark is that the HOST confirms that the operation is completed to be written later The first queue.

The acquiring unit 702 is specifically used for: the second queue in the HOST memory is accessed, in the second queue Obtain the assignment instructions.

If operation is writes data, the execution unit 703 is specifically used for:

Exemplary: (1) NVMe Controller reads NVMe order from SQ.

(4) distributed storage software returns to Response to NVMe Controller.

(5) operation is completed mark write-in third queue by NVMe Controller.

If operation is reads data, the execution unit 703 is specifically used for:

Exemplary, (1) NVMe Controller reads NVMe order from SQ queue.

(3) distributed storage software returns to Response.

The detection unit 701 is specifically used for, first queue described in equipment active poll；

NVMe equipment provided in an embodiment of the present invention, is polled to triggering in the first queue in the memory of host HOST and refers to It enables；The triggering command indicates that the HOST has confirmed that and will interact with the NVMe equipment.The NVMe equipment, which obtains, appoints Business instruction executes the operation of the assignment instructions instruction.NVMe equipment detects in the first queue in the memory of the HOST It is instructed to completion；The completion instruction indicates that the HOST has confirmed that and completes interaction with the NVMe equipment.In this way, in HOST During interacting with NVMe equipment, the CPU of HOST is avoided directly to operate the register of NVMe equipment, to avoid HOST's CPU causes system to hang dead situation appearance NVMe equipment side register manipulation without response.Even if there is NVMe equipment quilt suddenly The case where CPU operation register of HOST is without response will not be led to by pulling out, and it is primary read-write time-out that system, which only will be considered that, thus It effectively avoids system caused by NVMe device reset from hanging dead, realizes the hot plug of NVMe equipment.

Embodiment 8:

The embodiment of the present invention provides a kind of HOST, as shown in figure 9, the HOST includes: processor 801, system bus 802 With memory 803.

Wherein, processor 801 can for central processing unit (English: central processing unit, abbreviation: CPU)。

Memory 803 is transferred to the processor 801, processor 801 for storing program code, and by the program code Following instructions are executed according to program code.Memory 803 may include volatile memory (English: volatile memory), Such as random access memory (English: random-access memory, abbreviation: RAM)；Memory 803 also may include non- Volatile memory (English: non-volatile memory), such as read-only memory (English: read-only memory, Abbreviation: ROM), flash memory (English: flash memory), hard disk (English: hard disk drive, abbreviation: HDD) or Solid state hard disk (English: solid-state drive, abbreviation: SSD).Memory 803 can also include the memory of mentioned kind Combination.It connects by system bus 802 between processor 801, memory 803 and completes mutual communication.

Processor 801, for assignment instructions to be written in the first queue in the HOST memory, the assignment instructions refer to Show NVMe equipment by the operation of execution；The NVMe equipment be with the HOST by quick Peripheral Component Interconnect PCIe bus into The peripheral equipment of row interaction.

The processor 801 is also used to, and triggering mark is written to the second queue in the HOST memory；The triggering mark Knowledge represents the HOST and has confirmed that and will interact with non-volatile memory express passway NVMe equipment, and the interaction is the NVMe Equipment executes the interaction that the operation needs to carry out with the HOST.

Wherein, so-called interaction when referring to that HOST instruction NVMe equipment will execute certain operation, executes operation in NVMe equipment Before, complete operation after, the interaction to be carried out between NVMe equipment and HOST, to ensure NVMe equipment and HOST knows certain that carry out One step process.Such as: assignment instructions are written in HOST in a step 101, and instruction NVMe equipment is write data, later in write-in triggering mark Know, so that NVMe equipment knows that HOST has been acknowledged that the NVMe equipment will be write from the memory of HOST after detecting triggering mark Data.

Confirm processor 801, for confirming that the operation is completed, when confirming that the operation is completed, will complete to identify The first queue is written, the completion mark represents the HOST and has confirmed that the interaction is completed.

The processor 801 is specifically used for, and the HOST receives the default interruption that the NVMe equipment is sent, described in access Third queue in HOST memory detects that mark is completed in operation, then confirms that the operation is completed.

Embodiment 9:

The embodiment of the present invention provides a kind of NVMe equipment, and as shown in Figure 10, the HOST includes: that processor 901, system are total Line 902 and memory 903.

Wherein, processor 901 can for central processing unit (English: central processing unit, abbreviation: CPU)。

Memory 903 is transferred to the processor 901, processor 901 for storing program code, and by the program code Following instructions are executed according to program code.Memory 903 may include volatile memory (English: volatile memory), Such as random access memory (English: random-access memory, abbreviation: RAM)；Memory 903 also may include non- Volatile memory (English: non-volatile memory), such as read-only memory (English: read-only memory, Abbreviation: ROM), flash memory (English: flash memory), hard disk (English: hard disk drive, abbreviation: HDD) or Solid state hard disk (English: solid-state drive, abbreviation: SSD).Memory 903 can also include the memory of mentioned kind Combination.It connects by system bus 902 between processor 901, memory 903 and completes mutual communication.

Processor 901 is used for poll first queue；The first queue is stored in the memory of host HOST.Described Detect that triggering mark, the triggering mark represent the HOST and have confirmed that and will hand over the NVMe equipment in first queue Mutually；The interaction is the interaction that the NVMe equipment executes that operation needs to carry out with the HOST.

Processor 901, for obtaining assignment instructions；The assignment instructions indicate the operation of the HOST by execution.

Processor 901 is also used to, and executes the operation.

The processor 901 is also used to, and completion mark is detected in the first queue；The completion mark instruction institute It states HOST and has confirmed that and be completed with the interaction, the completion mark is that the HOST confirms write-in institute after the operation is completed State first queue.With triggering mark, the address completing mark and being also possible in the first queue Position, is used to indicate whether the HOST has confirmed that the interaction is completed.

The processor 901 is specifically used for: accessing the second queue in the HOST memory, obtains in the second queue Take the assignment instructions.

If operation is writes data, the processor 901 is specifically used for:

Exemplary, 1) NVMe Controller reads NVMe order from SQ.

(4) distributed storage software returns to Response to NVMe Controller.

(5) operation is completed mark write-in third queue by NVMe Controller.

If operation is reads data, the processor 901 is specifically used for:

Exemplary: (1) NVMe Controller reads NVMe order from SQ queue.

(3) distributed storage software returns to Response.

The processor 901 is specifically used for, first queue described in equipment active poll；

Embodiment 10:

The embodiment of the present invention provides a kind of physical machine system, and as shown in figure 11, the physical machine system includes including HOST With NVMe equipment.

Specifically, the interaction of the HOST and NVMe equipment room includes:

Assignment instructions are written in the first queue in the HOST memory HOST, and the assignment instructions instruction is non-easily Storage express passway NVMe equipment is lost by the operation of execution.The NVMe equipment is mutual by quick external module with the HOST The peripheral equipment that connection PCIe bus interacts.

The second queue in the HOST memory is written in triggering mark by the HOST；Described in the triggering mark represents HOST, which has confirmed that, to be interacted with the NVMe equipment, and the interaction executes the operation needs and institute for the NVMe equipment State the interaction of HOST progress.

Second queue described in the NVMe device polling.

The NVMe equipment detects triggering mark in the second queue.

The NVMe equipment obtains assignment instructions in the first queue；The row operation.

The NVMe equipment detects completion mark in the second queue.

It should be noted that the operation of the assignment instructions instruction specifically can be the NVMe equipment the HOST's Data are read in memory, alternatively, being the request that the NVMe equipment receives that HOST reads data, response data is sent to HOST.

If the operation is writes data, the NVMe equipment executes the operation and specifically includes:

If the operation is reads data, the NVMe equipment executes the operation and specifically includes: the NVMe equipment connects The read data request of the HOST is received, and the data that continue are sent to the HOST；Described in the NVMe equipment receives Operation is completed the third queue that mark is written in the HOST by the first interruption that HOST is sent；The operation is completed mark and is referred to Show that the operation is completed, first interruption is used to indicate the NVMe equipment and completes the operation described in mark write-in Third queue in HOST memory；The NVMe equipment sends default interruption to the HOST, indicates described in the HOST access Third queue confirms that the operation is completed.

In this way, HOST will access third queue after receiving the default interruption, obtains operation therein and complete mark, into And the second queue is written by mark is completed.

First queue described in the present embodiment, can be and submit queue SQ, and second queue described in the present embodiment can be Doorbell queue DQ.The third queue, which can be, completes queue CQ.The default interruption can be MSI-X.

Physical machine system provided in an embodiment of the present invention, NVMe equipment are taken turns in the first queue in the memory of host HOST Ask triggering command；The triggering command indicates that the HOST has confirmed that and will interact with the NVMe equipment.The NVMe Equipment obtains assignment instructions, executes the operation of the assignment instructions instruction.NVMe equipment in the memory of the HOST first Completion instruction is detected in queue；The completion instruction indicates that the HOST has confirmed that and completes interaction with the NVMe equipment. In this way, avoid the CPU of HOST from directly operating the register of NVMe equipment during HOST is interacted with NVMe equipment, thus It avoids the CPU of HOST from causing system to hang dead situation without response NVMe equipment side register manipulation to occur.Even if there is NVMe Equipment is unplugged suddenly will not lead to the case where CPU operation register of HOST is without response, and it is once to read that system, which only will be considered that, Time-out is write, so that it is dead effectively to avoid system caused by NVMe device reset from hanging, realizes the hot plug of NVMe equipment.

Through the above description of the embodiments, it is apparent to those skilled in the art that, for description It is convenienct and succinct, only the example of the division of the above functional modules, in practical application, can according to need and will be upper It states function distribution to be completed by different functional modules, i.e., the internal structure of device is divided into different functional modules, to complete All or part of function described above.The specific work process of the device of foregoing description can be implemented with reference to preceding method Corresponding process in example, details are not described herein.

The unit as illustrated by the separation member may or may not be physically separated, aobvious as unit The component shown can be a physical unit or multiple physical units, it can and it is in one place, or may be distributed over Multiple and different places.Some or all of unit therein can be selected to realize this embodiment scheme according to the actual needs Purpose.In addition, the functional units in various embodiments of the present invention may be integrated into one processing unit, it is also possible to each A unit physically exists alone, and can also be integrated in one unit with two or more units.Above-mentioned integrated unit was both It can take the form of hardware realization, can also realize in the form of software functional units.

If the integrated unit is realized in the form of SFU software functional unit and sells or use as independent product When, it can store in a read/write memory medium.Based on this understanding, technical solution of the present invention is substantially in other words The all or part of the part that contributes to existing technology or the technical solution can embody in the form of software products Come, which is stored in a storage medium, including some instructions are used so that equipment (it can be single-chip microcontroller, Chip etc.) or processor (processor) perform all or part of the steps of the method described in the various embodiments of the present invention.And it is aforementioned Storage medium include: USB flash disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory The various media that can store program code such as (RAM, Random Access Memory), magnetic or disk.

The above description is merely a specific embodiment, but scope of protection of the present invention is not limited thereto, any Those familiar with the art in the technical scope disclosed by the present invention, can easily think of the change or the replacement, and should all contain Lid is within protection scope of the present invention.Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. a kind of exchange method characterized by comprising

Assignment instructions are written in the submission queue in the HOST memory host HOST, and the assignment instructions instruction is non-volatile to deposit Express passway NVMe equipment is stored up by the operation of execution；The NVMe equipment is to pass through quick Peripheral Component Interconnect with the HOST The peripheral equipment that PCIe bus interacts；

The doorbell queue in the HOST memory is written in triggering mark by the HOST；The triggering mark has represented the HOST Confirmation will be interacted with the NVMe equipment, and the interaction is that the NVMe equipment executes the operation needs and the HOST The interaction of progress；

The HOST confirmation operation is completed, then will complete mark and the doorbell queue is written, the completion mark represents The HOST has confirmed that the interaction is completed.

2. the method according to claim 1, wherein the HOST confirmation operation is completed and includes:

The HOST receives the default interruption that the NVMe equipment is sent, and accesses the completion queue in the HOST memory, detects Mark is completed to operation, then confirms that the operation is completed；

Wherein, the default interruption is used to indicate the HOST and accesses the completion queue, and mark instruction institute is completed in the operation Operation is stated to be completed.

3. a kind of exchange method characterized by comprising

Non-volatile memory express passway NVMe device polling doorbell queue；The doorbell queue is stored in the memory of host HOST In；

The NVMe equipment detects that triggering mark, the triggering mark represent the HOST and have confirmed that in the doorbell queue It will be interacted with the NVMe equipment；The interaction is the friendship that the NVMe equipment executes that operation needs to carry out with the HOST Mutually；

The NVMe equipment obtains assignment instructions；The assignment instructions indicate the NVMe equipment by the operation of execution；

The NVMe equipment executes the operation；

The NVMe equipment detects completion mark in the doorbell queue；The completion mark indicates that the HOST has confirmed that The interaction is completed, and the completion mark is that the HOST confirms that the operation completes that the doorbell queue is written later.

4. according to the method described in claim 3, it is characterized in that, NVMe equipment acquisition assignment instructions include:

The NVMe equipment accesses the submission queue in the HOST memory, obtains the task in the submission queue and refers to It enables.

5. the method according to claim 3 or 4, which is characterized in that if the operation is to write data, the NVMe equipment The operation is executed to specifically include:

The NVMe equipment obtains data to be written in the register of the HOST, and the data to be written is stored in described In the local memory of NVMe equipment；

The completion queue that mark is written in the HOST is completed in operation by the NVMe equipment；Mark instruction institute is completed in the operation Operation is stated to be completed；

The NVMe equipment to the HOST send it is default interrupt, indicate that the HOST accesses the completion queue, described in confirmation Operation is completed.

6. the method according to claim 3 or 4, which is characterized in that if the operation is reading data, the NVMe equipment The operation is executed to specifically include:

The NVMe equipment receives the read data request of the HOST, and the data that will continue are sent to the HOST；

The NVMe equipment receives the HOST is sent first and interrupts, and the completion that mark is written in the HOST is completed in operation Queue；The operation is completed the mark instruction operation and is completed, and first interruption is used to indicate the NVMe equipment for institute It states operation and completes the completion queue that mark is written in the HOST memory；

7. according to the method described in claim 3, it is characterized in that, the NVMe device polling doorbell queue includes:

Doorbell queue described in the NVMe equipment active poll；

Or, the NVMe equipment receives doorbell queue described in poll after the instruction information that the HOST is sent.

8. a kind of host HOST characterized by comprising

Writing unit, for assignment instructions to be written in the submission queue in the HOST memory, the assignment instructions instruction is non- Volatile storage express passway NVMe equipment is by the operation of execution；The NVMe equipment is to pass through quick external module with the HOST The peripheral equipment that interconnection PCIe bus interacts；

Said write unit is also used to, and triggering mark is written to the doorbell queue in the HOST memory；The triggering identifies generation HOST described in table, which has confirmed that, to be interacted with non-volatile memory express passway NVMe equipment, and the interaction is the NVMe equipment Execute the interaction that the operation needs to carry out with the HOST；

Confirmation unit, for confirming that the operation is completed；

Said write unit is also used to, and when the confirmation unit confirmation operation is completed, will be completed described in mark write-in Doorbell queue, the completion mark represent the HOST and have confirmed that the interaction is completed.

9. HOST according to claim 8, which is characterized in that the confirmation unit is specifically used for,

10. a kind of non-volatile memory express passway NVMe equipment characterized by comprising

Detection unit is used for the queue of poll doorbell；The doorbell queue is stored in the memory of host HOST；

The detection unit is also used to, and triggering mark is detected in the doorbell queue, and the triggering identifies described in representative HOST, which has confirmed that, to be interacted with the NVMe equipment；The interaction be the NVMe equipment execute operation need with it is described The interaction that HOST is carried out；

Execution unit, for executing the operation；

The detection unit is also used to, and completion mark is detected in the doorbell queue；Described in the completion mark instruction HOST has confirmed that be completed with the interaction, and the completion mark is that the HOST confirms that the operation is completed described in write-in later Doorbell queue.

11. equipment according to claim 10, which is characterized in that the acquiring unit is specifically used for: accessing the HOST Submission queue in memory obtains the assignment instructions in the submission queue.

12. equipment described in 0 or 11 according to claim 1, which is characterized in that if the operation is to write data, the execution Unit is specifically used for:

Data to be written are obtained in the register of the HOST, and the data to be written are stored in the local of the NVMe equipment In memory；

The completion queue that mark is written in the HOST is completed into operation；It is complete that the mark instruction operation is completed in the operation At；

Default interruption is sent to the HOST, indicates that the HOST accesses the completion queue, confirms that the operation is completed.

13. equipment described in 0 or 11 according to claim 1, which is characterized in that if the operation is reading data, the execution Unit is specifically used for:

The read data request of the HOST is received, and the data that will continue are sent to the HOST；

It receives the HOST is sent first to interrupt, the completion queue that mark is written in the HOST is completed into operation；The behaviour Work is completed the mark instruction operation and is completed, and first interruption is used to indicate the NVMe equipment and completes to mark by the operation Know the completion queue being written in the HOST memory；

14. equipment according to claim 10, which is characterized in that the detection unit is specifically used for, equipment active poll The doorbell queue；

Or, receiving doorbell queue described in poll after the instruction information that the HOST is sent.

15. a kind of physical machine system, including host HOST and non-volatile memory express passway NVMe equipment, which is characterized in that

Assignment instructions are written in the submission queue in the HOST memory HOST, and the assignment instructions instruction is non-volatile to deposit Express passway NVMe equipment is stored up by the operation of execution；The NVMe equipment is to pass through quick Peripheral Component Interconnect with the HOST The peripheral equipment that PCIe bus interacts；

Doorbell queue described in the NVMe device polling；

The NVMe equipment detects triggering mark in the doorbell queue；

The NVMe equipment obtains assignment instructions in the submission queue；

The NVMe equipment executes the operation；

The HOST obtains the operation and completes mark, confirms that the operation is completed, then will complete mark and the doorbell is written Queue；The operation is completed the mark instruction operation and is completed；The completion mark represents the HOST and has confirmed that the friendship Mutually it is completed；

The NVMe equipment detects completion mark in the doorbell queue.