CN106484549A

CN106484549A - A kind of exchange method, NVMe equipment, HOST and physical machine system

Info

Publication number: CN106484549A
Application number: CN201510547074.1A
Authority: CN
Inventors: 种锋生; 张羽; 俞柏峰
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2015-08-31
Filing date: 2015-08-31
Publication date: 2017-03-08
Anticipated expiration: 2035-08-31
Also published as: CN106484549B

Abstract

The present invention provides a kind of exchange method, NVMe equipment, HOST and physical machine system, it is related to field of computer technology, for realizing the hot plug of NVMe equipment, on the premise of ensureing that HOST side is normally interacted with NVMe equipment, can be prevented effectively from and be hung extremely due to the system that SDI card (NVMe equipment) system reset leads to.Including：Assignment instructions are write in the first queue in described HOST internal memory by main frame HOST, and described assignment instructions indicate the operation that NVMe equipment will execute；NVMe equipment is the ancillary equipment being interacted by PCIe bus with HOST；HOST will trigger the second queue in mark write HOST internal memory；Triggering mark is represented HOST and has confirmed that and will be interacted with NVMe equipment, and interaction needs and interacting that HOST is carried out for the execution operation of NVMe equipment；HOST confirm operation complete, then will complete mark write first queue, complete mark represent HOST have confirmed that interaction complete.

Description

A kind of exchange method, NVMe equipment, HOST and physical machine system

Technical field

The present invention relates to field of computer technology, more particularly, to a kind of exchange method and, NVMe (Non Volatile Memory express, non-volatile memory express passway) equipment, HOST (main frame) And physical machine system.

Background technology

Generally, operate on physical machine CPU (Central Processing Unit, processor) Software can be divided into the business software of systems soft ware and user.As shown in figure 1, being existing SDI (Service Driven lnfrastructure, business-driven architecture) framework, will portion originally Administration is unloaded on independent SDI card in the systems soft ware on processor, and CPU only runs user Business software.So, just system has been divided into HOST side, NVMe equipment side two parts, two Pass through between person PCIe (Peripheral Component Interconnect express, quickly outer Parts interconnect) bus communicated.

SDI card is rendered as NVMe equipment to CPU (HOST side), by PCIe bus and Standard NVMe agreement is communicated.NVMe equipment is (such as：SDI card) carry out with HOST side During communication interaction, the CPU of HOST side needs successively twice NVMe equipment to be deposited Device carries out write operation (carrying out doorbell operation), rewrites certain field in the depositor of NVMe equipment, NVMe is known to interact with HOST, to ensure interactive being normally carried out.

Generally, SDI card is a separate hardware card being inserted on Servers standard PCIe slot position, and card has Bearing system software and firmware, these softwares and firmware are to need to be upgraded in use.? Generally, the upgrading of software and firmware is required for SDI card system reset just can come into force.SDI Card system reset, is equal to NVMe equipment for HOST side and is unplugged suddenly.If When the depositor of CPU operation SDI card of HOST side, SDI card system reset, lead to CPU Read/write requests cannot respond, CPU will be mistakenly considered unit exception, quotes MCE (Machine Check Exception, machine check mistake) allow whole system to hang extremely.

Content of the invention

The embodiment of the present invention provides a kind of exchange method, NVMe equipment, HOST and physical machine system System it is ensured that on the premise of HOST side normally interacted with NVMe equipment, can be prevented effectively from due to The system that SDI card (NVMe equipment) system reset leads to is hung extremely, and the heat realizing NVMe equipment is inserted Pull out.

Embodiments of the invention adopt the following technical scheme that：

In a first aspect, disclosing a kind of exchange method, including：

Assignment instructions are write in the first queue in described HOST internal memory by main frame HOST, institute State the operation that assignment instructions indicate that non-volatile memory express passway NVMe equipment will execute；Described NVMe equipment is to be interacted by quick Peripheral Component Interconnect PCIe bus with described HOST Ancillary equipment；

Described HOST writes the second queue in described HOST internal memory by triggering mark；Described Triggering mark is represented described HOST and has confirmed that and will be interacted with described NVMe equipment, described Interaction needs and interacting that described HOST is carried out for the described operation of described NVMe equipment execution；

Described HOST confirms that described operation completes, then will complete mark and write described first team Row, described complete mark and represent described HOST to have confirmed that described interaction completes.

In conjunction with a first aspect, in the first possible implementation of first aspect, described HOST confirm described operation completed including：

Described HOST receives the default interruption that described NVMe equipment sends, and accesses described HOST The 3rd queue in internal memory, detects operation and completes to identify, then confirm that described operation completes；

Wherein, described default interrupt for indicating that described HOST accesses described 3rd queue, institute State operation complete mark indicate described operation complete.

Second aspect, discloses a kind of exchange method, including：

Non-volatile memory express passway NVMe device polling first queue；Described first queue is deposited Storage is in the internal memory of main frame HOST；

Described NVMe equipment detects triggering mark, described triggering mark in described first queue Knowledge is represented described HOST and has confirmed that and will be interacted with described NVMe equipment；Described interaction is Described NVMe equipment execution operation needs and interacting that described HOST is carried out；

Described NVMe equipment obtains assignment instructions；Described assignment instructions indicate that described NVMe sets The standby described operation by execution；

Described NVMe equipment executes described operation；

Described NVMe equipment detects in described first queue and completes to identify；Described complete mark Know and indicate that described HOST has confirmed that described interaction completes, the described mark that completes is described HOST Confirm that described operation writes described first queue after completing.

In conjunction with second aspect, in the first possible implementation of second aspect, described NVMe equipment obtains assignment instructions and includes：

Described NVMe equipment accesses the second queue in described HOST internal memory, described second Described assignment instructions are obtained in queue.

In conjunction with the first possible implementation of second aspect or second aspect, in second aspect The possible implementation of second in, if described operate as writing data, described NVMe sets The described operation of standby execution specifically includes：

Described NVMe equipment obtains data to be written in the depositor of described HOST, and by institute State data storage to be written in the local memory of described NVMe equipment；

Described NVMe equipment will operate the 3rd queue completing in the mark described HOST of write； Described operation completes mark and indicates that described operation completes；

Described NVMe equipment sends default interruption to described HOST, indicates described HOST Access described 3rd queue, confirm that described operation completes.

In conjunction with the first possible implementation of second aspect or second aspect, in second aspect The third possible implementation in, if described operate as reading data, described NVMe sets The described operation of standby execution specifically includes：

Described NVMe equipment receives the read data request of described HOST, and treats reading by described According to being sent to described HOST；

Described NVMe equipment receives the first interruption that described HOST sends, and operation is completed to mark Know the 3rd queue writing in described HOST；Described operation has completed the described operation of mark instruction Complete, described first interrupts writing for indicating that described operation is completed mark by described NVMe equipment Enter the 3rd queue in described HOST internal memory；

Described NVMe equipment sends default interruption to described HOST, and the described HOST of instruction visits Ask described 3rd queue, confirm that described operation completes.

In conjunction with second aspect, in the 4th kind of possible implementation of second aspect, described NVMe device polling first queue includes：

First queue described in described NVMe equipment active poll；

Or, described NVMe equipment receives described in poll after the configured information that described HOST sends First queue.

The third aspect, discloses a kind of main frame HOST, including：

Writing unit, for assignment instructions being write in the first queue in described HOST internal memory, Described assignment instructions indicate the operation that non-volatile memory express passway NVMe equipment will execute；Institute Stating NVMe equipment is to be handed over by quick Peripheral Component Interconnect PCIe bus with described HOST Mutual ancillary equipment；

Said write unit is additionally operable to, and triggering mark is write second in described HOST internal memory Queue；Described triggering mark represent described HOST have confirmed that by with non-volatile memory express passway NVMe equipment interacts, and described interaction is that the described operation of described NVMe equipment execution needs With interacting that described HOST is carried out；

Confirmation unit, for confirming that described operation completes；

Said write unit is additionally operable to, when described confirmation unit confirms that described operation completes, Mark will be completed and write described first queue, and described complete mark and represent described HOST to have confirmed that Described interaction completes.

In conjunction with the third aspect, in the first possible implementation of the third aspect, described true Recognize unit specifically for,

Fourth aspect, discloses a kind of non-volatile memory express passway NVMe equipment, including：

Detector unit, for poll first queue；Described first queue is stored in main frame HOST Internal memory in；

Described detector unit is additionally operable to, and triggering mark is detected in described first queue, described Triggering mark is represented described HOST and has confirmed that and will be interacted with described NVMe equipment；Described Interaction needs and interacting that described HOST is carried out for described NVMe equipment execution operation；

Acquiring unit, for obtaining assignment instructions；Described assignment instructions indicate that described HOST will The described operation of execution；

Performance element, for executing described operation；

Described detector unit is additionally operable to, and detects and complete to identify in described first queue；Described Complete mark and indicate that described HOST has confirmed that and complete, the described mark that completes is with described interaction Described HOST confirms that described operation writes described first queue after completing.

In conjunction with fourth aspect, in the first possible implementation of fourth aspect, described obtain Take unit specifically for：Access the second queue in described HOST internal memory, in described second team Described assignment instructions are obtained in row.

In conjunction with the first possible implementation of fourth aspect or fourth aspect, in fourth aspect The possible implementation of second in, if operating as writing data, described performance element is specifically used In：

Obtain data to be written in the depositor of described HOST, and by described data storage to be written In the local memory of described NVMe equipment；

Operation is completed to identify the 3rd queue writing in described HOST；Described operation completes to mark Know and indicate that described operation completes；

Send default interruption to described HOST, the described HOST of instruction accesses described 3rd team Row, confirm that described operation completes.

In conjunction with the first possible implementation of fourth aspect or fourth aspect, in fourth aspect The third possible implementation in, if operating as reading data, described performance element specifically uses In：

Receive the read data request of described HOST, and by the described data is activation that continues to described HOST；

Receive the first interruption that described HOST sends, operation is completed mark and writes described HOST The 3rd interior queue；Described operation completes mark and indicates that described operation completes, described first interruption Write in described HOST internal memory for indicating that described operation is completed mark by described NVMe equipment The 3rd queue；

Send default interruption to described HOST, the described HOST of instruction accesses described 3rd queue, Confirm that described operation completes.

In conjunction with fourth aspect, in the 4th kind of possible implementation of fourth aspect, described inspection Survey unit specifically for first queue described in equipment active poll；

Or, receiving first queue described in poll after the configured information that described HOST sends.

5th aspect, discloses a kind of physical machine system, including main frame HOST with non-volatile deposit Storage express passway NVMe equipment,

Assignment instructions are write in the first queue in described HOST internal memory by described HOST, institute State the operation that assignment instructions indicate that non-volatile memory express passway NVMe equipment will execute；Described NVMe equipment is to be interacted by quick Peripheral Component Interconnect PCIe bus with described HOST Ancillary equipment；

Second queue described in described NVMe device polling；

Described NVMe equipment detects triggering mark in described second queue；

Described NVMe equipment obtains assignment instructions in described first queue；

Described NVMe equipment executes described operation；

Described HOST obtains described operation and completes to identify, and confirms that described operation completes, then will Complete mark and write described second queue；Described operation completes mark and indicates that described operation completes； Described complete mark and represent described HOST to have confirmed that described interaction completes；

Described NVMe equipment detects in described second queue and completes to identify.

Exchange method provided in an embodiment of the present invention, NVMe equipment, HOST and physical machine system, Described NVMe equipment is polled to triggering command in the first queue in the internal memory of main frame HOST； Described triggering command indicates that described HOST is had confirmed that and will be interacted with described NVMe equipment. Described NVMe equipment obtains assignment instructions, the operation of execution described assignment instructions instruction.NVMe Equipment detects in the first queue in the internal memory of described HOST and completes to instruct；Described complete Instruction indicates that described HOST has confirmed that to complete with described NVMe equipment and interacts.So, exist During HOST is interacted with NVMe equipment, it is to avoid the CPU of HOST directly operates NVMe The depositor of equipment, thus avoid the CPU of HOST to NVMe equipment side register manipulation no Response leads to system to hang dead situation appearance.Even if NVMe equipment occurs be unplugged suddenly also not The situation of the CPU operation depositor no response of HOST can be led to, it is once that system only will be considered that Read-write time-out, thus it is dead effectively to avoid the system that NVMe device reset causes to hang, realizes The hot plug of NVMe equipment.

Brief description

In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, below The accompanying drawing of required use in embodiment or description of the prior art will be briefly described, aobvious and easy Insight, drawings in the following description are only some embodiments of the present invention, common for this area For technical staff, on the premise of not paying creative work, can also obtain according to these accompanying drawings Obtain other accompanying drawings.

Fig. 1 is the schematic diagram of existing SDI framework；

Fig. 2 is the schematic flow sheet of the exchange method that the embodiment of the present invention 1 provides；

Fig. 3 is the schematic flow sheet of the exchange method that the embodiment of the present invention 2 provides；

Fig. 4 is the schematic flow sheet of the exchange method that the embodiment of the present invention 3 provides；

Fig. 5 is the schematic flow sheet writing data that the embodiment of the present invention 4 provides；

Fig. 6 is the schematic flow sheet of the reading data that the embodiment of the present invention 5 provides；

Fig. 7 is the structured flowchart of the HOST that the embodiment of the present invention 6 provides；

Fig. 8 is the structured flowchart of the NVMe equipment that the embodiment of the present invention 7 provides；

Fig. 9 is the structured flowchart of the HOST that the embodiment of the present invention 8 provides；

Figure 10 is the structured flowchart of the NVMe equipment that the embodiment of the present invention 9 provides；

Figure 11 is the Organization Chart of the physical machine system that the embodiment of the present invention 10 provides.

Specific embodiment

Below in conjunction with the accompanying drawing in the embodiment of the present invention, to the technical side in the embodiment of the present invention Case is clearly and completely described it is clear that described embodiment is only a present invention part Embodiment, rather than whole embodiments.Based on the embodiment in the present invention, the common skill in this area The every other embodiment that art personnel are obtained under the premise of not making creative work, broadly falls into The scope of protection of the invention.

So-called SDI framework, the systems soft ware that will be originally deployed on processor is unloaded to independent On SDI card, CPU only runs the business software of user.So, just system two parts have been divided into. As shown in figure 1, part A is referred to as HOST (main frame) side, part B is referred to as NVMe equipment side. It is often necessary to SDI card system reset could be made have bearing system software and firmware normally to rise on card Level.When SDI card does system reset action, it is equal to NVMe equipment quilt suddenly for CPU Pull out.

In existing standard, NVMe equipment is specifically included with HOST side interaction flow：

(1) CPU (CPU of HOST side) write command to SQ (Submission Queue, Submit queue to), will this interactive order executing write in SQ；

(2) Doorbell (doorbell) depositor of CPU write NVMe equipment, this is CPU pair The direct operation of NVMe device register, HOST informs side that NVMe equipment will carry out the two Between interaction；

(3) NVMe equipment reads the order writing in step (1) from SQ queue；

(4) NVMe equipment executes this order；

(5) NVMe equipment will complete data write CQ (Completion Queue, completes team Row) instruction has completed the order that step (1) writes, and discharge SQ；

(6) NVMe Contreller sends MSI-X and interrupts to CPU, indicates CPU execution CQ；

(7) have no progeny during CPU receives execution CQ；

(8) the Doorbell depositor of CPU write NVMe equipment, this is HOST to NVMe The direct operation of device register.Subsequently NVMe equipment release CQ queue.Once complete NVMe protocol interaction completes.

In above-mentioned flow process, (2nd) individual step and (8th) step are that HOST posts to NVMe equipment The direct operation of storage, remaining step is all the read-write to our internal memory for the HOST side, the row of equipment side For.In step (2), (8), if NVMe equipment is pulled out suddenly (such as：SDI sticks into Row resets), the read/write requests that at this moment HOST side CPU initiates cannot respond, and HOST will Think unit exception, quote MCE mistake and allow whole system to hang extremely.

So-called hot plug (hot-plugging or Hot Swap), that is, warm swap is it is simply that user Do not closing system, taking out in the case of not cutting off the electricity supply and change the hard disk damaging, power supply or board Deng part, do not affect the normal operation of system simultaneously.The present invention is intended to provide a kind of NVMe equipment Hot plug implementation method is so that extract (such as in NVMe equipment：SDI card does system reset) when, Do not affect the normal operation of system.

In addition, doing to queue according to the present invention to illustrate.Queue is one of frequently-used data structure, It is a kind of special linear list, it only allows to carry out deletion action in the front end (frent) of table, and The rear end (rear) of table carries out update.Wherein, the end carrying out update is referred to as tail of the queue, enters The end of row deletion action is referred to as team's head.

Embodiment 1：

The embodiment of the present invention provides a kind of exchange method, as shown in Fig. 2 methods described includes following step Suddenly：

101st, assignment instructions are write in the first queue in described HOST internal memory by HOST, described Assignment instructions indicate the operation that NVMe equipment will execute；Described NVMe equipment is and described HOST The ancillary equipment being interacted by quick Peripheral Component Interconnect PCIe bus.

Wherein, described operation, can be that described NVMe equipment is read in the internal memory of described HOST Fetch data, or, it is that described NVMe equipment receives the request that HOST reads data, by number of responses According to being sent to HOST.Queue is a kind of data structure, for data storage.

102nd, described HOST writes the second queue in described HOST internal memory by triggering mark；Institute State triggering mark to represent described HOST and have confirmed that and will interact with described NVMe equipment, described Interaction needs and interacting that described HOST is carried out for the described operation of described NVMe equipment execution.

Wherein, so-called interaction is that the object of participation activity can mutually exchange, interactive on both side.At this Refer in particular in inventive embodiments：When HOST instruction NVMe equipment will execute certain operation, in NVMe Before equipment execution operation, complete operation after, NVMe equipment and to be carried out exchanging between HOST, To guarantee that NVMe equipment and HOST know each step flow process carrying out.Example, work as HOST Instruction NVMe equipment writes data in addition it is also necessary to write triggering mark is so that NVMe equipment detects Know that HOST has been acknowledged that described NVMe equipment will be write from the internal memory of HOST after triggering mark Data.And for example：When NVMe equipment execution data writing operation, not merely in HOST Deposit acquisition data in addition it is also necessary to write operation completes to be identified to the internal memory of HOST after completing to write data, HOST is made to know that NVMe equipment has completed to write data.

In addition, described triggering command can be one of described first queue address bit, for indicating Whether described HOST has confirmed that will be interacted with described NVMe equipment.Example, address bit Represent for " 0 " that described HOST is unconfirmed will to be interacted with described NVMe equipment, address bit is " 1 " is represented described HOST and has confirmed that and will be interacted with described NVMe equipment.

103rd, described HOST confirms that described operation completes, then will complete mark write described first Queue, described completes mark and represents described HOST to have confirmed that described interaction completes.

It should be noted that as described triggering mark, the described mark that completes can also be described the One of one queue address bit, for indicating whether described HOST has confirmed that described interaction is complete Become.

In implementing, described HOST confirm described operation completed including：

Wherein, described default interrupt for indicating that described HOST accesses described 3rd queue, described behaviour Complete mark and indicate that described operation completes.

It should be noted that described default interruption can be MSI (Message Signaled Interrupt, information interrupts)-X.In addition, in the present embodiment, described first queue is permissible It is SQ (Submit Queue submits queue to), described second queue can be DQ (Doorbell Queue, doorbell queue), described 3rd queue can be that (Complete Queue completes CQ Queue).

In existing NVMe equipment with HOST interaction, HOST is to NVMe equipment Doorbell operation is the depositor directly being write NVMe equipment by finger HOST, changes certain field With inform NVMe equipment need interact with HOST, in the process, if NVMe sets Standby system reset, the write request that may result in HOST cannot respond, and system quotes MCE, enters And system is suspended.In the present invention, Doorbell operation is revised as being gone by NVMe device drives The register memory repeating query first queue of HOST, to determine whether to interact with HOST.This Sample both ensure that interact between NVMe equipment and HOST was normally carried out, turn avoid due to NVMe device systems reset the system extension leading to extremely.

Exchange method provided in an embodiment of the present invention, described NVMe equipment is main frame HOST's It is polled to triggering command in first queue in internal memory；Described triggering command indicates described HOST Have confirmed that and will interact with described NVMe equipment.Described NVMe equipment obtains assignment instructions, Execute the operation of described assignment instructions instruction.NVMe equipment in the internal memory of described HOST Detect in one queue and complete to instruct；Described complete instruction indicate described HOST have confirmed that with described NVMe equipment completes interaction.So, during HOST is interacted with NVMe equipment, The CPU avoiding HOST directly operates the depositor of NVMe equipment, thus avoiding HOST's CPU no responds to NVMe equipment side register manipulation and leads to system to hang dead situation appearance.I.e. Make to occur NVMe equipment and be unplugged suddenly to be also not result in the CPU operation depositor of HOST no The situation of response, it is once to read and write time-out, thus effectively avoiding NVMe to set that system only will be considered that The standby system causing that resets is hung extremely, realizes the hot plug of NVMe equipment.

Embodiment 2：

The embodiment of the present invention provides a kind of exchange method, as shown in figure 3, methods described includes following step Suddenly：

201st, NVMe device polling first queue；Described first queue is stored in main frame HOST's In internal memory.

So-called poll, refers to that NVMe equipment goes monitoring or constantly goes to read in HOST internal memory First queue, until reading described triggering command (such as：The numerical value of particular address position changes： It is changed into " 1 ") then it is assumed that NVMe equipment will be interacted with described HOST.

202nd, described NVMe equipment detects triggering mark, described triggering in described first queue Mark is represented described HOST and has confirmed that and will be interacted with described NVMe equipment；Described interaction is Described NVMe equipment execution operation needs and interacting that described HOST is carried out.

Wherein, described triggering command can be one of described first queue address bit, for indicating Whether described HOST has confirmed that will be interacted with described NVMe equipment.Example, address bit Represent for " 0 " that described HOST is unconfirmed will to be interacted with described NVMe equipment, address bit is " 1 " is represented described HOST and has confirmed that and will be interacted with described NVMe equipment.

In addition, described operation, can be that described NVMe equipment is read in the internal memory of described HOST Fetch data, or, it is that described NVMe equipment receives the request that HOST reads data, by number of responses According to being sent to HOST.Queue is a kind of data structure, for data storage.

So-called interaction, when referring to that HOST instruction NVMe equipment will execute certain operation, in NVMe Before equipment execution operation, complete operation after, NVMe equipment and to be carried out interacting between HOST, To guarantee that NVMe equipment and HOST know a certain step flow process carrying out.As：HOST is in step Write assignment instructions in 101, instruction NVMe equipment is write data, afterwards in write triggering mark, NVMe equipment is made to know that HOST has been acknowledged described NVMe equipment after triggering mark is detected Data will be write from the internal memory of HOST.

203rd, described NVMe equipment obtains assignment instructions；Described assignment instructions indicate described NVMe The described operation that equipment will execute.

Specifically, described NVMe equipment accesses the second queue in described HOST internal memory, in institute State and in second queue, obtain described assignment instructions.

204th, described NVMe equipment executes described operation.

Can be specifically that described NVMe equipment reads data in the internal memory of described HOST, or Person, is that described NVMe equipment receives the request that HOST reads data, response data is sent to HOST.

205th, described NVMe equipment detects in described first queue and completes to identify；Described complete Mark indicates that described HOST has confirmed that described interaction completes, and the described mark that completes is described HOST Confirm that described operation writes described first queue after completing.

As described triggering mark, the described mark that completes can also be one of described first queue Address bit, for indicating whether described HOST has confirmed that described interaction completes.

In existing NVMe equipment with HOST interaction, HOST is to NVMe equipment Doorbell operation is the depositor directly being write NVMe equipment by finger HOST, changes certain field With inform NVMe equipment need interact with HOST, in the process, if NVMe sets Standby system reset, the write request that may result in HOST cannot respond, and system quotes MCE, enters And system is suspended.In the present invention, Doorbell operation is revised as being gone by NVMe device drives The register memory repeating query first queue of HOST, will be handed over determining whether HOST has confirmed that Mutually.So, HOST does not spend the depositor to NVMe equipment and carries out write operation it is possible to avoid Due to NVMe equipment extract suddenly the system that (i.e. SDI card system reset) lead to hang dead.Separately Outward, inform that NVMe equipment will be interacted with HOST, interaction can not carry out NVMe before completing Equipment extracts (i.e. SDI card system reset).

Described NVMe equipment executes described operation, specifically can include following two situations：

If first described operate as writing data, the described operation of described NVMe equipment execution is concrete to wrap Include：

Described NVMe equipment obtains data to be written in the depositor of described HOST, and will be described Data storage to be written is in the local memory of described NVMe equipment；Described NVMe equipment will operate Complete to identify the 3rd queue writing in described HOST；Described operation completes mark and indicates described operation Complete；Described NVMe equipment sends default interruption to described HOST, indicates described HOST Access described 3rd queue, confirm that described operation completes.

Specifically, (1) NVMe Controller reads NVMe order from SQ.

Wherein, described NVMe Controller is the control module of NVMe equipment side, described SQ I.e. described second queue, described NVMe order is described assignment instructions.Here, described NVMe The operation of order instruction is that data to be written is written to described NVMe equipment.

(2) NVMe Controller operates the DMA () engine of NVMe equipment side in HOST Internal memory in obtain data.

(3) NVMe Controller sends to NVMe equipment side after encapsulating described data to be written Distributed storage software.

Wherein, described distributed storage software is described NVMe equipment side for data storage. So-called encapsulation data to be written data to be written will be packaged into the form that distributed storage software can identify.

(4) distributed storage software returns Response to NVMe Controller.

In fact, being exactly distributed storage software in the data having stored NVMe Controller transmission Afterwards, return an information to NVMe Controller, be used for informing NVMe Controller originally The data to be written that secondary interaction will write NVMe equipment has passed.

(5) operation is completed mark write the 3rd queue by NVMe Controller.

Wherein, described 3rd queue can be CQ, and described operation completes mark instruction operation and completes (data to be written being write NVMe equipment).

(6) NVMe Controller sends MSI-X to HOST, and the described HOST of instruction accesses Described 3rd queue, obtains in the 3rd queue after operation completes mark and confirms that described operation completes.

If second described operate as reading data, the described operation of described NVMe equipment execution is concrete to wrap Include：Described NVMe equipment receives the read data request of described HOST, and by the described data that continues It is sent to described HOST；Described NVMe equipment receives the first interruption that described HOST sends, Operation is completed to identify the 3rd queue writing in described HOST；Described operation completes mark instruction institute State operation complete, described first interrupt for indicate described NVMe equipment by described operation complete mark Know the 3rd queue writing in described HOST internal memory；Described NVMe equipment is sent out to described HOST Send default interruption, the described HOST of instruction accesses described 3rd queue, confirms that described operation completes.

Wherein, described first interrupt can be DMA ((Direct Memory Access, directly interior Access)) interrupt.

Specifically, (1) NVMe Controller reads NVMe order from SQ queue.

Wherein, described NVMe Controller is the control module of NVMe equipment side, described SQ I.e. described second queue, described NVMe order is described assignment instructions.Here, described NVMe The operation of order instruction is that described NVMe equipment reads data from the internal memory of HOST side.

(2) NVMe Controller sends to distributed storage software after encapsulating the data that continues.

The so-called encapsulation data data that will continue that continues is packaged into what distributed storage software can identify Form.

(3) distributed storage software returns Response.

It is used for informing that the data that continues described in NVMe Controller completes to connect in this Response Receive.

(4) DMA engine of NVMe Controller equipment side reads in distributed storage software Continue data, and the data is activation that will continue is to HOST.

(5) HOST completes to continue and returns DMA to NVMe side after data receiver and interrupt.

Wherein, described DMA interrupts being used for informing that NVMe Controlle has completed data receiver.

(6) NVMe Controller receives to have no progeny in DMA and operation is completed mark write the 3rd team Row.

(7) NVMe Controller sends MSI-X to HOST, and the described HOST of instruction accesses Described 3rd queue, obtains in the 3rd queue after operation completes mark and confirms that described operation completes.

So, during HOST is interacted with NVMe equipment, it is to avoid the CPU of HOST Directly operate the depositor of NVMe equipment.By HOST directly depositing twice to NVMe equipment Device operation becomes the memory queue repeating query that HOST is actively removed in NVMe equipment side, thus avoiding HOST CPU NVMe equipment side register manipulation no responded lead to system to hang dead situation to occur. Doorbell operation is directly write NVMe device register by original HOST and is revised as by NVMe Device drives go repeating query Doorbell queue (i.e. first queue of the present invention), and HOST will be described Triggering command, the Doorbell queue completing in instruction write internal memory, that is, be considered read-write requests Meet with a response.Also it is not result in HOST's even if NVMe equipment at this time occurring and being unplugged suddenly The situation of CPU operation depositor no response, it is once to read and write time-out that system only will be considered that, thus effectively The system that avoids hang dead situation.So, HOST does not spend the depositor to NVMe equipment and carries out Write operation, can also normally be interacted therebetween, can also avoid and be dashed forward due to NVMe equipment So extract the system leading to hang extremely.In addition, informing having interacted between NVMe equipment and HOST Become, NVMe equipment can be carried out and extract, thus realizing the hot plug of NVMe equipment.

Further, in a preferred embodiment of the invention, described NVMe equipment obtains and completes to instruct Afterwards, methods described also includes：

Described NVMe equipment discharges described 3rd queue.

In another preferred embodiment of the present invention, described NVMe equipment posting in described HOST In storage, poll first queue includes：

First queue described in described NVMe equipment active poll；

Or, described NVMe equipment receives described in poll after the configured information that described HOST sends the One queue.

In addition, it is necessary to explanation, the first queue described in the present embodiment is the described in embodiment 1 Two queues, can be doorbell queue DQ.Described second queue described in the present embodiment is embodiment 1 Described first queue, can be to submit queue SQ to.Described 3rd queue can be to complete queue CQ.

Embodiment 3：

The embodiment of the present invention provides a kind of exchange method, as shown in figure 4, methods described includes following step Suddenly：

301st, HOST writes assignment instructions in the first queue in described HOST internal memory.

Wherein, described assignment instructions indicate the behaviour that non-volatile memory express passway NVMe equipment will execute Make；Described NVMe equipment is to be entered by quick Peripheral Component Interconnect PCIe bus with described HOST The ancillary equipment of row interaction.

302nd, described HOST writes the second queue in described HOST internal memory by triggering mark.

Described triggering mark is represented described HOST and has confirmed that and will be interacted with described NVMe equipment, Described interaction is that the described operation of described NVMe equipment execution needs and interacting that described HOST is carried out.

303rd, second queue described in described NVMe device polling.

304th, described NVMe equipment detects triggering mark in described second queue.

305th, described NVMe equipment obtains assignment instructions in described first queue, and execution task refers to The operation of order instruction.

Specifically, if described operate as writing data, described NVMe equipment execution is described to be operated specifically Including：

If described operate as reading data, described NVMe equipment executes described operation and specifically includes：Institute State NVMe equipment receive described HOST read data request, and by described continue data is activation to Described HOST；Described NVMe equipment receives the first interruption that described HOST sends, and will operate Complete to identify the 3rd queue writing in described HOST；Described operation completes mark and indicates described operation Complete, described first interrupts writing for indicating that described operation is completed mark by described NVMe equipment The 3rd queue in described HOST internal memory.

Wherein, described default interruption can be MSI-X, and described first interrupts being that DMA interrupts.

306th, described HOST obtains described operation and completes to identify, and confirms that described operation completes, then Mark will be completed and write described second queue.

Described operation completes mark and indicates that described operation completes.Described complete mark represent described HOST has confirmed that described interaction completes.

In implementing, it is that described HOST receives the default interruption that described NVMe equipment sends, And access described 3rd queue, described 3rd queue obtains described operation and completes to identify.

307th, described NVMe equipment detects in described second queue and completes to identify.

Exchange method provided in an embodiment of the present invention, triggering command is write internal memory by HOST, described NVMe equipment is polled to triggering command in the first queue in the internal memory of main frame HOST；Described Triggering command indicates that described HOST is had confirmed that and will be interacted with described NVMe equipment.Described NVMe equipment obtains assignment instructions, the operation of execution described assignment instructions instruction.NVMe equipment First queue in the internal memory of described HOST detects and completes to instruct；Described complete instruction and refer to Show that described HOST has confirmed that to complete with described NVMe equipment to interact.So, in HOST During interacting with NVMe equipment, it is to avoid the CPU of HOST directly operates NVMe equipment Depositor, thus avoiding the CPU of HOST that NVMe equipment side register manipulation is no responded Lead to system to hang dead situation to occur.Also will not lead even if NVMe equipment occurring and being unplugged suddenly Cause the situation of the CPU operation depositor no response of HOST, it is once to read and write that system only will be considered that Time-out, thus it is dead effectively to avoid the system that NVMe device reset causes to hang, realizes NVMe The hot plug of equipment.

Embodiment 4：

The embodiment of the present invention provides a kind of exchange method, is mainly used in NVMe equipment and hands over HOST Mutually, write data into NVMe equipment.As shown in figure 5, the method comprising the steps of：

401st, HOST writes command to SQ queue.

402nd, triggering command is write DQ (Doorbell Queue, doorbell queue) by HOST.

403rd, NVMe Controller (controller) from DQ repeating query to triggering command.

404th, NVMe Controller obtains SQ queue in the internal memory of HOST.

405th, NVMe Controller obtains assignment instructions in SQ queue.

406th, NVMe Controller operates the DMA engine of NVMe equipment side HOST's Data to be written is read in internal memory.

407th, NVMe Controller sends to distributed storage software after encapsulating data to be written.

408th, distributed storage software returns Response (response) to NVMe Controlle.

409th, operation is completed mark write CQ queue and discharges SQ queue by NVMe Controller.

410th, NVMe Controller sends MSI-X and interrupts to HOST.

411st, have no progeny during HOST receives and execute CQ queue.

Access CQ queue, obtain operation and complete to identify.

412nd, HOST will complete instruction write Doorbell queue.

413rd, NVMe Controller is polled to from Doorbell queue and completes to instruct, NVMe Controller discharges CQ queue.

So far, according to NVMe agreement, once complete between HOST and NVMe write data flow Journey just completes.

The embodiment of the present invention provides a kind of exchange method, during described NVMe equipment write data, it is to avoid The CPU of HOST directly operates the depositor of NVMe equipment, thus avoiding the CPU of HOST NVMe equipment side register manipulation is no responded and leads to system to hang dead situation appearance.Even if occurring NVMe equipment is unplugged suddenly the feelings of the CPU operation depositor no response being also not result in HOST Condition, it is once to read and write time-out, thus effectively avoiding NVMe device reset to cause that system only will be considered that System hang dead, realize the hot plug of NVMe equipment.

Embodiment 5：

The embodiment of the present invention provides a kind of exchange method, is mainly used in NVMe equipment and hands over HOST Mutually, HOST reads data in NVMe equipment.As shown in fig. 6, methods described includes following step Suddenly：

501st, HOST writes command to SQ queue.

502nd, triggering command is write Doorbell queue by HOST.

503rd, NVMe Controller is polled to triggering command from Doorbell queue.

504th, NVMe Controller obtains SQ queue in the internal memory of HOST.

505th, NVMe Controller obtains assignment instructions from SQ queue.

506th, NVMe Controller sends to distributed storage software after encapsulating the data that continues.

507th, distributed storage software returns Response.

508th, NVMe Controller operates the DMA engine of NVMe equipment side in distributed storage Read in software and continue data, and the data is activation that will continue is to HOST.

509th, HOST complete to continue data reception after return DMA and interrupt.

510th, operation is completed mark write CQ queue and discharges SQ queue by NVMe Controller.

511st, NVMe Controller sends MSI-X and interrupts to HOST.

512nd, have no progeny during HOST receives and execute CQ queue.

Access CQ queue, obtain operation and complete to identify.

513rd, HOST will complete instruction write Doorbell queue.

514th, NVMe Controller is polled to from Doorbell queue and completes to instruct, NVMe Controller discharges CQ queue.

So far, according to NVMe agreement, once complete time data stream between HOST and NVMe Journey just completes.

The embodiment of the present invention provides a kind of exchange method, when described NVMe equipment reads data, it is to avoid The CPU of HOST directly operates the depositor of NVMe equipment, thus avoiding the CPU of HOST NVMe equipment side register manipulation is no responded and leads to system to hang dead situation appearance.Even if occurring NVMe equipment is unplugged suddenly the feelings of the CPU operation depositor no response being also not result in HOST Condition, it is once to read and write time-out, thus effectively avoiding NVMe device reset to cause that system only will be considered that System hang dead, realize the hot plug of NVMe equipment.

Embodiment 6：

The embodiment of the present invention provides a kind of HOST, as shown in fig. 7, described HOST includes：Write Unit 601, confirmation unit 602.

Writing unit 601, for writing the first queue in described HOST internal memory by assignment instructions In, described assignment instructions indicate the operation that NVMe equipment will execute；Described NVMe equipment is The ancillary equipment being interacted by quick Peripheral Component Interconnect PCIe bus with described HOST.

Said write unit 601 is additionally operable to, and triggering mark is write in described HOST internal memory Second queue；Described triggering mark represents that described HOST has confirmed that will be quick with non-volatile memory Passage NVMe equipment interacts, and described interaction is that described NVMe equipment executes described operation Need and interacting that described HOST is carried out.

Confirmation unit 602, for confirming that described operation completes.

Said write unit 601 is additionally operable to, and confirms that described operation completes in described confirmation unit When, mark will be completed and write described first queue, the described mark that completes will have represented described HOST Confirm that described interaction completes.

Described confirmation unit 602 is specifically for described HOST receives described NVMe equipment and sends out The default interruption sent, accesses the 3rd queue in described HOST internal memory, operation is detected and complete Mark, then confirm that described operation completes.

HOST provided in an embodiment of the present invention, triggering command is write internal memory so that described NVMe equipment is polled to triggering command in the first queue in the internal memory of main frame HOST；Institute State triggering command and indicate that described HOST is had confirmed that and will be interacted with described NVMe equipment.Institute State NVMe equipment and obtain assignment instructions, the operation of execution described assignment instructions instruction.NVMe Equipment detects in the first queue in the internal memory of described HOST and completes to instruct；Described complete Instruction indicates that described HOST has confirmed that to complete with described NVMe equipment and interacts.So, exist During HOST is interacted with NVMe equipment, it is to avoid the CPU of HOST directly operates NVMe The depositor of equipment, thus avoid the CPU of HOST to NVMe equipment side register manipulation no Response leads to system to hang dead situation appearance.Even if NVMe equipment occurs be unplugged suddenly also not The situation of the CPU operation depositor no response of HOST can be led to, it is once that system only will be considered that Read-write time-out, thus it is dead effectively to avoid the system that NVMe device reset causes to hang, realizes The hot plug of NVMe equipment.

Embodiment 7：

The embodiment of the present invention provides a kind of NVMe equipment, as shown in figure 8, described HOST includes： Detector unit 701, acquiring unit 702, performance element 703.

Detector unit 701, for poll first queue；Described first queue is stored in main frame HOST Internal memory in.

Described detector unit 701 is additionally operable to, and triggering mark is detected in described first queue, Described triggering mark is represented described HOST and has confirmed that and will be interacted with described NVMe equipment； Described interaction is that described NVMe equipment execution operation needs and interacting that described HOST is carried out.

Acquiring unit 702, for obtaining assignment instructions；Described assignment instructions indicate described HOST Described operation by execution.

Performance element 703, for executing described operation.

Described detector unit 701 is additionally operable to, and detects and complete to identify in described first queue； The described mark that completes indicates that described HOST is had confirmed that and completed with described interaction, described completes to mark Knowledge is that described HOST confirms that described operation writes described first queue after completing.

Described acquiring unit 702 specifically for：Access the second queue in described HOST internal memory, Described assignment instructions are obtained in described second queue.

If operating as writing data, described performance element 703 specifically for：

Example：(1) NVMe Controller reads NVMe order from SQ.

(4) distributed storage software returns Response to NVMe Controller.

(5) operation is completed mark write the 3rd queue by NVMe Controller.

If operate for read data, described performance element 703 specifically for：

Example, (1) NVMe Controller reads NVMe order from SQ queue.

(3) distributed storage software returns Response.

Described detector unit 701 is specifically for first queue described in equipment active poll；

NVMe equipment provided in an embodiment of the present invention, first in the internal memory of main frame HOST It is polled to triggering command in queue；Described triggering command indicate described HOST have confirmed that by with institute State NVMe equipment to interact.Described NVMe equipment obtains assignment instructions, and execution is described to appoint The operation of business instruction instruction.NVMe equipment is in the first queue in the internal memory of described HOST Detect and complete to instruct；The described instruction described HOST of instruction that completes has confirmed that and described NVMe Equipment completes interaction.So, during HOST is interacted with NVMe equipment, it is to avoid The CPU of HOST directly operates the depositor of NVMe equipment, thus avoiding the CPU of HOST NVMe equipment side register manipulation is no responded and leads to system to hang dead situation appearance.Use Existing NVMe equipment is unplugged suddenly and is also not result in that the CPU operation depositor of HOST no responds Situation, system only will be considered that be once read and write time-out, thus effectively avoiding NVMe equipment The system causing that resets is hung extremely, realizes the hot plug of NVMe equipment.

Embodiment 8：

The embodiment of the present invention provides a kind of HOST, as shown in figure 9, described HOST includes：Process Device 801, system bus 802 and memorizer 803.

Wherein, processor 801 can be central processing unit (English：Central processing unit, Abbreviation：CPU).

Memorizer 803, for store program codes, and this program code is transferred to this processor 801, processor 801 executes following instructions according to program code.Memorizer 803 can include volatile Property memorizer (English：Volatile memory), such as random access memory (English： Random-access memory, abbreviation：RAM)；Memorizer 803 can also include non-volatile Property memorizer (English：Non-volatile memory), such as read only memory (English：read-only Memory, abbreviation：ROM), flash memory (English：Flash memory), hard disk (English Literary composition：Hard disk drive, abbreviation：HDD) or solid state hard disc (English：Solid-state drive, Abbreviation：SSD).Memorizer 803 can also include the combination of the memorizer of mentioned kind.Processor 801st, connected by system bus 802 between memorizer 803 and complete mutual communication.

Processor 801, for assignment instructions being write in the first queue in described HOST internal memory, Described assignment instructions indicate the operation that NVMe equipment will execute；Described NVMe equipment is and institute State the ancillary equipment that HOST is interacted by quick Peripheral Component Interconnect PCIe bus.

Described processor 801 is additionally operable to, and triggering mark is write the in described HOST internal memory Two queues；Described triggering mark is represented described HOST and has confirmed that and quickly will be led to non-volatile memory Road NVMe equipment interacts, and described interaction is that the described operation of described NVMe equipment execution needs Will be with interacting that described HOST is carried out.

Wherein, so-called interaction, when referring to that HOST instruction NVMe equipment will execute certain operation, NVMe equipment execution operation before, complete operation after, to carry out between NVMe equipment and HOST Interaction, to guarantee that NVMe equipment and HOST know a certain step flow process carrying out.As：HOST Write assignment instructions in a step 101, instruction NVMe equipment is write data, touches in write afterwards Issue of bidding documents know so that NVMe equipment to know that HOST has been acknowledged after triggering mark is detected described NVMe equipment will write data from the internal memory of HOST.

Confirm processor 801, for confirming that described operation completes, confirm that described operation completes When, mark will be completed and write described first queue, and described complete mark to represent described HOST true Recognize described interaction to complete.

Described processor 801 is specifically for described HOST receives described NVMe equipment and sends Default interruption, access described HOST internal memory in the 3rd queue, detect operation complete mark Know, then confirm that described operation completes.

Embodiment 9：

The embodiment of the present invention provides a kind of NVMe equipment, and as shown in Figure 10, described HOST includes： Processor 901, system bus 902 and memorizer 903.

Wherein, processor 901 can be central processing unit (English：Central processing unit, Abbreviation：CPU).

Memorizer 903, for store program codes, and this program code is transferred to this processor 901, processor 901 executes following instructions according to program code.Memorizer 903 can include volatile Property memorizer (English：Volatile memory), such as random access memory (English： Random-access memory, abbreviation：RAM)；Memorizer 903 can also include non-volatile Property memorizer (English：Non-volatile memory), such as read only memory (English：read-only Memory, abbreviation：ROM), flash memory (English：Flash memory), hard disk (English Literary composition：Hard disk drive, abbreviation：HDD) or solid state hard disc (English：Solid-state drive, Abbreviation：SSD).Memorizer 903 can also include the combination of the memorizer of mentioned kind.Processor 901st, connected by system bus 902 between memorizer 903 and complete mutual communication.

Processor 901, for poll first queue；Described first queue is stored in main frame HOST Internal memory in.Triggering mark is detected in described first queue, described triggering mark represents described HOST is had confirmed that and will be interacted with described NVMe equipment；Described interaction is described NVMe Equipment execution operation needs and interacting that described HOST is carried out.

Processor 901, for obtaining assignment instructions；Described assignment instructions indicate that described HOST will The described operation of execution.

Processor 901 is additionally operable to, and executes described operation.

Described processor 901 is additionally operable to, and detects and complete to identify in described first queue；Described Complete mark and indicate that described HOST has confirmed that and complete, the described mark that completes is institute with described interaction State HOST and confirm that described operation writes described first queue after completing.With described triggering mark Equally, the described mark that completes can also be one of described first queue address bit, for indicating State whether HOST has confirmed that described interaction completes.

Described processor 901 specifically for：Access the second queue in described HOST internal memory, Described assignment instructions are obtained in described second queue.

If operating as writing data, described processor 901 specifically for：

Example, 1) NVMe Controller reads NVMe order from SQ.

(4) distributed storage software returns Response to NVMe Controller.

(5) operation is completed mark write the 3rd queue by NVMe Controller.

If operate for read data, described processor 901 specifically for：

Example：(1) NVMe Controller reads NVMe order from SQ queue.

(3) distributed storage software returns Response.

Described processor 901 is specifically for first queue described in equipment active poll；

Embodiment 10：

The embodiment of the present invention provides a kind of physical machine system, as shown in figure 11, described physical machine system System is including HOST and NVMe equipment.

Specifically, the interaction inclusion of described HOST and NVMe equipment room：

Assignment instructions are write in the first queue in described HOST internal memory by described HOST, institute State the operation that assignment instructions indicate that non-volatile memory express passway NVMe equipment will execute.Described NVMe equipment is to be interacted by quick Peripheral Component Interconnect PCIe bus with described HOST Ancillary equipment.

Described HOST writes the second queue in described HOST internal memory by triggering mark；Described Triggering mark is represented described HOST and has confirmed that and will be interacted with described NVMe equipment, described Interaction needs and interacting that described HOST is carried out for the described operation of described NVMe equipment execution.

Second queue described in described NVMe device polling.

Described NVMe equipment detects triggering mark in described second queue.

Described NVMe equipment obtains assignment instructions in described first queue；The described operation of row.

It should be noted that the operation of described assignment instructions instruction can be specifically described NVMe Equipment reads data in the internal memory of described HOST, or, it is that described NVMe equipment receives HOST reads the request of data, and response data is sent to HOST.

If described operate as writing data, described NVMe equipment executes described operation and specifically includes：

If described operate as reading data, described NVMe equipment executes described operation and specifically includes：Institute State NVMe equipment receive described HOST read data request, and by described continue data is activation to Described HOST；Described NVMe equipment receives the first interruption that described HOST sends, and will operate Complete to identify the 3rd queue writing in described HOST；Described operation completes mark and indicates described operation Complete, described first interrupts writing for indicating that described operation is completed mark by described NVMe equipment The 3rd queue in described HOST internal memory；Described NVMe equipment sends default to described HOST Interrupt, the described HOST of instruction accesses described 3rd queue, confirm that described operation completes.

So, HOST receives to have no progeny in described presetting and will access the 3rd queue, obtains behaviour therein Complete to identify, and then mark will be completed and write described second queue.

First queue described in the present embodiment, can be to submit queue SQ to, the described in the present embodiment Two queues, can be doorbell queue DQ.Described 3rd queue can be to complete queue CQ.Described Default interruption can be MSI-X.

Physical machine system provided in an embodiment of the present invention, NVMe equipment is in the internal memory of main frame HOST In first queue in be polled to triggering command；Described triggering command indicates that described HOST has confirmed that To interact with described NVMe equipment.Described NVMe equipment obtains assignment instructions, execution The operation of described assignment instructions instruction.First team in the internal memory of described HOST for the NVMe equipment Detect in row and complete to instruct；Described complete instruction indicate described HOST have confirmed that with described NVMe equipment completes interaction.So, during HOST is interacted with NVMe equipment, The CPU avoiding HOST directly operates the depositor of NVMe equipment, thus avoiding HOST's CPU no responds to NVMe equipment side register manipulation and leads to system to hang dead situation appearance.I.e. Make to occur NVMe equipment and be unplugged suddenly to be also not result in the CPU operation depositor of HOST no The situation of response, it is once to read and write time-out, thus effectively avoiding NVMe to set that system only will be considered that The standby system causing that resets is hung extremely, realizes the hot plug of NVMe equipment.

Through the above description of the embodiments, those skilled in the art can be understood that Arrive, for convenience and simplicity of description, be only illustrated with the division of above-mentioned each functional module, real In the application of border, can as desired above-mentioned functions distribution be completed by different functional modules, will The internal structure of device is divided into different functional modules, described above all or part of to complete Function.The specific work process of the device of foregoing description, it is right in preceding method embodiment to may be referred to Answer process, will not be described here.

The described unit illustrating as separating component can be or may not be physically separate, Can be a physical location or multiple physical location as the part that unit shows, you can with positioned at one Individual place, or multiple different places can also be distributed to.Can select wherein according to the actual needs The purpose to realize this embodiment scheme for some or all of unit.In addition, each is real in the present invention Apply that each functional unit in example can be integrated in a processing unit or unit is independent It is physically present it is also possible to two or more units are integrated in a unit.Above-mentioned integrated list Unit both can be to be realized in the form of hardware, it would however also be possible to employ the form of SFU software functional unit is realized.

If described integrated unit is realized and as independent product using in the form of SFU software functional unit When selling or using, can be stored in a read/write memory medium.Based on such understanding, this Part or this technical side that the technical scheme of invention substantially contributes to prior art in other words The all or part of case can be embodied in the form of software product, and this software product is stored in one In storage medium, including some instructions with so that an equipment (can be single-chip microcomputer, chip etc.) Or processor (processor) executes all or part step of each embodiment methods described of the present invention Suddenly.And aforesaid storage medium includes：USB flash disk, portable hard drive, read only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disc or CD etc. are various can be with the medium of store program codes.

The above, the only specific embodiment of the present invention, but protection scope of the present invention not office Be limited to this, any those familiar with the art the invention discloses technical scope in, can Readily occur in change or replacement, all should be included within the scope of the present invention.Therefore, the present invention Protection domain should described be defined by scope of the claims.

Claims

1. a kind of exchange method is it is characterised in that include：

Assignment instructions are write in the first queue in described HOST internal memory by main frame HOST, described The operation that business instruction instruction non-volatile memory express passway NVMe equipment will execute；Described NVMe sets Standby is the ancillary equipment being interacted by quick Peripheral Component Interconnect PCIe bus with described HOST；

Described HOST writes the second queue in described HOST internal memory by triggering mark；Described triggering Mark is represented described HOST and has confirmed that and will be interacted with described NVMe equipment, and described interaction is institute Stating the described operation of NVMe equipment execution needs and interacting that described HOST is carried out；

Described HOST confirms that described operation completes, then will complete mark and write described first queue, Described complete mark and represent described HOST to have confirmed that described interaction completes.

2. method according to claim 1 is it is characterised in that described HOST confirms described behaviour Completed including：

Described HOST receives the default interruption that described NVMe equipment sends, and accesses in described HOST The 3rd queue in depositing, detects operation and completes to identify, then confirm that described operation completes；

3. a kind of exchange method is it is characterised in that include：

Non-volatile memory express passway NVMe device polling first queue；Described first queue is stored in In the internal memory of main frame HOST；

Described NVMe equipment detects triggering mark, described triggering mark generation in described first queue HOST described in table is had confirmed that and will be interacted with described NVMe equipment；Described interaction is described NVMe Equipment execution operation needs and interacting that described HOST is carried out；

Described NVMe equipment obtains assignment instructions；Described assignment instructions indicate that described NVMe equipment will The described operation of execution；

Described NVMe equipment executes described operation；

Described NVMe equipment detects in described first queue and completes to identify；The described mark that completes refers to Show that described HOST has confirmed that described interaction completes, the described mark that completes is that described HOST confirms institute State after operation completes and write described first queue.

4. method according to claim 3 is it is characterised in that the acquisition of described NVMe equipment is appointed Business instruction includes：

Described NVMe equipment accesses the second queue in described HOST internal memory, in described second queue The described assignment instructions of middle acquisition.

If the method 5. according to claim 3 or 4 is it is characterised in that described operate as writing number According to then described NVMe equipment executes described operation and specifically includes：

Described NVMe equipment obtains data to be written in the depositor of described HOST, and treats described Write data storage in the local memory of described NVMe equipment；

Described NVMe equipment will operate the 3rd queue completing in the mark described HOST of write；Described Operation completes mark and indicates that described operation completes；

Described NVMe equipment sends default interruption to described HOST, and the described HOST of instruction accesses Described 3rd queue, confirms that described operation completes.

If the method 6. according to claim 3 or 4 is it is characterised in that described operate as reading According to then described NVMe equipment executes described operation and specifically includes：

Described NVMe equipment receives the read data request of described HOST, and the described data that continues is sent out Give described HOST；

Described NVMe equipment receives the first interruption that described HOST sends, and operation is completed mark and writes Enter the 3rd queue in described HOST；Described operation completes mark and indicates that described operation completes, institute State the first interruption to be used for indicating that described operation is completed mark and writes described HOST by described NVMe equipment The 3rd queue in internal memory；

Described NVMe equipment sends default interruption to described HOST, and the described HOST of instruction accesses institute State the 3rd queue, confirm that described operation completes.

7. method according to claim 1 is it is characterised in that described NVMe device polling One queue includes：

First queue described in described NVMe equipment active poll；

Or, described NVMe equipment receives first described in poll after the configured information that described HOST sends Queue.

8. a kind of main frame HOST is it is characterised in that include：

Writing unit, for assignment instructions being write in the first queue in described HOST internal memory, institute State the operation that assignment instructions indicate that non-volatile memory express passway NVMe equipment will execute；Described NVMe Equipment is to be set by the periphery that quick Peripheral Component Interconnect PCIe bus interacts with described HOST Standby；

Said write unit is additionally operable to, and triggering mark is write the second queue in described HOST internal memory； Described triggering mark represent described HOST have confirmed that by with non-volatile memory express passway NVMe equipment Interact, described interaction is that the described operation of described NVMe equipment execution needs to enter with described HOST The interaction of row；

Confirmation unit, for confirming that described operation completes；

Said write unit is additionally operable to, and when described confirmation unit confirms that described operation completes, will complete Mark writes described first queue, described completes mark and represent described HOST to have had confirmed that described interaction Complete.

9. HOST according to claim 8 is it is characterised in that described confirmation unit is specifically used In,

10. a kind of non-volatile memory express passway NVMe equipment is it is characterised in that include：

Detector unit, for poll first queue；Described first queue is stored in the interior of main frame HOST In depositing；

Described detector unit is additionally operable to, and triggering mark, described triggering mark is detected in described first queue Knowledge is represented described HOST and has confirmed that and will be interacted with described NVMe equipment；Described interaction is described The execution operation of NVMe equipment needs and interacting that described HOST is carried out；

Acquiring unit, for obtaining assignment instructions；Described assignment instructions indicate that described HOST will execute Described operation；

Performance element, for executing described operation；

Described detector unit is additionally operable to, and detects and complete to identify in described first queue；Described complete mark Knowledge indicates that described HOST has confirmed that and completes with described interaction, the described mark that completes is described HOST Confirm that described operation writes described first queue after completing.

11. equipment according to claim 10 are it is characterised in that described acquiring unit is specifically used In：Access the second queue in described HOST internal memory, described second queue obtains described task Instruction.

If 12. equipment according to claim 10 or 11 are it is characterised in that described operation is Write data, then described performance element specifically for：

Obtain data to be written in the depositor of described HOST, and by described data storage to be written in institute State in the local memory of NVMe equipment；

Operation is completed to identify the 3rd queue writing in described HOST；Described operation completes mark and refers to Show that described operation completes；

If 13. equipment according to claim 10 or 11 are it is characterised in that described operation is Read data, then described performance element specifically for：

Receive the first interruption that described HOST sends, operation is completed mark and writes in described HOST The 3rd queue；Described operation completes mark and indicates that described operation completes, and described first interrupts for referring to Show that described operation is completed to identify the 3rd queue writing in described HOST internal memory by described NVMe equipment；

Send default interruption to described HOST, the described HOST of instruction accesses described 3rd queue, really Recognize described operation to complete.

14. equipment according to claim 10 are it is characterised in that described detector unit is specifically used In first queue described in equipment active poll；

A kind of 15. physical machine systems, including main frame HOST and non-volatile memory express passway NVMe Equipment it is characterised in that

Assignment instructions are write in the first queue in described HOST internal memory by described HOST, described The operation that business instruction instruction non-volatile memory express passway NVMe equipment will execute；Described NVMe sets Standby is the ancillary equipment being interacted by quick Peripheral Component Interconnect PCIe bus with described HOST；

Second queue described in described NVMe device polling；

Described NVMe equipment detects triggering mark in described second queue；

Described NVMe equipment executes described operation；

Described HOST obtains described operation and completes to identify, and confirms that described operation completes, then will complete Mark writes described second queue；Described operation completes mark and indicates that described operation completes；Described complete Mark represents described HOST and has confirmed that described interaction completes；